drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../display_mode_lib.h"
  27 #include "../display_mode_vba.h"
  28 #include "display_rq_dlg_calc_20.h"
  29
  30 // Function: dml20_rq_dlg_get_rq_params
  31 //  Calculate requestor related parameters that register definition agnostic
  32 //  (i.e. this layer does try to separate real values from register definition)
  33 // Input:
  34 //  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
  35 // Output:
  36 //  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
  37 //
  38 static void dml20_rq_dlg_get_rq_params(
  39                 struct display_mode_lib *mode_lib,
  40                 display_rq_params_st * rq_param,
  41                 const display_pipe_source_params_st pipe_src_param);
  42
  43 // Function: dml20_rq_dlg_get_dlg_params
  44 //  Calculate deadline related parameters
  45 //
  46 static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
  47                 const display_e2e_pipe_params_st *e2e_pipe_param,
  48                 const unsigned int num_pipes,
  49                 const unsigned int pipe_idx,
  50                 display_dlg_regs_st *disp_dlg_regs,
  51                 display_ttu_regs_st *disp_ttu_regs,
  52                 const display_rq_dlg_params_st rq_dlg_param,
  53                 const display_dlg_sys_params_st dlg_sys_param,
  54                 const bool cstate_en,
  55                 const bool pstate_en);
  56 /*
  57  * NOTE:
  58  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  59  *
  60  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  61  * ways. Unless there is something clearly wrong with it the code should
  62  * remain as-is as it provides us with a guarantee from HW that it is correct.
  63  */
  64
  65 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
  66                 double *refcyc_per_req_delivery_pre_cur,
  67                 double *refcyc_per_req_delivery_cur,
  68                 double refclk_freq_in_mhz,
  69                 double ref_freq_to_pix_freq,
  70                 double hscale_pixel_rate_l,
  71                 double hscl_ratio,
  72                 double vratio_pre_l,
  73                 double vratio_l,
  74                 unsigned int cur_width,
  75                 enum cursor_bpp cur_bpp);
  76
  77 #include "../dml_inline_defs.h"
  78
  79 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
  80 {
  81         unsigned int ret_val = 0;
  82
  83         if (source_format == dm_444_16) {
  84                 if (!is_chroma)
  85                         ret_val = 2;
  86         } else if (source_format == dm_444_32) {
  87                 if (!is_chroma)
  88                         ret_val = 4;
  89         } else if (source_format == dm_444_64) {
  90                 if (!is_chroma)
  91                         ret_val = 8;
  92         } else if (source_format == dm_420_8) {
  93                 if (is_chroma)
  94                         ret_val = 2;
  95                 else
  96                         ret_val = 1;
  97         } else if (source_format == dm_420_10) {
  98                 if (is_chroma)
  99                         ret_val = 4;
 100                 else
 101                         ret_val = 2;
 102         } else if (source_format == dm_444_8) {
 103                 ret_val = 1;
 104         }
 105         return ret_val;
 106 }
 107
 108 static bool is_dual_plane(enum source_format_class source_format)
 109 {
 110         bool ret_val = 0;
 111
 112         if ((source_format == dm_420_8) || (source_format == dm_420_10))
 113                 ret_val = 1;
 114
 115         return ret_val;
 116 }
 117
 118 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
 119                 double refclk_freq_in_mhz,
 120                 double pclk_freq_in_mhz,
 121                 bool odm_combine,
 122                 unsigned int recout_width,
 123                 unsigned int hactive,
 124                 double vratio,
 125                 double hscale_pixel_rate,
 126                 unsigned int delivery_width,
 127                 unsigned int req_per_swath_ub)
 128 {
 129         double refcyc_per_delivery = 0.0;
 130
 131         if (vratio <= 1.0) {
 132                 if (odm_combine)
 133                         refcyc_per_delivery = (double) refclk_freq_in_mhz
 134                                         * dml_min((double) recout_width, (double) hactive / 2.0)
 135                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 136                 else
 137                         refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
 138                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 139         } else {
 140                 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
 141                                 / (double) hscale_pixel_rate / (double) req_per_swath_ub;
 142         }
 143
 144         dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
 145         dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
 146         dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
 147         dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
 148         dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
 149         dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
 150
 151         return refcyc_per_delivery;
 152
 153 }
 154
 155 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
 156 {
 157         if (tile_size == dm_256k_tile)
 158                 return (256 * 1024);
 159         else if (tile_size == dm_64k_tile)
 160                 return (64 * 1024);
 161         else
 162                 return (4 * 1024);
 163 }
 164
 165 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
 166                 display_data_rq_regs_st *rq_regs,
 167                 const display_data_rq_sizing_params_st rq_sizing)
 168 {
 169         dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
 170         print__data_rq_sizing_params_st(mode_lib, rq_sizing);
 171
 172         rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
 173
 174         if (rq_sizing.min_chunk_bytes == 0)
 175                 rq_regs->min_chunk_size = 0;
 176         else
 177                 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
 178
 179         rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
 180         if (rq_sizing.min_meta_chunk_bytes == 0)
 181                 rq_regs->min_meta_chunk_size = 0;
 182         else
 183                 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
 184
 185         rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
 186         rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
 187 }
 188
 189 static void extract_rq_regs(struct display_mode_lib *mode_lib,
 190                 display_rq_regs_st *rq_regs,
 191                 const display_rq_params_st rq_param)
 192 {
 193         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 194         unsigned int detile_buf_plane1_addr = 0;
 195
 196         extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
 197
 198         rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
 199                         1) - 3;
 200
 201         if (rq_param.yuv420) {
 202                 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
 203                 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
 204                                 1) - 3;
 205         }
 206
 207         rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
 208         rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
 209
 210         // FIXME: take the max between luma, chroma chunk size?
 211         // okay for now, as we are setting chunk_bytes to 8kb anyways
 212         if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
 213                 rq_regs->drq_expansion_mode = 0;
 214         } else {
 215                 rq_regs->drq_expansion_mode = 2;
 216         }
 217         rq_regs->prq_expansion_mode = 1;
 218         rq_regs->mrq_expansion_mode = 1;
 219         rq_regs->crq_expansion_mode = 1;
 220
 221         if (rq_param.yuv420) {
 222                 if ((double) rq_param.misc.rq_l.stored_swath_bytes
 223                                 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
 224                         detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
 225                 } else {
 226                         detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
 227                                         256,
 228                                         0) / 64.0; // 2/3 to chroma
 229                 }
 230         }
 231         rq_regs->plane1_base_address = detile_buf_plane1_addr;
 232 }
 233
 234 static void handle_det_buf_split(struct display_mode_lib *mode_lib,
 235                 display_rq_params_st *rq_param,
 236                 const display_pipe_source_params_st pipe_src_param)
 237 {
 238         unsigned int total_swath_bytes = 0;
 239         unsigned int swath_bytes_l = 0;
 240         unsigned int swath_bytes_c = 0;
 241         unsigned int full_swath_bytes_packed_l = 0;
 242         unsigned int full_swath_bytes_packed_c = 0;
 243         bool req128_l = 0;
 244         bool req128_c = 0;
 245         bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
 246         bool surf_vert = (pipe_src_param.source_scan == dm_vert);
 247         unsigned int log2_swath_height_l = 0;
 248         unsigned int log2_swath_height_c = 0;
 249         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 250
 251         full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
 252         full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
 253
 254         if (rq_param->yuv420_10bpc) {
 255                 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
 256                                 256,
 257                                 1) + 256;
 258                 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
 259                                 256,
 260                                 1) + 256;
 261         }
 262
 263         if (rq_param->yuv420) {
 264                 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
 265
 266                 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
 267                         req128_l = 0;
 268                         req128_c = 0;
 269                         swath_bytes_l = full_swath_bytes_packed_l;
 270                         swath_bytes_c = full_swath_bytes_packed_c;
 271                 } else { //128b request (for luma only for yuv420 8bpc)
 272                         req128_l = 1;
 273                         req128_c = 0;
 274                         swath_bytes_l = full_swath_bytes_packed_l / 2;
 275                         swath_bytes_c = full_swath_bytes_packed_c;
 276                 }
 277                 // Note: assumption, the config that pass in will fit into
 278                 //       the detiled buffer.
 279         } else {
 280                 total_swath_bytes = 2 * full_swath_bytes_packed_l;
 281
 282                 if (total_swath_bytes <= detile_buf_size_in_bytes)
 283                         req128_l = 0;
 284                 else
 285                         req128_l = 1;
 286
 287                 swath_bytes_l = total_swath_bytes;
 288                 swath_bytes_c = 0;
 289         }
 290         rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
 291         rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
 292
 293         if (surf_linear) {
 294                 log2_swath_height_l = 0;
 295                 log2_swath_height_c = 0;
 296         } else if (!surf_vert) {
 297                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
 298                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
 299         } else {
 300                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
 301                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
 302         }
 303         rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
 304         rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
 305
 306         dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
 307         dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
 308         dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
 309                         __func__,
 310                         full_swath_bytes_packed_l);
 311         dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
 312                         __func__,
 313                         full_swath_bytes_packed_c);
 314 }
 315
 316 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
 317                 display_data_rq_dlg_params_st *rq_dlg_param,
 318                 display_data_rq_misc_params_st *rq_misc_param,
 319                 display_data_rq_sizing_params_st *rq_sizing_param,
 320                 unsigned int vp_width,
 321                 unsigned int vp_height,
 322                 unsigned int data_pitch,
 323                 unsigned int meta_pitch,
 324                 unsigned int source_format,
 325                 unsigned int tiling,
 326                 unsigned int macro_tile_size,
 327                 unsigned int source_scan,
 328                 unsigned int is_chroma)
 329 {
 330         bool surf_linear = (tiling == dm_sw_linear);
 331         bool surf_vert = (source_scan == dm_vert);
 332
 333         unsigned int bytes_per_element;
 334         unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
 335                         false);
 336         unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
 337                         true);
 338
 339         unsigned int blk256_width = 0;
 340         unsigned int blk256_height = 0;
 341
 342         unsigned int blk256_width_y = 0;
 343         unsigned int blk256_height_y = 0;
 344         unsigned int blk256_width_c = 0;
 345         unsigned int blk256_height_c = 0;
 346         unsigned int log2_bytes_per_element;
 347         unsigned int log2_blk256_width;
 348         unsigned int log2_blk256_height;
 349         unsigned int blk_bytes;
 350         unsigned int log2_blk_bytes;
 351         unsigned int log2_blk_height;
 352         unsigned int log2_blk_width;
 353         unsigned int log2_meta_req_bytes;
 354         unsigned int log2_meta_req_height;
 355         unsigned int log2_meta_req_width;
 356         unsigned int meta_req_width;
 357         unsigned int meta_req_height;
 358         unsigned int log2_meta_row_height;
 359         unsigned int meta_row_width_ub;
 360         unsigned int log2_meta_chunk_bytes;
 361         unsigned int log2_meta_chunk_height;
 362
 363         //full sized meta chunk width in unit of data elements
 364         unsigned int log2_meta_chunk_width;
 365         unsigned int log2_min_meta_chunk_bytes;
 366         unsigned int min_meta_chunk_width;
 367         unsigned int meta_chunk_width;
 368         unsigned int meta_chunk_per_row_int;
 369         unsigned int meta_row_remainder;
 370         unsigned int meta_chunk_threshold;
 371         unsigned int meta_blk_bytes;
 372         unsigned int meta_blk_height;
 373         unsigned int meta_blk_width;
 374         unsigned int meta_surface_bytes;
 375         unsigned int vmpg_bytes;
 376         unsigned int meta_pte_req_per_frame_ub;
 377         unsigned int meta_pte_bytes_per_frame_ub;
 378         const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
 379         const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
 380         const unsigned int pde_proc_buffer_size_64k_reqs =
 381                         mode_lib->ip.pde_proc_buffer_size_64k_reqs;
 382
 383         unsigned int log2_vmpg_height = 0;
 384         unsigned int log2_vmpg_width = 0;
 385         unsigned int log2_dpte_req_height_ptes = 0;
 386         unsigned int log2_dpte_req_height = 0;
 387         unsigned int log2_dpte_req_width = 0;
 388         unsigned int log2_dpte_row_height_linear = 0;
 389         unsigned int log2_dpte_row_height = 0;
 390         unsigned int log2_dpte_group_width = 0;
 391         unsigned int dpte_row_width_ub = 0;
 392         unsigned int dpte_req_height = 0;
 393         unsigned int dpte_req_width = 0;
 394         unsigned int dpte_group_width = 0;
 395         unsigned int log2_dpte_group_bytes = 0;
 396         unsigned int log2_dpte_group_length = 0;
 397         unsigned int pde_buf_entries;
 398         bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
 399
 400         Calculate256BBlockSizes((enum source_format_class)(source_format),
 401                         (enum dm_swizzle_mode)(tiling),
 402                         bytes_per_element_y,
 403                         bytes_per_element_c,
 404                         &blk256_height_y,
 405                         &blk256_height_c,
 406                         &blk256_width_y,
 407                         &blk256_width_c);
 408
 409         if (!is_chroma) {
 410                 blk256_width = blk256_width_y;
 411                 blk256_height = blk256_height_y;
 412                 bytes_per_element = bytes_per_element_y;
 413         } else {
 414                 blk256_width = blk256_width_c;
 415                 blk256_height = blk256_height_c;
 416                 bytes_per_element = bytes_per_element_c;
 417         }
 418
 419         log2_bytes_per_element = dml_log2(bytes_per_element);
 420
 421         dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
 422         dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
 423         dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
 424         dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
 425
 426         log2_blk256_width = dml_log2((double) blk256_width);
 427         log2_blk256_height = dml_log2((double) blk256_height);
 428         blk_bytes = surf_linear ?
 429                         256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
 430         log2_blk_bytes = dml_log2((double) blk_bytes);
 431         log2_blk_height = 0;
 432         log2_blk_width = 0;
 433
 434         // remember log rule
 435         // "+" in log is multiply
 436         // "-" in log is divide
 437         // "/2" is like square root
 438         // blk is vertical biased
 439         if (tiling != dm_sw_linear)
 440                 log2_blk_height = log2_blk256_height
 441                                 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
 442         else
 443                 log2_blk_height = 0;  // blk height of 1
 444
 445         log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
 446
 447         if (!surf_vert) {
 448                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
 449                                 + blk256_width;
 450                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
 451         } else {
 452                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
 453                                 + blk256_height;
 454                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
 455         }
 456
 457         if (!surf_vert)
 458                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
 459                                 * bytes_per_element;
 460         else
 461                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
 462                                 * bytes_per_element;
 463
 464         rq_misc_param->blk256_height = blk256_height;
 465         rq_misc_param->blk256_width = blk256_width;
 466
 467         // -------
 468         // meta
 469         // -------
 470         log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
 471
 472         // each 64b meta request for dcn is 8x8 meta elements and
 473         // a meta element covers one 256b block of the the data surface.
 474         log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
 475         log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
 476                         - log2_meta_req_height;
 477         meta_req_width = 1 << log2_meta_req_width;
 478         meta_req_height = 1 << log2_meta_req_height;
 479         log2_meta_row_height = 0;
 480         meta_row_width_ub = 0;
 481
 482         // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
 483         // calculate upper bound of the meta_row_width
 484         if (!surf_vert) {
 485                 log2_meta_row_height = log2_meta_req_height;
 486                 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
 487                                 + meta_req_width;
 488                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
 489         } else {
 490                 log2_meta_row_height = log2_meta_req_width;
 491                 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
 492                                 + meta_req_height;
 493                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
 494         }
 495         rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
 496
 497         rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
 498
 499         log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
 500         log2_meta_chunk_height = log2_meta_row_height;
 501
 502         //full sized meta chunk width in unit of data elements
 503         log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
 504                         - log2_meta_chunk_height;
 505         log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
 506         min_meta_chunk_width = 1
 507                         << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
 508                                         - log2_meta_chunk_height);
 509         meta_chunk_width = 1 << log2_meta_chunk_width;
 510         meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
 511         meta_row_remainder = meta_row_width_ub % meta_chunk_width;
 512         meta_chunk_threshold = 0;
 513         meta_blk_bytes = 4096;
 514         meta_blk_height = blk256_height * 64;
 515         meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
 516         meta_surface_bytes = meta_pitch
 517                         * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
 518                         * bytes_per_element / 256;
 519         vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
 520         meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
 521                         8 * vmpg_bytes,
 522                         1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
 523         meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
 524         rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
 525
 526         dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
 527         dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
 528         dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
 529         dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
 530                         __func__,
 531                         meta_pte_req_per_frame_ub);
 532         dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
 533                         __func__,
 534                         meta_pte_bytes_per_frame_ub);
 535
 536         if (!surf_vert)
 537                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
 538         else
 539                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
 540
 541         if (meta_row_remainder <= meta_chunk_threshold)
 542                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
 543         else
 544                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
 545
 546         // ------
 547         // dpte
 548         // ------
 549         if (surf_linear) {
 550                 log2_vmpg_height = 0;   // one line high
 551         } else {
 552                 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
 553         }
 554         log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
 555
 556         // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
 557         if (surf_linear) { //one 64B PTE request returns 8 PTEs
 558                 log2_dpte_req_height_ptes = 0;
 559                 log2_dpte_req_width = log2_vmpg_width + 3;
 560                 log2_dpte_req_height = 0;
 561         } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
 562                 //one 64B req gives 8x1 PTEs for 4KB tile
 563                 log2_dpte_req_height_ptes = 0;
 564                 log2_dpte_req_width = log2_blk_width + 3;
 565                 log2_dpte_req_height = log2_blk_height + 0;
 566         } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
 567                 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
 568                 log2_dpte_req_height_ptes = 4;
 569                 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
 570                 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
 571         } else { //64KB page size and must 64KB tile block
 572                  //one 64B req gives 8x1 PTEs for 64KB tile
 573                 log2_dpte_req_height_ptes = 0;
 574                 log2_dpte_req_width = log2_blk_width + 3;
 575                 log2_dpte_req_height = log2_blk_height + 0;
 576         }
 577
 578         // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
 579         // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
 580         // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
 581         //log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
 582         //log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
 583         dpte_req_height = 1 << log2_dpte_req_height;
 584         dpte_req_width = 1 << log2_dpte_req_width;
 585
 586         // calculate pitch dpte row buffer can hold
 587         // round the result down to a power of two.
 588         pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
 589         if (surf_linear) {
 590                 unsigned int dpte_row_height;
 591
 592                 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
 593                                                                                 / bytes_per_element,
 594                                                                 dpte_buf_in_pte_reqs
 595                                                                                 * dpte_req_width)
 596                                                                 / data_pitch),
 597                                 1);
 598
 599                 ASSERT(log2_dpte_row_height_linear >= 3);
 600
 601                 if (log2_dpte_row_height_linear > 7)
 602                         log2_dpte_row_height_linear = 7;
 603
 604                 log2_dpte_row_height = log2_dpte_row_height_linear;
 605                 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
 606                 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
 607                 dpte_row_height = 1 << log2_dpte_row_height;
 608                 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
 609                                 dpte_req_width,
 610                                 1) + dpte_req_width;
 611                 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 612         } else {
 613                 // the upper bound of the dpte_row_width without dependency on viewport position follows.
 614                 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
 615                 if (!surf_vert) {
 616                         log2_dpte_row_height = log2_dpte_req_height;
 617                         dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
 618                                         + dpte_req_width;
 619                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 620                 } else {
 621                         log2_dpte_row_height =
 622                                         (log2_blk_width < log2_dpte_req_width) ?
 623                                                         log2_blk_width : log2_dpte_req_width;
 624                         dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
 625                                         + dpte_req_height;
 626                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
 627                 }
 628         }
 629         if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
 630                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
 631         else
 632                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
 633
 634         rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
 635
 636         // the dpte_group_bytes is reduced for the specific case of vertical
 637         // access of a tile surface that has dpte request of 8x1 ptes.
 638         if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
 639                 rq_sizing_param->dpte_group_bytes = 512;
 640         else
 641                 //full size
 642                 rq_sizing_param->dpte_group_bytes = 2048;
 643
 644         //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
 645         log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
 646         log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
 647
 648         // full sized data pte group width in elements
 649         if (!surf_vert)
 650                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
 651         else
 652                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
 653
 654         //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
 655         if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
 656                 log2_dpte_group_width = log2_dpte_group_width - 1;
 657
 658         dpte_group_width = 1 << log2_dpte_group_width;
 659
 660         // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
 661         // the upper bound for the dpte groups per row is as follows.
 662         rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
 663                         1);
 664 }
 665
 666 static void get_surf_rq_param(struct display_mode_lib *mode_lib,
 667                 display_data_rq_sizing_params_st *rq_sizing_param,
 668                 display_data_rq_dlg_params_st *rq_dlg_param,
 669                 display_data_rq_misc_params_st *rq_misc_param,
 670                 const display_pipe_source_params_st pipe_src_param,
 671                 bool is_chroma)
 672 {
 673         bool mode_422 = 0;
 674         unsigned int vp_width = 0;
 675         unsigned int vp_height = 0;
 676         unsigned int data_pitch = 0;
 677         unsigned int meta_pitch = 0;
 678         unsigned int ppe = mode_422 ? 2 : 1;
 679
 680         // FIXME check if ppe apply for both luma and chroma in 422 case
 681         if (is_chroma) {
 682                 vp_width = pipe_src_param.viewport_width_c / ppe;
 683                 vp_height = pipe_src_param.viewport_height_c;
 684                 data_pitch = pipe_src_param.data_pitch_c;
 685                 meta_pitch = pipe_src_param.meta_pitch_c;
 686         } else {
 687                 vp_width = pipe_src_param.viewport_width / ppe;
 688                 vp_height = pipe_src_param.viewport_height;
 689                 data_pitch = pipe_src_param.data_pitch;
 690                 meta_pitch = pipe_src_param.meta_pitch;
 691         }
 692
 693         rq_sizing_param->chunk_bytes = 8192;
 694
 695         if (rq_sizing_param->chunk_bytes == 64 * 1024)
 696                 rq_sizing_param->min_chunk_bytes = 0;
 697         else
 698                 rq_sizing_param->min_chunk_bytes = 1024;
 699
 700         rq_sizing_param->meta_chunk_bytes = 2048;
 701         rq_sizing_param->min_meta_chunk_bytes = 256;
 702
 703         rq_sizing_param->mpte_group_bytes = 2048;
 704
 705         get_meta_and_pte_attr(mode_lib,
 706                         rq_dlg_param,
 707                         rq_misc_param,
 708                         rq_sizing_param,
 709                         vp_width,
 710                         vp_height,
 711                         data_pitch,
 712                         meta_pitch,
 713                         pipe_src_param.source_format,
 714                         pipe_src_param.sw_mode,
 715                         pipe_src_param.macro_tile_size,
 716                         pipe_src_param.source_scan,
 717                         is_chroma);
 718 }
 719
 720 static void dml20_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
 721                 display_rq_params_st *rq_param,
 722                 const display_pipe_source_params_st pipe_src_param)
 723 {
 724         // get param for luma surface
 725         rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
 726                         || pipe_src_param.source_format == dm_420_10;
 727         rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
 728
 729         get_surf_rq_param(mode_lib,
 730                         &(rq_param->sizing.rq_l),
 731                         &(rq_param->dlg.rq_l),
 732                         &(rq_param->misc.rq_l),
 733                         pipe_src_param,
 734                         0);
 735
 736         if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
 737                 // get param for chroma surface
 738                 get_surf_rq_param(mode_lib,
 739                                 &(rq_param->sizing.rq_c),
 740                                 &(rq_param->dlg.rq_c),
 741                                 &(rq_param->misc.rq_c),
 742                                 pipe_src_param,
 743                                 1);
 744         }
 745
 746         // calculate how to split the det buffer space between luma and chroma
 747         handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
 748         print__rq_params_st(mode_lib, *rq_param);
 749 }
 750
 751 void dml20_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
 752                 display_rq_regs_st *rq_regs,
 753                 const display_pipe_params_st pipe_param)
 754 {
 755         display_rq_params_st rq_param = {0};
 756
 757         memset(rq_regs, 0, sizeof(*rq_regs));
 758         dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
 759         extract_rq_regs(mode_lib, rq_regs, rq_param);
 760
 761         print__rq_regs_st(mode_lib, *rq_regs);
 762 }
 763
 764 // Note: currently taken in as is.
 765 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
 766 static void dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 767                 const display_e2e_pipe_params_st *e2e_pipe_param,
 768                 const unsigned int num_pipes,
 769                 const unsigned int pipe_idx,
 770                 display_dlg_regs_st *disp_dlg_regs,
 771                 display_ttu_regs_st *disp_ttu_regs,
 772                 const display_rq_dlg_params_st rq_dlg_param,
 773                 const display_dlg_sys_params_st dlg_sys_param,
 774                 const bool cstate_en,
 775                 const bool pstate_en)
 776 {
 777         const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 778         const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
 779         const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
 780         const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
 781         const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
 782         const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
 783
 784         // -------------------------
 785         // Section 1.15.2.1: OTG dependent Params
 786         // -------------------------
 787         // Timing
 788         unsigned int htotal = dst->htotal;
 789 //    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
 790         unsigned int hblank_end = dst->hblank_end;
 791         unsigned int vblank_start = dst->vblank_start;
 792         unsigned int vblank_end = dst->vblank_end;
 793         unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
 794
 795         double dppclk_freq_in_mhz = clks->dppclk_mhz;
 796         double dispclk_freq_in_mhz = clks->dispclk_mhz;
 797         double refclk_freq_in_mhz = clks->refclk_mhz;
 798         double pclk_freq_in_mhz = dst->pixel_rate_mhz;
 799         bool interlaced = dst->interlaced;
 800
 801         double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
 802
 803         double min_dcfclk_mhz;
 804         double t_calc_us;
 805         double min_ttu_vblank;
 806
 807         double min_dst_y_ttu_vblank;
 808         unsigned int dlg_vblank_start;
 809         bool dual_plane;
 810         bool mode_422;
 811         unsigned int access_dir;
 812         unsigned int vp_height_l;
 813         unsigned int vp_width_l;
 814         unsigned int vp_height_c;
 815         unsigned int vp_width_c;
 816
 817         // Scaling
 818         unsigned int htaps_l;
 819         unsigned int htaps_c;
 820         double hratio_l;
 821         double hratio_c;
 822         double vratio_l;
 823         double vratio_c;
 824         bool scl_enable;
 825
 826         double line_time_in_us;
 827         //    double vinit_l;
 828         //    double vinit_c;
 829         //    double vinit_bot_l;
 830         //    double vinit_bot_c;
 831
 832         //    unsigned int swath_height_l;
 833         unsigned int swath_width_ub_l;
 834         //    unsigned int dpte_bytes_per_row_ub_l;
 835         unsigned int dpte_groups_per_row_ub_l;
 836         //    unsigned int meta_pte_bytes_per_frame_ub_l;
 837         //    unsigned int meta_bytes_per_row_ub_l;
 838
 839         //    unsigned int swath_height_c;
 840         unsigned int swath_width_ub_c;
 841         //   unsigned int dpte_bytes_per_row_ub_c;
 842         unsigned int dpte_groups_per_row_ub_c;
 843
 844         unsigned int meta_chunks_per_row_ub_l;
 845         unsigned int meta_chunks_per_row_ub_c;
 846         unsigned int vupdate_offset;
 847         unsigned int vupdate_width;
 848         unsigned int vready_offset;
 849
 850         unsigned int dppclk_delay_subtotal;
 851         unsigned int dispclk_delay_subtotal;
 852         unsigned int pixel_rate_delay_subtotal;
 853
 854         unsigned int vstartup_start;
 855         unsigned int dst_x_after_scaler;
 856         unsigned int dst_y_after_scaler;
 857         double line_wait;
 858         double dst_y_prefetch;
 859         double dst_y_per_vm_vblank;
 860         double dst_y_per_row_vblank;
 861         double dst_y_per_vm_flip;
 862         double dst_y_per_row_flip;
 863         double min_dst_y_per_vm_vblank;
 864         double min_dst_y_per_row_vblank;
 865         double lsw;
 866         double vratio_pre_l;
 867         double vratio_pre_c;
 868         unsigned int req_per_swath_ub_l;
 869         unsigned int req_per_swath_ub_c;
 870         unsigned int meta_row_height_l;
 871         unsigned int meta_row_height_c;
 872         unsigned int swath_width_pixels_ub_l;
 873         unsigned int swath_width_pixels_ub_c;
 874         unsigned int scaler_rec_in_width_l;
 875         unsigned int scaler_rec_in_width_c;
 876         unsigned int dpte_row_height_l;
 877         unsigned int dpte_row_height_c;
 878         double hscale_pixel_rate_l;
 879         double hscale_pixel_rate_c;
 880         double min_hratio_fact_l;
 881         double min_hratio_fact_c;
 882         double refcyc_per_line_delivery_pre_l;
 883         double refcyc_per_line_delivery_pre_c;
 884         double refcyc_per_line_delivery_l;
 885         double refcyc_per_line_delivery_c;
 886
 887         double refcyc_per_req_delivery_pre_l;
 888         double refcyc_per_req_delivery_pre_c;
 889         double refcyc_per_req_delivery_l;
 890         double refcyc_per_req_delivery_c;
 891
 892         unsigned int full_recout_width;
 893         double xfc_transfer_delay;
 894         double xfc_precharge_delay;
 895         double xfc_remote_surface_flip_latency;
 896         double xfc_dst_y_delta_drq_limit;
 897         double xfc_prefetch_margin;
 898         double refcyc_per_req_delivery_pre_cur0;
 899         double refcyc_per_req_delivery_cur0;
 900         double refcyc_per_req_delivery_pre_cur1;
 901         double refcyc_per_req_delivery_cur1;
 902
 903         memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
 904         memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
 905
 906         dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
 907         dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
 908
 909         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 910         dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
 911         dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
 912         dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
 913         dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
 914         ASSERT(ref_freq_to_pix_freq < 4.0);
 915
 916         disp_dlg_regs->ref_freq_to_pix_freq =
 917                         (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
 918         disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
 919                         * dml_pow(2, 8));
 920         disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
 921         disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
 922                         * (double) ref_freq_to_pix_freq);
 923         ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
 924
 925         min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
 926         t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
 927         min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
 928
 929         min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
 930         dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
 931
 932         disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
 933                         + min_dst_y_ttu_vblank) * dml_pow(2, 2));
 934         ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
 935
 936         dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
 937                         __func__,
 938                         min_dcfclk_mhz);
 939         dml_print("DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
 940                         __func__,
 941                         min_ttu_vblank);
 942         dml_print("DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
 943                         __func__,
 944                         min_dst_y_ttu_vblank);
 945         dml_print("DML_DLG: %s: t_calc_us                              = %3.2f\n",
 946                         __func__,
 947                         t_calc_us);
 948         dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
 949                         __func__,
 950                         disp_dlg_regs->min_dst_y_next_start);
 951         dml_print("DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
 952                         __func__,
 953                         ref_freq_to_pix_freq);
 954
 955         // -------------------------
 956         // Section 1.15.2.2: Prefetch, Active and TTU
 957         // -------------------------
 958         // Prefetch Calc
 959         // Source
 960 //             dcc_en              = src.dcc;
 961         dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
 962         mode_422 = 0; // FIXME
 963         access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
 964 //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
 965 //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
 966         vp_height_l = src->viewport_height;
 967         vp_width_l = src->viewport_width;
 968         vp_height_c = src->viewport_height_c;
 969         vp_width_c = src->viewport_width_c;
 970
 971         // Scaling
 972         htaps_l = taps->htaps;
 973         htaps_c = taps->htaps_c;
 974         hratio_l = scl->hscl_ratio;
 975         hratio_c = scl->hscl_ratio_c;
 976         vratio_l = scl->vscl_ratio;
 977         vratio_c = scl->vscl_ratio_c;
 978         scl_enable = scl->scl_enable;
 979
 980         line_time_in_us = (htotal / pclk_freq_in_mhz);
 981 //     vinit_l         = scl.vinit;
 982 //     vinit_c         = scl.vinit_c;
 983 //     vinit_bot_l     = scl.vinit_bot;
 984 //     vinit_bot_c     = scl.vinit_bot_c;
 985
 986 //    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;
 987         swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
 988 //    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
 989         dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
 990 //    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
 991 //    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
 992
 993 //    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;
 994         swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
 995         //   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
 996         dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
 997
 998         meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
 999         meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
1000         vupdate_offset = dst->vupdate_offset;
1001         vupdate_width = dst->vupdate_width;
1002         vready_offset = dst->vready_offset;
1003
1004         dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
1005         dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
1006
1007         if (scl_enable)
1008                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
1009         else
1010                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
1011
1012         dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
1013                         + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
1014
1015         if (dout->dsc_enable) {
1016                 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1017
1018                 dispclk_delay_subtotal += dsc_delay;
1019         }
1020
1021         pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
1022                         + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
1023
1024         vstartup_start = dst->vstartup_start;
1025         if (interlaced) {
1026                 if (vstartup_start / 2.0
1027                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1028                                 <= vblank_end / 2.0)
1029                         disp_dlg_regs->vready_after_vcount0 = 1;
1030                 else
1031                         disp_dlg_regs->vready_after_vcount0 = 0;
1032         } else {
1033                 if (vstartup_start
1034                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1035                                 <= vblank_end)
1036                         disp_dlg_regs->vready_after_vcount0 = 1;
1037                 else
1038                         disp_dlg_regs->vready_after_vcount0 = 0;
1039         }
1040
1041         // TODO: Where is this coming from?
1042         if (interlaced)
1043                 vstartup_start = vstartup_start / 2;
1044
1045         // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
1046         if (vstartup_start >= min_vblank) {
1047                 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1048                                 __func__,
1049                                 vblank_start,
1050                                 vblank_end);
1051                 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1052                                 __func__,
1053                                 vstartup_start,
1054                                 min_vblank);
1055                 min_vblank = vstartup_start + 1;
1056                 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1057                                 __func__,
1058                                 vstartup_start,
1059                                 min_vblank);
1060         }
1061
1062         dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1063         dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1064
1065         dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
1066         dml_print("DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
1067                         __func__,
1068                         pixel_rate_delay_subtotal);
1069         dml_print("DML_DLG: %s: dst_x_after_scaler                     = %d\n",
1070                         __func__,
1071                         dst_x_after_scaler);
1072         dml_print("DML_DLG: %s: dst_y_after_scaler                     = %d\n",
1073                         __func__,
1074                         dst_y_after_scaler);
1075
1076         // Lwait
1077         line_wait = mode_lib->soc.urgent_latency_us;
1078         if (cstate_en)
1079                 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
1080         if (pstate_en)
1081                 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
1082                                                 + mode_lib->soc.urgent_latency_us,
1083                                 line_wait);
1084         line_wait = line_wait / line_time_in_us;
1085
1086         dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1087         dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1088
1089         dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
1090                         e2e_pipe_param,
1091                         num_pipes,
1092                         pipe_idx);
1093         dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
1094                         e2e_pipe_param,
1095                         num_pipes,
1096                         pipe_idx);
1097         dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1098         dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1099
1100         min_dst_y_per_vm_vblank = 8.0;
1101         min_dst_y_per_row_vblank = 16.0;
1102
1103         // magic!
1104         if (htotal <= 75) {
1105                 min_vblank = 300;
1106                 min_dst_y_per_vm_vblank = 100.0;
1107                 min_dst_y_per_row_vblank = 100.0;
1108         }
1109
1110         dml_print("DML_DLG: %s: dst_y_per_vm_vblank    = %3.2f\n", __func__, dst_y_per_vm_vblank);
1111         dml_print("DML_DLG: %s: dst_y_per_row_vblank   = %3.2f\n", __func__, dst_y_per_row_vblank);
1112
1113         ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
1114         ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
1115
1116         ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1117         lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
1118
1119         dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
1120
1121         vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1122         vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1123
1124         dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
1125         dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
1126
1127         // Active
1128         req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1129         req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1130         meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1131         meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
1132         swath_width_pixels_ub_l = 0;
1133         swath_width_pixels_ub_c = 0;
1134         scaler_rec_in_width_l = 0;
1135         scaler_rec_in_width_c = 0;
1136         dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1137         dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
1138
1139         if (mode_422) {
1140                 swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
1141                 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1142         } else {
1143                 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1144                 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1145         }
1146
1147         hscale_pixel_rate_l = 0.;
1148         hscale_pixel_rate_c = 0.;
1149         min_hratio_fact_l = 1.0;
1150         min_hratio_fact_c = 1.0;
1151
1152         if (htaps_l <= 1)
1153                 min_hratio_fact_l = 2.0;
1154         else if (htaps_l <= 6) {
1155                 if ((hratio_l * 2.0) > 4.0)
1156                         min_hratio_fact_l = 4.0;
1157                 else
1158                         min_hratio_fact_l = hratio_l * 2.0;
1159         } else {
1160                 if (hratio_l > 4.0)
1161                         min_hratio_fact_l = 4.0;
1162                 else
1163                         min_hratio_fact_l = hratio_l;
1164         }
1165
1166         hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1167
1168         if (htaps_c <= 1)
1169                 min_hratio_fact_c = 2.0;
1170         else if (htaps_c <= 6) {
1171                 if ((hratio_c * 2.0) > 4.0)
1172                         min_hratio_fact_c = 4.0;
1173                 else
1174                         min_hratio_fact_c = hratio_c * 2.0;
1175         } else {
1176                 if (hratio_c > 4.0)
1177                         min_hratio_fact_c = 4.0;
1178                 else
1179                         min_hratio_fact_c = hratio_c;
1180         }
1181
1182         hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1183
1184         refcyc_per_line_delivery_pre_l = 0.;
1185         refcyc_per_line_delivery_pre_c = 0.;
1186         refcyc_per_line_delivery_l = 0.;
1187         refcyc_per_line_delivery_c = 0.;
1188
1189         refcyc_per_req_delivery_pre_l = 0.;
1190         refcyc_per_req_delivery_pre_c = 0.;
1191         refcyc_per_req_delivery_l = 0.;
1192         refcyc_per_req_delivery_c = 0.;
1193
1194         full_recout_width = 0;
1195         // In ODM
1196         if (src->is_hsplit) {
1197                 // This "hack"  is only allowed (and valid) for MPC combine. In ODM
1198                 // combine, you MUST specify the full_recout_width...according to Oswin
1199                 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1200                         dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
1201                                         __func__);
1202                         full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1203                 } else
1204                         full_recout_width = dst->full_recout_width;
1205         } else
1206                 full_recout_width = dst->recout_width;
1207
1208         // As of DCN2, mpc_combine and odm_combine are mutually exclusive
1209         refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1210                         refclk_freq_in_mhz,
1211                         pclk_freq_in_mhz,
1212                         dst->odm_combine,
1213                         full_recout_width,
1214                         dst->hactive,
1215                         vratio_pre_l,
1216                         hscale_pixel_rate_l,
1217                         swath_width_pixels_ub_l,
1218                         1); // per line
1219
1220         refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
1221                         refclk_freq_in_mhz,
1222                         pclk_freq_in_mhz,
1223                         dst->odm_combine,
1224                         full_recout_width,
1225                         dst->hactive,
1226                         vratio_l,
1227                         hscale_pixel_rate_l,
1228                         swath_width_pixels_ub_l,
1229                         1); // per line
1230
1231         dml_print("DML_DLG: %s: full_recout_width              = %d\n",
1232                         __func__,
1233                         full_recout_width);
1234         dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
1235                         __func__,
1236                         hscale_pixel_rate_l);
1237         dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
1238                         __func__,
1239                         refcyc_per_line_delivery_pre_l);
1240         dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
1241                         __func__,
1242                         refcyc_per_line_delivery_l);
1243
1244         if (dual_plane) {
1245                 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1246                                 refclk_freq_in_mhz,
1247                                 pclk_freq_in_mhz,
1248                                 dst->odm_combine,
1249                                 full_recout_width,
1250                                 dst->hactive,
1251                                 vratio_pre_c,
1252                                 hscale_pixel_rate_c,
1253                                 swath_width_pixels_ub_c,
1254                                 1); // per line
1255
1256                 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
1257                                 refclk_freq_in_mhz,
1258                                 pclk_freq_in_mhz,
1259                                 dst->odm_combine,
1260                                 full_recout_width,
1261                                 dst->hactive,
1262                                 vratio_c,
1263                                 hscale_pixel_rate_c,
1264                                 swath_width_pixels_ub_c,
1265                                 1);  // per line
1266
1267                 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
1268                                 __func__,
1269                                 refcyc_per_line_delivery_pre_c);
1270                 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
1271                                 __func__,
1272                                 refcyc_per_line_delivery_c);
1273         }
1274
1275         // TTU - Luma / Chroma
1276         if (access_dir) {  // vertical access
1277                 scaler_rec_in_width_l = vp_height_l;
1278                 scaler_rec_in_width_c = vp_height_c;
1279         } else {
1280                 scaler_rec_in_width_l = vp_width_l;
1281                 scaler_rec_in_width_c = vp_width_c;
1282         }
1283
1284         refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1285                         refclk_freq_in_mhz,
1286                         pclk_freq_in_mhz,
1287                         dst->odm_combine,
1288                         full_recout_width,
1289                         dst->hactive,
1290                         vratio_pre_l,
1291                         hscale_pixel_rate_l,
1292                         scaler_rec_in_width_l,
1293                         req_per_swath_ub_l);  // per req
1294         refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
1295                         refclk_freq_in_mhz,
1296                         pclk_freq_in_mhz,
1297                         dst->odm_combine,
1298                         full_recout_width,
1299                         dst->hactive,
1300                         vratio_l,
1301                         hscale_pixel_rate_l,
1302                         scaler_rec_in_width_l,
1303                         req_per_swath_ub_l);  // per req
1304
1305         dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
1306                         __func__,
1307                         refcyc_per_req_delivery_pre_l);
1308         dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
1309                         __func__,
1310                         refcyc_per_req_delivery_l);
1311
1312         ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
1313         ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1314
1315         if (dual_plane) {
1316                 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1317                                 refclk_freq_in_mhz,
1318                                 pclk_freq_in_mhz,
1319                                 dst->odm_combine,
1320                                 full_recout_width,
1321                                 dst->hactive,
1322                                 vratio_pre_c,
1323                                 hscale_pixel_rate_c,
1324                                 scaler_rec_in_width_c,
1325                                 req_per_swath_ub_c);  // per req
1326                 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
1327                                 refclk_freq_in_mhz,
1328                                 pclk_freq_in_mhz,
1329                                 dst->odm_combine,
1330                                 full_recout_width,
1331                                 dst->hactive,
1332                                 vratio_c,
1333                                 hscale_pixel_rate_c,
1334                                 scaler_rec_in_width_c,
1335                                 req_per_swath_ub_c);  // per req
1336
1337                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
1338                                 __func__,
1339                                 refcyc_per_req_delivery_pre_c);
1340                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
1341                                 __func__,
1342                                 refcyc_per_req_delivery_c);
1343
1344                 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
1345                 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1346         }
1347
1348         // XFC
1349         xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1350         xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
1351                         e2e_pipe_param,
1352                         num_pipes,
1353                         pipe_idx);
1354         xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
1355                         e2e_pipe_param,
1356                         num_pipes,
1357                         pipe_idx);
1358         xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
1359         xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
1360                         e2e_pipe_param,
1361                         num_pipes,
1362                         pipe_idx);
1363
1364         // TTU - Cursor
1365         refcyc_per_req_delivery_pre_cur0 = 0.0;
1366         refcyc_per_req_delivery_cur0 = 0.0;
1367         if (src->num_cursors > 0) {
1368                 calculate_ttu_cursor(mode_lib,
1369                                 &refcyc_per_req_delivery_pre_cur0,
1370                                 &refcyc_per_req_delivery_cur0,
1371                                 refclk_freq_in_mhz,
1372                                 ref_freq_to_pix_freq,
1373                                 hscale_pixel_rate_l,
1374                                 scl->hscl_ratio,
1375                                 vratio_pre_l,
1376                                 vratio_l,
1377                                 src->cur0_src_width,
1378                                 (enum cursor_bpp)(src->cur0_bpp));
1379         }
1380
1381         refcyc_per_req_delivery_pre_cur1 = 0.0;
1382         refcyc_per_req_delivery_cur1 = 0.0;
1383         if (src->num_cursors > 1) {
1384                 calculate_ttu_cursor(mode_lib,
1385                                 &refcyc_per_req_delivery_pre_cur1,
1386                                 &refcyc_per_req_delivery_cur1,
1387                                 refclk_freq_in_mhz,
1388                                 ref_freq_to_pix_freq,
1389                                 hscale_pixel_rate_l,
1390                                 scl->hscl_ratio,
1391                                 vratio_pre_l,
1392                                 vratio_l,
1393                                 src->cur1_src_width,
1394                                 (enum cursor_bpp)(src->cur1_bpp));
1395         }
1396
1397         // TTU - Misc
1398         // all hard-coded
1399
1400         // Assignment to register structures
1401         disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1402         disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1403         ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
1404         disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1405         disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1406         disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1407         disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1408         disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1409
1410         disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1411         disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1412
1413         disp_dlg_regs->refcyc_per_pte_group_vblank_l =
1414                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1415                                         * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1416         ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
1417
1418         if (dual_plane) {
1419                 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
1420                                 * (double) htotal * ref_freq_to_pix_freq
1421                                 / (double) dpte_groups_per_row_ub_c);
1422                 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
1423                                                 < (unsigned int) dml_pow(2, 13));
1424         }
1425
1426         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
1427                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1428                                         * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1429         ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
1430
1431         disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
1432                         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1433
1434         disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1435                         * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1436         disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1437                         * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1438
1439         if (dual_plane) {
1440                 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1441                                 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1442                 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
1443                                 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1444         }
1445
1446         disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
1447                         / (double) vratio_l * dml_pow(2, 2));
1448         ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
1449
1450         if (dual_plane) {
1451                 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
1452                                 / (double) vratio_c * dml_pow(2, 2));
1453                 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1454                         dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1455                                         __func__,
1456                                         disp_dlg_regs->dst_y_per_pte_row_nom_c,
1457                                         (unsigned int) dml_pow(2, 17) - 1);
1458                 }
1459         }
1460
1461         disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
1462                         / (double) vratio_l * dml_pow(2, 2));
1463         ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
1464
1465         disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1466
1467         disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
1468                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1469                         / (double) dpte_groups_per_row_ub_l);
1470         if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1471                 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1472         disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
1473                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1474                         / (double) meta_chunks_per_row_ub_l);
1475         if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1476                 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1477
1478         if (dual_plane) {
1479                 disp_dlg_regs->refcyc_per_pte_group_nom_c =
1480                                 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c
1481                                                 * (double) htotal * ref_freq_to_pix_freq
1482                                                 / (double) dpte_groups_per_row_ub_c);
1483                 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1484                         disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1485
1486                 // TODO: Is this the right calculation? Does htotal need to be halved?
1487                 disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
1488                                 (unsigned int) ((double) meta_row_height_c / (double) vratio_c
1489                                                 * (double) htotal * ref_freq_to_pix_freq
1490                                                 / (double) meta_chunks_per_row_ub_c);
1491                 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1492                         disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1493         }
1494
1495         disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
1496                         1);
1497         disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
1498                         1);
1499         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
1500         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
1501
1502         disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
1503                         1);
1504         disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
1505                         1);
1506         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
1507         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
1508
1509         disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1510         disp_dlg_regs->dst_y_offset_cur0 = 0;
1511         disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1512         disp_dlg_regs->dst_y_offset_cur1 = 0;
1513
1514         disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
1515         disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
1516         disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
1517         disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
1518                         1);
1519
1520         // slave has to have this value also set to off
1521         if (src->xfc_enable && !src->xfc_slave)
1522                 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1523         else
1524                 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1525
1526         disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1527                         * dml_pow(2, 10));
1528         disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1529                         * dml_pow(2, 10));
1530         disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
1531                         * dml_pow(2, 10));
1532         disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1533                         * dml_pow(2, 10));
1534         disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1535                         (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1536         disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
1537                         * dml_pow(2, 10));
1538         disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1539                         (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1540         disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
1541                         * dml_pow(2, 10));
1542         disp_ttu_regs->qos_level_low_wm = 0;
1543         ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1544         disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1545                         * ref_freq_to_pix_freq);
1546         /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
1547
1548         disp_ttu_regs->qos_level_flip = 14;
1549         disp_ttu_regs->qos_level_fixed_l = 8;
1550         disp_ttu_regs->qos_level_fixed_c = 8;
1551         disp_ttu_regs->qos_level_fixed_cur0 = 8;
1552         disp_ttu_regs->qos_ramp_disable_l = 0;
1553         disp_ttu_regs->qos_ramp_disable_c = 0;
1554         disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1555
1556         disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1557         ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1558
1559         print__ttu_regs_st(mode_lib, *disp_ttu_regs);
1560         print__dlg_regs_st(mode_lib, *disp_dlg_regs);
1561 }
1562
1563 void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
1564                 display_dlg_regs_st *dlg_regs,
1565                 display_ttu_regs_st *ttu_regs,
1566                 display_e2e_pipe_params_st *e2e_pipe_param,
1567                 const unsigned int num_pipes,
1568                 const unsigned int pipe_idx,
1569                 const bool cstate_en,
1570                 const bool pstate_en,
1571                 const bool vm_en,
1572                 const bool ignore_viewport_pos,
1573                 const bool immediate_flip_support)
1574 {
1575         display_rq_params_st rq_param = {0};
1576         display_dlg_sys_params_st dlg_sys_param = {0};
1577
1578         // Get watermark and Tex.
1579         dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1580         dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
1581                         e2e_pipe_param,
1582                         num_pipes);
1583         dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1584         dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1585         dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1586         dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1587         dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
1588                         e2e_pipe_param,
1589                         num_pipes);
1590         dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
1591                         e2e_pipe_param,
1592                         num_pipes);
1593         dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
1594                         / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
1595
1596         print__dlg_sys_params_st(mode_lib, dlg_sys_param);
1597
1598         // system parameter calculation done
1599
1600         dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1601         dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
1602         dml20_rq_dlg_get_dlg_params(mode_lib,
1603                         e2e_pipe_param,
1604                         num_pipes,
1605                         pipe_idx,
1606                         dlg_regs,
1607                         ttu_regs,
1608                         rq_param.dlg,
1609                         dlg_sys_param,
1610                         cstate_en,
1611                         pstate_en);
1612         dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1613 }
1614
1615 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
1616                 double *refcyc_per_req_delivery_pre_cur,
1617                 double *refcyc_per_req_delivery_cur,
1618                 double refclk_freq_in_mhz,
1619                 double ref_freq_to_pix_freq,
1620                 double hscale_pixel_rate_l,
1621                 double hscl_ratio,
1622                 double vratio_pre_l,
1623                 double vratio_l,
1624                 unsigned int cur_width,
1625                 enum cursor_bpp cur_bpp)
1626 {
1627         unsigned int cur_src_width = cur_width;
1628         unsigned int cur_req_size = 0;
1629         unsigned int cur_req_width = 0;
1630         double cur_width_ub = 0.0;
1631         double cur_req_per_width = 0.0;
1632         double hactive_cur = 0.0;
1633
1634         ASSERT(cur_src_width <= 256);
1635
1636         *refcyc_per_req_delivery_pre_cur = 0.0;
1637         *refcyc_per_req_delivery_cur = 0.0;
1638         if (cur_src_width > 0) {
1639                 unsigned int cur_bit_per_pixel = 0;
1640
1641                 if (cur_bpp == dm_cur_2bit) {
1642                         cur_req_size = 64; // byte
1643                         cur_bit_per_pixel = 2;
1644                 } else { // 32bit
1645                         cur_bit_per_pixel = 32;
1646                         if (cur_src_width >= 1 && cur_src_width <= 16)
1647                                 cur_req_size = 64;
1648                         else if (cur_src_width >= 17 && cur_src_width <= 31)
1649                                 cur_req_size = 128;
1650                         else
1651                                 cur_req_size = 256;
1652                 }
1653
1654                 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
1655                 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
1656                                 * (double) cur_req_width;
1657                 cur_req_per_width = cur_width_ub / (double) cur_req_width;
1658                 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
1659
1660                 if (vratio_pre_l <= 1.0) {
1661                         *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
1662                                         / (double) cur_req_per_width;
1663                 } else {
1664                         *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
1665                                         * (double) cur_src_width / hscale_pixel_rate_l
1666                                         / (double) cur_req_per_width;
1667                 }
1668
1669                 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
1670
1671                 if (vratio_l <= 1.0) {
1672                         *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
1673                                         / (double) cur_req_per_width;
1674                 } else {
1675                         *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
1676                                         * (double) cur_src_width / hscale_pixel_rate_l
1677                                         / (double) cur_req_per_width;
1678                 }
1679
1680                 dml_print("DML_DLG: %s: cur_req_width                     = %d\n",
1681                                 __func__,
1682                                 cur_req_width);
1683                 dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n",
1684                                 __func__,
1685                                 cur_width_ub);
1686                 dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
1687                                 __func__,
1688                                 cur_req_per_width);
1689                 dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n",
1690                                 __func__,
1691                                 hactive_cur);
1692                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
1693                                 __func__,
1694                                 *refcyc_per_req_delivery_pre_cur);
1695                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
1696                                 __func__,
1697                                 *refcyc_per_req_delivery_cur);
1698
1699                 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
1700         }
1701 }