drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "core_types.h"
  29
  30 #include "reg_helper.h"
  31 #include "dcn20_dpp.h"
  32 #include "basics/conversion.h"
  33
  34 #define NUM_PHASES    64
  35 #define HORZ_MAX_TAPS 8
  36 #define VERT_MAX_TAPS 8
  37
  38 #define BLACK_OFFSET_RGB_Y 0x0
  39 #define BLACK_OFFSET_CBCR  0x8000
  40
  41 #define REG(reg)\
  42         dpp->tf_regs->reg
  43
  44 #define CTX \
  45         dpp->base.ctx
  46
  47 #undef FN
  48 #define FN(reg_name, field_name) \
  49         dpp->tf_shift->field_name, dpp->tf_mask->field_name
  50
  51 void dpp20_read_state(struct dpp *dpp_base,
  52                 struct dcn_dpp_state *s)
  53 {
  54         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
  55
  56         REG_GET(DPP_CONTROL,
  57                         DPP_CLOCK_ENABLE, &s->is_enabled);
  58         REG_GET(CM_DGAM_CONTROL,
  59                         CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
  60         // BGAM has no ROM, and definition is different, can't reuse same dump
  61         //REG_GET(CM_BLNDGAM_CONTROL,
  62         //              CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
  63         REG_GET(CM_GAMUT_REMAP_CONTROL,
  64                         CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
  65         if (s->gamut_remap_mode) {
  66                 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
  67                 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
  68                 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
  69                 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
  70                 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
  71                 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
  72         }
  73 }
  74
  75 void dpp2_dummy_program_input_lut(
  76                 struct dpp *dpp_base,
  77                 const struct dc_gamma *gamma)
  78 {}
  79
  80 static void dpp2_cnv_setup (
  81                 struct dpp *dpp_base,
  82                 enum surface_pixel_format format,
  83                 enum expansion_mode mode,
  84                 struct dc_csc_transform input_csc_color_matrix,
  85                 enum dc_color_space input_color_space,
  86                 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
  87 {
  88         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
  89         uint32_t pixel_format = 0;
  90         uint32_t alpha_en = 1;
  91         enum dc_color_space color_space = COLOR_SPACE_SRGB;
  92         enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
  93         bool force_disable_cursor = false;
  94         struct out_csc_color_matrix tbl_entry;
  95         uint32_t is_2bit = 0;
  96         int i = 0;
  97
  98         REG_SET_2(FORMAT_CONTROL, 0,
  99                 CNVC_BYPASS, 0,
 100                 FORMAT_EXPANSION_MODE, mode);
 101
 102         //hardcode default
 103     //FORMAT_CONTROL. FORMAT_CNV16                                      default 0: U0.16/S.1.15;         1: U1.15/ S.1.14
 104     //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN                                     default 0: disabled              1: enabled
 105     //FORMAT_CONTROL. CLAMP_POSITIVE                                    default 0: disabled              1: enabled
 106     //FORMAT_CONTROL. CLAMP_POSITIVE_C                                  default 0: disabled              1: enabled
 107         REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
 108         REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
 109         REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
 110         REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
 111
 112         switch (format) {
 113         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 114                 pixel_format = 1;
 115                 break;
 116         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 117                 pixel_format = 3;
 118                 alpha_en = 0;
 119                 break;
 120         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 121         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 122                 pixel_format = 8;
 123                 break;
 124         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 125         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 126                 pixel_format = 10;
 127                 is_2bit = 1;
 128                 break;
 129         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 130                 force_disable_cursor = false;
 131                 pixel_format = 65;
 132                 color_space = COLOR_SPACE_YCBCR709;
 133                 select = INPUT_CSC_SELECT_ICSC;
 134                 break;
 135         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 136                 force_disable_cursor = true;
 137                 pixel_format = 64;
 138                 color_space = COLOR_SPACE_YCBCR709;
 139                 select = INPUT_CSC_SELECT_ICSC;
 140                 break;
 141         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 142                 force_disable_cursor = true;
 143                 pixel_format = 67;
 144                 color_space = COLOR_SPACE_YCBCR709;
 145                 select = INPUT_CSC_SELECT_ICSC;
 146                 break;
 147         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 148                 force_disable_cursor = true;
 149                 pixel_format = 66;
 150                 color_space = COLOR_SPACE_YCBCR709;
 151                 select = INPUT_CSC_SELECT_ICSC;
 152                 break;
 153         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 154                 pixel_format = 22;
 155                 break;
 156         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 157                 pixel_format = 24;
 158                 break;
 159         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 160                 pixel_format = 25;
 161                 break;
 162         case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 163                 pixel_format = 12;
 164                 color_space = COLOR_SPACE_YCBCR709;
 165                 select = INPUT_CSC_SELECT_ICSC;
 166                 break;
 167         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 168                 pixel_format = 112;
 169                 break;
 170         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 171                 pixel_format = 113;
 172                 break;
 173         case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 174                 pixel_format = 114;
 175                 color_space = COLOR_SPACE_YCBCR709;
 176                 select = INPUT_CSC_SELECT_ICSC;
 177                 is_2bit = 1;
 178                 break;
 179         case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
 180                 pixel_format = 115;
 181                 color_space = COLOR_SPACE_YCBCR709;
 182                 select = INPUT_CSC_SELECT_ICSC;
 183                 is_2bit = 1;
 184                 break;
 185         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 186                 pixel_format = 118;
 187                 break;
 188         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 189                 pixel_format = 119;
 190                 break;
 191         default:
 192                 break;
 193         }
 194
 195         if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 196                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 197                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
 198                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
 199                 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
 200         }
 201
 202         REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
 203                         CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
 204         REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 205
 206         // if input adjustments exist, program icsc with those values
 207         if (input_csc_color_matrix.enable_adjustment
 208                                 == true) {
 209                 for (i = 0; i < 12; i++)
 210                         tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
 211
 212                 tbl_entry.color_space = input_color_space;
 213
 214                 if (color_space >= COLOR_SPACE_YCBCR601)
 215                         select = INPUT_CSC_SELECT_ICSC;
 216                 else
 217                         select = INPUT_CSC_SELECT_BYPASS;
 218
 219                 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
 220         } else
 221         dpp1_program_input_csc(dpp_base, color_space, select, NULL);
 222
 223         if (force_disable_cursor) {
 224                 REG_UPDATE(CURSOR_CONTROL,
 225                                 CURSOR_ENABLE, 0);
 226                 REG_UPDATE(CURSOR0_CONTROL,
 227                                 CUR0_ENABLE, 0);
 228
 229         }
 230
 231 }
 232
 233 void dpp2_cnv_set_bias_scale(
 234                 struct dpp *dpp_base,
 235                 struct  dc_bias_and_scale *bias_and_scale)
 236 {
 237         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
 238
 239         REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
 240         REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
 241         REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
 242         REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
 243         REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
 244         REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
 245 }
 246
 247 /*compute the maximum number of lines that we can fit in the line buffer*/
 248 void dscl2_calc_lb_num_partitions(
 249                 const struct scaler_data *scl_data,
 250                 enum lb_memory_config lb_config,
 251                 int *num_part_y,
 252                 int *num_part_c)
 253 {
 254         int memory_line_size_y, memory_line_size_c, memory_line_size_a,
 255         lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
 256
 257         int line_size = scl_data->viewport.width < scl_data->recout.width ?
 258                         scl_data->viewport.width : scl_data->recout.width;
 259         int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
 260                         scl_data->viewport_c.width : scl_data->recout.width;
 261
 262         if (line_size == 0)
 263                 line_size = 1;
 264
 265         if (line_size_c == 0)
 266                 line_size_c = 1;
 267
 268         memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
 269         memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
 270         memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
 271
 272         if (lb_config == LB_MEMORY_CONFIG_1) {
 273                 lb_memory_size = 970;
 274                 lb_memory_size_c = 970;
 275                 lb_memory_size_a = 970;
 276         } else if (lb_config == LB_MEMORY_CONFIG_2) {
 277                 lb_memory_size = 1290;
 278                 lb_memory_size_c = 1290;
 279                 lb_memory_size_a = 1290;
 280         } else if (lb_config == LB_MEMORY_CONFIG_3) {
 281                 /* 420 mode: using 3rd mem from Y, Cr and Cb */
 282                 lb_memory_size = 970 + 1290 + 484 + 484 + 484;
 283                 lb_memory_size_c = 970 + 1290;
 284                 lb_memory_size_a = 970 + 1290 + 484;
 285         } else {
 286                 lb_memory_size = 970 + 1290 + 484;
 287                 lb_memory_size_c = 970 + 1290 + 484;
 288                 lb_memory_size_a = 970 + 1290 + 484;
 289         }
 290         *num_part_y = lb_memory_size / memory_line_size_y;
 291         *num_part_c = lb_memory_size_c / memory_line_size_c;
 292         num_partitions_a = lb_memory_size_a / memory_line_size_a;
 293
 294         if (scl_data->lb_params.alpha_en
 295                         && (num_partitions_a < *num_part_y))
 296                 *num_part_y = num_partitions_a;
 297
 298         if (*num_part_y > 64)
 299                 *num_part_y = 64;
 300         if (*num_part_c > 64)
 301                 *num_part_c = 64;
 302 }
 303
 304 void dpp2_cnv_set_alpha_keyer(
 305                 struct dpp *dpp_base,
 306                 struct cnv_color_keyer_params *color_keyer)
 307 {
 308         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
 309
 310         REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
 311
 312         REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
 313
 314         REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
 315         REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
 316
 317         REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
 318         REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
 319
 320         REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
 321         REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
 322
 323         REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
 324         REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
 325 }
 326
 327 void dpp2_set_cursor_attributes(
 328                 struct dpp *dpp_base,
 329                 enum dc_cursor_color_format color_format)
 330 {
 331         struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
 332         int cur_rom_en = 0;
 333
 334         if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
 335                 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
 336                 cur_rom_en = 1;
 337
 338         REG_UPDATE_3(CURSOR0_CONTROL,
 339                         CUR0_MODE, color_format,
 340                         CUR0_EXPANSION_MODE, 0,
 341                         CUR0_ROM_EN, cur_rom_en);
 342
 343         if (color_format == CURSOR_MODE_MONO) {
 344                 /* todo: clarify what to program these to */
 345                 REG_UPDATE(CURSOR0_COLOR0,
 346                                 CUR0_COLOR0, 0x00000000);
 347                 REG_UPDATE(CURSOR0_COLOR1,
 348                                 CUR0_COLOR1, 0xFFFFFFFF);
 349         }
 350 }
 351
 352 #define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
 353
 354 bool dpp2_get_optimal_number_of_taps(
 355                 struct dpp *dpp,
 356                 struct scaler_data *scl_data,
 357                 const struct scaling_taps *in_taps)
 358 {
 359         uint32_t pixel_width;
 360
 361         if (scl_data->viewport.width > scl_data->recout.width)
 362                 pixel_width = scl_data->recout.width;
 363         else
 364                 pixel_width = scl_data->viewport.width;
 365
 366         /* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
 367         if (scl_data->viewport.width  != scl_data->h_active &&
 368                 scl_data->viewport.height != scl_data->v_active &&
 369                 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
 370                 scl_data->format == PIXEL_FORMAT_FP16)
 371                 return false;
 372
 373         if (scl_data->viewport.width > scl_data->h_active &&
 374                 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
 375                 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
 376                 return false;
 377
 378         /* TODO: add lb check */
 379
 380         /* No support for programming ratio of 8, drop to 7.99999.. */
 381         if (scl_data->ratios.horz.value == (8ll << 32))
 382                 scl_data->ratios.horz.value--;
 383         if (scl_data->ratios.vert.value == (8ll << 32))
 384                 scl_data->ratios.vert.value--;
 385         if (scl_data->ratios.horz_c.value == (8ll << 32))
 386                 scl_data->ratios.horz_c.value--;
 387         if (scl_data->ratios.vert_c.value == (8ll << 32))
 388                 scl_data->ratios.vert_c.value--;
 389
 390         /* Set default taps if none are provided */
 391         if (in_taps->h_taps == 0) {
 392                 if (dc_fixpt_ceil(scl_data->ratios.horz) > 4)
 393                         scl_data->taps.h_taps = 8;
 394                 else
 395                         scl_data->taps.h_taps = 4;
 396         } else
 397                 scl_data->taps.h_taps = in_taps->h_taps;
 398         if (in_taps->v_taps == 0) {
 399                 if (dc_fixpt_ceil(scl_data->ratios.vert) > 4)
 400                         scl_data->taps.v_taps = 8;
 401                 else
 402                         scl_data->taps.v_taps = 4;
 403         } else
 404                 scl_data->taps.v_taps = in_taps->v_taps;
 405         if (in_taps->v_taps_c == 0) {
 406                 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 4)
 407                         scl_data->taps.v_taps_c = 4;
 408                 else
 409                         scl_data->taps.v_taps_c = 2;
 410         } else
 411                 scl_data->taps.v_taps_c = in_taps->v_taps_c;
 412         if (in_taps->h_taps_c == 0) {
 413                 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 4)
 414                         scl_data->taps.h_taps_c = 4;
 415                 else
 416                         scl_data->taps.h_taps_c = 2;
 417         } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
 418                 /* Only 1 and even h_taps_c are supported by hw */
 419                 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
 420         else
 421                 scl_data->taps.h_taps_c = in_taps->h_taps_c;
 422
 423         if (!dpp->ctx->dc->debug.always_scale) {
 424                 if (IDENTITY_RATIO(scl_data->ratios.horz))
 425                         scl_data->taps.h_taps = 1;
 426                 if (IDENTITY_RATIO(scl_data->ratios.vert))
 427                         scl_data->taps.v_taps = 1;
 428                 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
 429                         scl_data->taps.h_taps_c = 1;
 430                 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
 431                         scl_data->taps.v_taps_c = 1;
 432         }
 433
 434         return true;
 435 }
 436
 437 void oppn20_dummy_program_regamma_pwl(
 438                 struct dpp *dpp,
 439                 const struct pwl_params *params,
 440                 enum opp_regamma mode)
 441 {}
 442
 443 static struct dpp_funcs dcn20_dpp_funcs = {
 444         .dpp_read_state = dpp20_read_state,
 445         .dpp_reset = dpp_reset,
 446         .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
 447         .dpp_get_optimal_number_of_taps = dpp2_get_optimal_number_of_taps,
 448         .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
 449         .dpp_set_csc_adjustment = NULL,
 450         .dpp_set_csc_default = NULL,
 451         .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
 452         .dpp_set_degamma                = dpp2_set_degamma,
 453         .dpp_program_input_lut          = dpp2_dummy_program_input_lut,
 454         .dpp_full_bypass                = dpp1_full_bypass,
 455         .dpp_setup                      = dpp2_cnv_setup,
 456         .dpp_program_degamma_pwl        = dpp2_set_degamma_pwl,
 457         .dpp_program_blnd_lut = dpp20_program_blnd_lut,
 458         .dpp_program_shaper_lut = dpp20_program_shaper,
 459         .dpp_program_3dlut = dpp20_program_3dlut,
 460         .dpp_program_bias_and_scale = NULL,
 461         .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
 462         .set_cursor_attributes = dpp2_set_cursor_attributes,
 463         .set_cursor_position = dpp1_set_cursor_position,
 464         .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
 465         .dpp_dppclk_control = dpp1_dppclk_control,
 466         .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
 467 };
 468
 469 static struct dpp_caps dcn20_dpp_cap = {
 470         .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
 471         .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
 472 };
 473
 474 bool dpp2_construct(
 475         struct dcn20_dpp *dpp,
 476         struct dc_context *ctx,
 477         uint32_t inst,
 478         const struct dcn2_dpp_registers *tf_regs,
 479         const struct dcn2_dpp_shift *tf_shift,
 480         const struct dcn2_dpp_mask *tf_mask)
 481 {
 482         dpp->base.ctx = ctx;
 483
 484         dpp->base.inst = inst;
 485         dpp->base.funcs = &dcn20_dpp_funcs;
 486         dpp->base.caps = &dcn20_dpp_cap;
 487
 488         dpp->tf_regs = tf_regs;
 489         dpp->tf_shift = tf_shift;
 490         dpp->tf_mask = tf_mask;
 491
 492         dpp->lb_pixel_depth_supported =
 493                 LB_PIXEL_DEPTH_18BPP |
 494                 LB_PIXEL_DEPTH_24BPP |
 495                 LB_PIXEL_DEPTH_30BPP;
 496
 497         dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
 498         dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
 499
 500         return true;
 501 }
 502