drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dal_asic_id.h"
  29 #include "dc_types.h"
  30 #include "dccg.h"
  31 #include "clk_mgr_internal.h"
  32
  33 #include "dce100/dce_clk_mgr.h"
  34 #include "dce110/dce110_clk_mgr.h"
  35 #include "dce112/dce112_clk_mgr.h"
  36 #include "dce120/dce120_clk_mgr.h"
  37 #include "dcn10/rv1_clk_mgr.h"
  38 #include "dcn10/rv2_clk_mgr.h"
  39 #include "dcn20/dcn20_clk_mgr.h"
  40
  41
  42 int clk_mgr_helper_get_active_display_cnt(
  43                 struct dc *dc,
  44                 struct dc_state *context)
  45 {
  46         int i, display_count;
  47
  48         display_count = 0;
  49         for (i = 0; i < context->stream_count; i++) {
  50                 const struct dc_stream_state *stream = context->streams[i];
  51
  52                 /*
  53                  * Only notify active stream or virtual stream.
  54                  * Need to notify virtual stream to work around
  55                  * headless case. HPD does not fire when system is in
  56                  * S0i2.
  57                  */
  58                 if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
  59                         display_count++;
  60         }
  61
  62         return display_count;
  63 }
  64
  65
  66 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
  67 {
  68         struct hw_asic_id asic_id = ctx->asic_id;
  69
  70         struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
  71
  72         if (clk_mgr == NULL) {
  73                 BREAK_TO_DEBUGGER();
  74                 return NULL;
  75         }
  76
  77         switch (asic_id.chip_family) {
  78         case FAMILY_CI:
  79         case FAMILY_KV:
  80                 dce_clk_mgr_construct(ctx, clk_mgr);
  81                 break;
  82         case FAMILY_CZ:
  83                 dce110_clk_mgr_construct(ctx, clk_mgr);
  84                 break;
  85         case FAMILY_VI:
  86                 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
  87                                 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
  88                         dce_clk_mgr_construct(ctx, clk_mgr);
  89                         break;
  90                 }
  91                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
  92                                 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
  93                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
  94                         dce112_clk_mgr_construct(ctx, clk_mgr);
  95                         break;
  96                 }
  97                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
  98                         dce112_clk_mgr_construct(ctx, clk_mgr);
  99                         break;
 100                 }
 101                 break;
 102         case FAMILY_AI:
 103                 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
 104                         dce121_clk_mgr_construct(ctx, clk_mgr);
 105                 else
 106                         dce120_clk_mgr_construct(ctx, clk_mgr);
 107                 break;
 108
 109 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 110         case FAMILY_RV:
 111                 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
 112                         rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 113                         break;
 114                 }
 115                 if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
 116                                 ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
 117                         rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 118                         break;
 119                 }
 120                 break;
 121 #endif  /* Family RV */
 122
 123 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 124         case FAMILY_NV:
 125                 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 126                 break;
 127 #endif /* Family NV */
 128
 129         default:
 130                 ASSERT(0); /* Unknown Asic */
 131                 break;
 132         }
 133
 134         return &clk_mgr->base;
 135 }
 136
 137 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 138 {
 139         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 140
 141         kfree(clk_mgr);
 142 }
 143