2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/module.h>
25 #include <linux/pci.h>
28 #include "amdgpu_pm.h"
29 #include "amdgpu_dpm.h"
30 #include "amdgpu_atombios.h"
36 #include "../include/pptable.h"
37 #include <linux/math64.h>
38 #include <linux/seq_file.h>
39 #include <linux/firmware.h>
41 #define MC_CG_ARB_FREQ_F0 0x0a
42 #define MC_CG_ARB_FREQ_F1 0x0b
43 #define MC_CG_ARB_FREQ_F2 0x0c
44 #define MC_CG_ARB_FREQ_F3 0x0d
46 #define SMC_RAM_END 0x20000
48 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
51 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
56 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
57 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
59 #define BIOS_SCRATCH_4 0x5cd
63 static const struct amd_pm_funcs si_dpm_funcs;
66 struct _ATOM_POWERPLAY_INFO info;
67 struct _ATOM_POWERPLAY_INFO_V2 info_2;
68 struct _ATOM_POWERPLAY_INFO_V3 info_3;
69 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
70 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
71 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
72 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
73 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
77 struct _ATOM_PPLIB_FANTABLE fan;
78 struct _ATOM_PPLIB_FANTABLE2 fan2;
79 struct _ATOM_PPLIB_FANTABLE3 fan3;
82 union pplib_clock_info {
83 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
84 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
85 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
86 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
87 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
90 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
109 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
128 static const struct si_cac_config_reg cac_weights_tahiti[] =
130 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
131 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
132 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
133 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
134 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
135 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
137 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
138 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
140 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
142 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
143 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
144 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
145 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
146 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
147 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
148 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
149 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
150 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
151 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
152 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
154 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
155 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
156 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
161 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
165 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
168 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
169 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
170 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
174 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
193 static const struct si_cac_config_reg lcac_tahiti[] =
195 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
196 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
197 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
198 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
199 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
204 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
206 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
220 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
222 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
256 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
258 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
268 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
270 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
272 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 static const struct si_cac_config_reg cac_override_tahiti[] =
290 static const struct si_powertune_data powertune_data_tahiti =
321 static const struct si_dte_data dte_data_tahiti =
323 { 1159409, 0, 0, 0, 0 },
332 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
333 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
334 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
340 static const struct si_dte_data dte_data_tahiti_le =
342 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
343 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
351 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
352 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
353 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
359 static const struct si_dte_data dte_data_tahiti_pro =
361 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
362 { 0x0, 0x0, 0x0, 0x0, 0x0 },
370 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
371 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
372 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 static const struct si_dte_data dte_data_new_zealand =
379 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
380 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
388 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
389 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
390 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 static const struct si_dte_data dte_data_aruba_pro =
397 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
398 { 0x0, 0x0, 0x0, 0x0, 0x0 },
406 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
407 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
408 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 static const struct si_dte_data dte_data_malta =
415 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
416 { 0x0, 0x0, 0x0, 0x0, 0x0 },
424 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
425 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
426 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 static const struct si_cac_config_reg cac_weights_pitcairn[] =
433 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
434 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
435 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
436 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
437 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
438 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
439 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
441 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
442 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
443 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
444 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
445 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
446 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
447 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
448 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
449 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
450 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
451 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
452 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
453 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
454 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
455 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
456 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
457 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
458 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
459 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
460 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
463 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
464 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
466 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
468 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
469 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
470 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
473 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
474 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
476 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
496 static const struct si_cac_config_reg lcac_pitcairn[] =
498 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
499 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
500 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
501 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
502 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
503 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
505 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
509 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
511 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
515 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
517 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
523 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
529 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
535 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
541 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
559 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
561 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
587 static const struct si_cac_config_reg cac_override_pitcairn[] =
592 static const struct si_powertune_data powertune_data_pitcairn =
623 static const struct si_dte_data dte_data_pitcairn =
634 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
635 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
636 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 static const struct si_dte_data dte_data_curacao_xt =
643 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
644 { 0x0, 0x0, 0x0, 0x0, 0x0 },
652 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
653 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
654 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 static const struct si_dte_data dte_data_curacao_pro =
661 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
662 { 0x0, 0x0, 0x0, 0x0, 0x0 },
670 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
671 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
672 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 static const struct si_dte_data dte_data_neptune_xt =
679 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
680 { 0x0, 0x0, 0x0, 0x0, 0x0 },
688 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
689 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
690 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
697 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
698 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
699 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
700 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
701 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
702 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
703 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
704 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
705 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
706 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
707 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
708 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
709 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
710 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
711 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
712 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
713 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
714 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
715 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
716 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
717 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
718 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
719 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
720 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
721 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
722 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
723 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
724 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
725 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
726 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
727 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
728 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
729 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
730 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
731 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
732 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
733 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
734 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
735 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
736 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
737 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
738 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
739 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
741 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
742 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
744 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
745 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
746 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
760 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
762 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
763 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
764 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
765 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
766 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
767 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
768 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
769 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
770 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
771 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
772 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
773 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
774 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
775 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
776 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
777 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
778 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
779 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
780 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
781 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
782 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
783 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
784 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
785 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
786 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
787 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
788 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
789 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
790 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
791 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
792 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
793 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
794 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
795 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
796 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
797 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
798 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
799 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
800 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
801 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
802 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
803 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
804 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
806 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
807 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
809 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
810 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
811 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
825 static const struct si_cac_config_reg cac_weights_heathrow[] =
827 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
828 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
829 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
830 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
831 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
832 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
833 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
834 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
835 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
836 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
837 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
838 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
839 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
840 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
841 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
842 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
843 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
844 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
845 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
846 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
847 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
848 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
849 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
850 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
851 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
852 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
853 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
854 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
855 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
856 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
857 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
858 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
859 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
860 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
861 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
862 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
863 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
864 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
865 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
866 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
867 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
868 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
869 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
871 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
872 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
874 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
875 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
876 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
890 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
892 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
893 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
894 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
895 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
896 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
897 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
898 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
899 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
900 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
901 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
902 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
903 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
904 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
905 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
906 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
907 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
908 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
909 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
910 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
911 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
912 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
913 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
914 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
915 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
916 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
917 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
918 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
919 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
920 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
921 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
922 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
923 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
924 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
925 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
926 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
927 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
928 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
929 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
930 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
931 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
932 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
933 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
934 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
936 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
937 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
939 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
940 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
941 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
955 static const struct si_cac_config_reg cac_weights_cape_verde[] =
957 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
958 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
959 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
960 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
961 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
962 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
963 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
964 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
965 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
966 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
967 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
968 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
969 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
970 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
971 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
972 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
973 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
974 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
975 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
976 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
977 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
978 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
979 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
980 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
981 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
982 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
983 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
984 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
985 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
986 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
987 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
988 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
989 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
990 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
991 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
992 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
993 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
994 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
995 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
996 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
997 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
998 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
999 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1001 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1002 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1020 static const struct si_cac_config_reg lcac_cape_verde[] =
1022 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1023 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1024 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1025 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1026 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1027 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1029 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1033 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1035 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1037 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1039 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1041 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1043 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1045 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1047 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1049 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1071 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 static const struct si_cac_config_reg cac_override_cape_verde[] =
1084 static const struct si_powertune_data powertune_data_cape_verde =
1086 ((1 << 16) | 0x6993),
1115 static const struct si_dte_data dte_data_cape_verde =
1126 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1127 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1128 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 static const struct si_dte_data dte_data_venus_xtx =
1135 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1136 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1144 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1145 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1146 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 static const struct si_dte_data dte_data_venus_xt =
1153 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1154 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1162 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1163 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1164 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 static const struct si_dte_data dte_data_venus_pro =
1171 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1172 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1180 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1181 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1182 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 static const struct si_cac_config_reg cac_weights_oland[] =
1189 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1190 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1191 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1192 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1193 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1194 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1195 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1196 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1197 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1198 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1199 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1200 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1201 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1202 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1203 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1204 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1205 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1206 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1207 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1208 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1209 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1210 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1211 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1212 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1213 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1214 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1215 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1216 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1217 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1218 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1219 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1220 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1221 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1222 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1223 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1224 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1225 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1226 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1227 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1228 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1229 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1230 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1231 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1233 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1234 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1252 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1254 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1255 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1256 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1257 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1258 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1259 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1261 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1262 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1263 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1264 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1265 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1266 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1267 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1268 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1269 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1271 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1272 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1273 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1274 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1275 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1276 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1277 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1278 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1279 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1280 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1281 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1282 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1283 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1284 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1285 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1286 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1287 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1288 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1289 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1290 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1292 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1293 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1294 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1295 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1296 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1298 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1299 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1301 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1302 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1317 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1319 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1320 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1321 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1322 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1323 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1325 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1326 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1327 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1328 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1329 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1330 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1331 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1332 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1333 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1334 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1336 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1337 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1338 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1339 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1340 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1341 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1342 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1343 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1344 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1345 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1346 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1347 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1348 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1349 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1350 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1351 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1352 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1353 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1354 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1355 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1356 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1357 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1358 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1359 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1360 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1361 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1363 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1364 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1366 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1367 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1382 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1384 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1385 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1386 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1387 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1388 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1389 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1390 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1391 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1392 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1393 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1394 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1395 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1396 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1397 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1398 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1399 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1401 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1402 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1403 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1404 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1405 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1406 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1407 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1408 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1409 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1410 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1411 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1412 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1413 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1414 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1415 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1416 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1417 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1418 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1419 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1420 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1421 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1422 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1423 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1424 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1425 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1426 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1428 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1429 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1431 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1432 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1447 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1449 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1450 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1451 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1452 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1453 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1454 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1455 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1456 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1457 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1458 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1459 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1460 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1461 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1462 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1463 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1464 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1466 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1467 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1468 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1469 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1470 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1471 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1472 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1473 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1474 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1475 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1476 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1477 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1479 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1480 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1481 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1482 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1483 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1484 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1485 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1486 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1487 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1488 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1489 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1490 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1491 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1493 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1494 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1496 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1497 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1512 static const struct si_cac_config_reg lcac_oland[] =
1514 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1515 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1517 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1519 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1521 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1525 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1527 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1529 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1531 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1533 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1543 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1547 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 static const struct si_cac_config_reg lcac_mars_pro[] =
1561 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1562 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1563 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1564 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1566 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1568 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1572 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1574 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1578 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1580 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1590 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1594 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 static const struct si_cac_config_reg cac_override_oland[] =
1611 static const struct si_powertune_data powertune_data_oland =
1613 ((1 << 16) | 0x6993),
1642 static const struct si_powertune_data powertune_data_mars_pro =
1644 ((1 << 16) | 0x6993),
1673 static const struct si_dte_data dte_data_oland =
1684 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1685 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1686 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 static const struct si_dte_data dte_data_mars_pro =
1693 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1694 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1702 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1703 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1704 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 static const struct si_dte_data dte_data_sun_xt =
1711 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1712 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1720 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1721 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1722 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1728 static const struct si_cac_config_reg cac_weights_hainan[] =
1730 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1731 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1732 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1733 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1734 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1735 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1736 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1737 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1738 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1741 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1742 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1743 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1744 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1745 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1746 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1747 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1748 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1749 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1750 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1751 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1752 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1753 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1754 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1756 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1757 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1760 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1761 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1765 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1766 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1767 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1769 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1770 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1771 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1772 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1774 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1776 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1793 static const struct si_powertune_data powertune_data_hainan =
1795 ((1 << 16) | 0x6993),
1824 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1825 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1826 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1827 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1829 static int si_populate_voltage_value(struct amdgpu_device *adev,
1830 const struct atom_voltage_table *table,
1831 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1832 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1833 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1835 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1836 u16 reg_offset, u32 value);
1837 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1838 struct rv7xx_pl *pl,
1839 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1840 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1842 SISLANDS_SMC_SCLK_VALUE *sclk);
1844 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1845 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1846 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1848 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1850 struct si_power_info *pi = adev->pm.dpm.priv;
1854 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1855 u16 v, s32 t, u32 ileakage, u32 *leakage)
1857 s64 kt, kv, leakage_w, i_leakage, vddc;
1858 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1861 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1862 vddc = div64_s64(drm_int2fixp(v), 1000);
1863 temperature = div64_s64(drm_int2fixp(t), 1000);
1865 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1866 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1867 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1868 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1869 t_ref = drm_int2fixp(coeff->t_ref);
1871 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1872 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1873 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1874 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1876 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1878 *leakage = drm_fixp2int(leakage_w * 1000);
1881 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1882 const struct ni_leakage_coeffients *coeff,
1888 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1891 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1892 const u32 fixed_kt, u16 v,
1893 u32 ileakage, u32 *leakage)
1895 s64 kt, kv, leakage_w, i_leakage, vddc;
1897 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1898 vddc = div64_s64(drm_int2fixp(v), 1000);
1900 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1901 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1902 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1904 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1906 *leakage = drm_fixp2int(leakage_w * 1000);
1909 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1910 const struct ni_leakage_coeffients *coeff,
1916 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1920 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1921 struct si_dte_data *dte_data)
1923 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1924 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1925 u32 k = dte_data->k;
1926 u32 t_max = dte_data->max_t;
1927 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1928 u32 t_0 = dte_data->t0;
1931 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1932 dte_data->tdep_count = 3;
1934 for (i = 0; i < k; i++) {
1936 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1937 (p_limit2 * (u32)100);
1940 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1942 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1943 dte_data->tdep_r[i] = dte_data->r[4];
1946 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1950 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1952 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1957 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1959 struct ni_power_info *pi = adev->pm.dpm.priv;
1964 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1966 struct si_ps *ps = aps->ps_priv;
1971 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1973 struct ni_power_info *ni_pi = ni_get_pi(adev);
1974 struct si_power_info *si_pi = si_get_pi(adev);
1975 bool update_dte_from_pl2 = false;
1977 if (adev->asic_type == CHIP_TAHITI) {
1978 si_pi->cac_weights = cac_weights_tahiti;
1979 si_pi->lcac_config = lcac_tahiti;
1980 si_pi->cac_override = cac_override_tahiti;
1981 si_pi->powertune_data = &powertune_data_tahiti;
1982 si_pi->dte_data = dte_data_tahiti;
1984 switch (adev->pdev->device) {
1986 si_pi->dte_data.enable_dte_by_default = true;
1989 si_pi->dte_data = dte_data_new_zealand;
1995 si_pi->dte_data = dte_data_aruba_pro;
1996 update_dte_from_pl2 = true;
1999 si_pi->dte_data = dte_data_malta;
2000 update_dte_from_pl2 = true;
2003 si_pi->dte_data = dte_data_tahiti_pro;
2004 update_dte_from_pl2 = true;
2007 if (si_pi->dte_data.enable_dte_by_default == true)
2008 DRM_ERROR("DTE is not enabled!\n");
2011 } else if (adev->asic_type == CHIP_PITCAIRN) {
2012 si_pi->cac_weights = cac_weights_pitcairn;
2013 si_pi->lcac_config = lcac_pitcairn;
2014 si_pi->cac_override = cac_override_pitcairn;
2015 si_pi->powertune_data = &powertune_data_pitcairn;
2017 switch (adev->pdev->device) {
2020 si_pi->dte_data = dte_data_curacao_xt;
2021 update_dte_from_pl2 = true;
2025 si_pi->dte_data = dte_data_curacao_pro;
2026 update_dte_from_pl2 = true;
2030 si_pi->dte_data = dte_data_neptune_xt;
2031 update_dte_from_pl2 = true;
2034 si_pi->dte_data = dte_data_pitcairn;
2037 } else if (adev->asic_type == CHIP_VERDE) {
2038 si_pi->lcac_config = lcac_cape_verde;
2039 si_pi->cac_override = cac_override_cape_verde;
2040 si_pi->powertune_data = &powertune_data_cape_verde;
2042 switch (adev->pdev->device) {
2047 si_pi->cac_weights = cac_weights_cape_verde_pro;
2048 si_pi->dte_data = dte_data_cape_verde;
2051 si_pi->cac_weights = cac_weights_cape_verde_pro;
2052 si_pi->dte_data = dte_data_sun_xt;
2053 update_dte_from_pl2 = true;
2057 si_pi->cac_weights = cac_weights_heathrow;
2058 si_pi->dte_data = dte_data_cape_verde;
2062 si_pi->cac_weights = cac_weights_chelsea_xt;
2063 si_pi->dte_data = dte_data_cape_verde;
2066 si_pi->cac_weights = cac_weights_chelsea_pro;
2067 si_pi->dte_data = dte_data_cape_verde;
2070 si_pi->cac_weights = cac_weights_heathrow;
2071 si_pi->dte_data = dte_data_venus_xtx;
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xt;
2081 si_pi->cac_weights = cac_weights_chelsea_pro;
2082 si_pi->dte_data = dte_data_venus_pro;
2085 si_pi->cac_weights = cac_weights_cape_verde;
2086 si_pi->dte_data = dte_data_cape_verde;
2089 } else if (adev->asic_type == CHIP_OLAND) {
2090 si_pi->lcac_config = lcac_mars_pro;
2091 si_pi->cac_override = cac_override_oland;
2092 si_pi->powertune_data = &powertune_data_mars_pro;
2093 si_pi->dte_data = dte_data_mars_pro;
2095 switch (adev->pdev->device) {
2100 si_pi->cac_weights = cac_weights_mars_pro;
2101 update_dte_from_pl2 = true;
2107 si_pi->cac_weights = cac_weights_mars_xt;
2108 update_dte_from_pl2 = true;
2113 si_pi->cac_weights = cac_weights_oland_pro;
2114 update_dte_from_pl2 = true;
2117 si_pi->cac_weights = cac_weights_oland_xt;
2118 update_dte_from_pl2 = true;
2121 si_pi->cac_weights = cac_weights_oland;
2122 si_pi->lcac_config = lcac_oland;
2123 si_pi->cac_override = cac_override_oland;
2124 si_pi->powertune_data = &powertune_data_oland;
2125 si_pi->dte_data = dte_data_oland;
2128 } else if (adev->asic_type == CHIP_HAINAN) {
2129 si_pi->cac_weights = cac_weights_hainan;
2130 si_pi->lcac_config = lcac_oland;
2131 si_pi->cac_override = cac_override_oland;
2132 si_pi->powertune_data = &powertune_data_hainan;
2133 si_pi->dte_data = dte_data_sun_xt;
2134 update_dte_from_pl2 = true;
2136 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2140 ni_pi->enable_power_containment = false;
2141 ni_pi->enable_cac = false;
2142 ni_pi->enable_sq_ramping = false;
2143 si_pi->enable_dte = false;
2145 if (si_pi->powertune_data->enable_powertune_by_default) {
2146 ni_pi->enable_power_containment = true;
2147 ni_pi->enable_cac = true;
2148 if (si_pi->dte_data.enable_dte_by_default) {
2149 si_pi->enable_dte = true;
2150 if (update_dte_from_pl2)
2151 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2154 ni_pi->enable_sq_ramping = true;
2157 ni_pi->driver_calculate_cac_leakage = true;
2158 ni_pi->cac_configuration_required = true;
2160 if (ni_pi->cac_configuration_required) {
2161 ni_pi->support_cac_long_term_average = true;
2162 si_pi->dyn_powertune_data.l2_lta_window_size =
2163 si_pi->powertune_data->l2_lta_window_size_default;
2164 si_pi->dyn_powertune_data.lts_truncate =
2165 si_pi->powertune_data->lts_truncate_default;
2167 ni_pi->support_cac_long_term_average = false;
2168 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2169 si_pi->dyn_powertune_data.lts_truncate = 0;
2172 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2175 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185 u32 cac_window_size;
2187 xclk = amdgpu_asic_get_xclk(adev);
2192 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2193 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2195 wintime = (cac_window_size * 100) / xclk;
2200 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2202 return power_in_watts;
2205 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2206 bool adjust_polarity,
2209 u32 *near_tdp_limit)
2211 u32 adjustment_delta, max_tdp_limit;
2213 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2216 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2218 if (adjust_polarity) {
2219 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2220 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2222 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2223 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2224 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2225 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2227 *near_tdp_limit = 0;
2230 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2232 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2238 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2239 struct amdgpu_ps *amdgpu_state)
2241 struct ni_power_info *ni_pi = ni_get_pi(adev);
2242 struct si_power_info *si_pi = si_get_pi(adev);
2244 if (ni_pi->enable_power_containment) {
2245 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2246 PP_SIslands_PAPMParameters *papm_parm;
2247 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2248 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 if (scaling_factor == 0)
2256 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2258 ret = si_calculate_adjusted_tdp_limits(adev,
2260 adev->pm.dpm.tdp_adjustment,
2266 smc_table->dpm2Params.TDPLimit =
2267 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2268 smc_table->dpm2Params.NearTDPLimit =
2269 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2270 smc_table->dpm2Params.SafePowerLimit =
2271 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2273 ret = amdgpu_si_copy_bytes_to_smc(adev,
2274 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2275 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2276 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2282 if (si_pi->enable_ppm) {
2283 papm_parm = &si_pi->papm_parm;
2284 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2285 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2286 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2287 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2288 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2289 papm_parm->PlatformPowerLimit = 0xffffffff;
2290 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2292 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2294 sizeof(PP_SIslands_PAPMParameters),
2303 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2304 struct amdgpu_ps *amdgpu_state)
2306 struct ni_power_info *ni_pi = ni_get_pi(adev);
2307 struct si_power_info *si_pi = si_get_pi(adev);
2309 if (ni_pi->enable_power_containment) {
2310 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2311 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2314 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2316 smc_table->dpm2Params.NearTDPLimit =
2317 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2318 smc_table->dpm2Params.SafePowerLimit =
2319 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2321 ret = amdgpu_si_copy_bytes_to_smc(adev,
2322 (si_pi->state_table_start +
2323 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2324 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2325 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2335 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2336 const u16 prev_std_vddc,
2337 const u16 curr_std_vddc)
2339 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2340 u64 prev_vddc = (u64)prev_std_vddc;
2341 u64 curr_vddc = (u64)curr_std_vddc;
2342 u64 pwr_efficiency_ratio, n, d;
2344 if ((prev_vddc == 0) || (curr_vddc == 0))
2347 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2348 d = prev_vddc * prev_vddc;
2349 pwr_efficiency_ratio = div64_u64(n, d);
2351 if (pwr_efficiency_ratio > (u64)0xFFFF)
2354 return (u16)pwr_efficiency_ratio;
2357 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2358 struct amdgpu_ps *amdgpu_state)
2360 struct si_power_info *si_pi = si_get_pi(adev);
2362 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2363 amdgpu_state->vclk && amdgpu_state->dclk)
2369 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2371 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2377 struct amdgpu_ps *amdgpu_state,
2378 SISLANDS_SMC_SWSTATE *smc_state)
2380 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2381 struct ni_power_info *ni_pi = ni_get_pi(adev);
2382 struct si_ps *state = si_get_ps(amdgpu_state);
2383 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2390 u16 pwr_efficiency_ratio;
2392 bool disable_uvd_power_tune;
2395 if (ni_pi->enable_power_containment == false)
2398 if (state->performance_level_count == 0)
2401 if (smc_state->levelCount != state->performance_level_count)
2404 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2406 smc_state->levels[0].dpm2.MaxPS = 0;
2407 smc_state->levels[0].dpm2.NearTDPDec = 0;
2408 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2409 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2410 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2412 for (i = 1; i < state->performance_level_count; i++) {
2413 prev_sclk = state->performance_levels[i-1].sclk;
2414 max_sclk = state->performance_levels[i].sclk;
2416 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2418 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2420 if (prev_sclk > max_sclk)
2423 if ((max_ps_percent == 0) ||
2424 (prev_sclk == max_sclk) ||
2425 disable_uvd_power_tune)
2426 min_sclk = max_sclk;
2428 min_sclk = prev_sclk;
2430 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2432 if (min_sclk < state->performance_levels[0].sclk)
2433 min_sclk = state->performance_levels[0].sclk;
2438 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2439 state->performance_levels[i-1].vddc, &vddc);
2443 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2447 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2448 state->performance_levels[i].vddc, &vddc);
2452 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2456 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2457 prev_std_vddc, curr_std_vddc);
2459 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2460 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2461 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2462 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2463 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2469 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2470 struct amdgpu_ps *amdgpu_state,
2471 SISLANDS_SMC_SWSTATE *smc_state)
2473 struct ni_power_info *ni_pi = ni_get_pi(adev);
2474 struct si_ps *state = si_get_ps(amdgpu_state);
2475 u32 sq_power_throttle, sq_power_throttle2;
2476 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2479 if (state->performance_level_count == 0)
2482 if (smc_state->levelCount != state->performance_level_count)
2485 if (adev->pm.dpm.sq_ramping_threshold == 0)
2488 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2489 enable_sq_ramping = false;
2491 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2492 enable_sq_ramping = false;
2494 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2495 enable_sq_ramping = false;
2497 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2498 enable_sq_ramping = false;
2500 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2501 enable_sq_ramping = false;
2503 for (i = 0; i < state->performance_level_count; i++) {
2504 sq_power_throttle = 0;
2505 sq_power_throttle2 = 0;
2507 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2508 enable_sq_ramping) {
2509 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2510 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2511 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2512 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2513 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2515 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2516 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2519 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2520 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2526 static int si_enable_power_containment(struct amdgpu_device *adev,
2527 struct amdgpu_ps *amdgpu_new_state,
2530 struct ni_power_info *ni_pi = ni_get_pi(adev);
2531 PPSMC_Result smc_result;
2534 if (ni_pi->enable_power_containment) {
2536 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2537 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2538 if (smc_result != PPSMC_Result_OK) {
2540 ni_pi->pc_enabled = false;
2542 ni_pi->pc_enabled = true;
2546 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2547 if (smc_result != PPSMC_Result_OK)
2549 ni_pi->pc_enabled = false;
2556 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2558 struct si_power_info *si_pi = si_get_pi(adev);
2560 struct si_dte_data *dte_data = &si_pi->dte_data;
2561 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 if (dte_data == NULL)
2567 si_pi->enable_dte = false;
2569 if (si_pi->enable_dte == false)
2572 if (dte_data->k <= 0)
2575 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2576 if (dte_tables == NULL) {
2577 si_pi->enable_dte = false;
2581 table_size = dte_data->k;
2583 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2584 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2586 tdep_count = dte_data->tdep_count;
2587 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2588 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2590 dte_tables->K = cpu_to_be32(table_size);
2591 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2592 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2593 dte_tables->WindowSize = dte_data->window_size;
2594 dte_tables->temp_select = dte_data->temp_select;
2595 dte_tables->DTE_mode = dte_data->dte_mode;
2596 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601 for (i = 0; i < table_size; i++) {
2602 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2603 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2606 dte_tables->Tdep_count = tdep_count;
2608 for (i = 0; i < (u32)tdep_count; i++) {
2609 dte_tables->T_limits[i] = dte_data->t_limits[i];
2610 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2611 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2614 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2616 sizeof(Smc_SIslands_DTE_Configuration),
2623 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2626 struct si_power_info *si_pi = si_get_pi(adev);
2627 struct amdgpu_cac_leakage_table *table =
2628 &adev->pm.dpm.dyn_state.cac_leakage_table;
2638 for (i = 0; i < table->count; i++) {
2639 if (table->entries[i].vddc > *max)
2640 *max = table->entries[i].vddc;
2641 if (table->entries[i].vddc < *min)
2642 *min = table->entries[i].vddc;
2645 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2648 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2650 if (v0_loadline > 0xFFFFUL)
2653 *min = (u16)v0_loadline;
2655 if ((*min > *max) || (*max == 0) || (*min == 0))
2661 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2663 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2664 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2667 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2668 PP_SIslands_CacConfig *cac_tables,
2669 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2672 struct si_power_info *si_pi = si_get_pi(adev);
2680 scaling_factor = si_get_smc_power_scaling_factor(adev);
2682 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2683 t = (1000 * (i * t_step + t0));
2685 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2686 voltage = vddc_max - (vddc_step * j);
2688 si_calculate_leakage_for_v_and_t(adev,
2689 &si_pi->powertune_data->leakage_coefficients,
2692 si_pi->dyn_powertune_data.cac_leakage,
2695 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2697 if (smc_leakage > 0xFFFF)
2698 smc_leakage = 0xFFFF;
2700 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2701 cpu_to_be16((u16)smc_leakage);
2707 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2708 PP_SIslands_CacConfig *cac_tables,
2709 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2711 struct si_power_info *si_pi = si_get_pi(adev);
2718 scaling_factor = si_get_smc_power_scaling_factor(adev);
2720 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2721 voltage = vddc_max - (vddc_step * j);
2723 si_calculate_leakage_for_v(adev,
2724 &si_pi->powertune_data->leakage_coefficients,
2725 si_pi->powertune_data->fixed_kt,
2727 si_pi->dyn_powertune_data.cac_leakage,
2730 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2732 if (smc_leakage > 0xFFFF)
2733 smc_leakage = 0xFFFF;
2735 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2736 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2737 cpu_to_be16((u16)smc_leakage);
2742 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2744 struct ni_power_info *ni_pi = ni_get_pi(adev);
2745 struct si_power_info *si_pi = si_get_pi(adev);
2746 PP_SIslands_CacConfig *cac_tables = NULL;
2747 u16 vddc_max, vddc_min, vddc_step;
2749 u32 load_line_slope, reg;
2751 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2753 if (ni_pi->enable_cac == false)
2756 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2760 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2761 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2762 WREG32(CG_CAC_CTRL, reg);
2764 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2765 si_pi->dyn_powertune_data.dc_pwr_value =
2766 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2767 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2768 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2770 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2772 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2776 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2777 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2781 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2782 ret = si_init_dte_leakage_table(adev, cac_tables,
2783 vddc_max, vddc_min, vddc_step,
2786 ret = si_init_simplified_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step);
2791 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2793 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2794 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2795 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2796 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2797 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2798 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2799 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2800 cac_tables->calculation_repeats = cpu_to_be32(2);
2801 cac_tables->dc_cac = cpu_to_be32(0);
2802 cac_tables->log2_PG_LKG_SCALE = 12;
2803 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2804 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2805 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2807 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2809 sizeof(PP_SIslands_CacConfig),
2815 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2819 ni_pi->enable_cac = false;
2820 ni_pi->enable_power_containment = false;
2828 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2829 const struct si_cac_config_reg *cac_config_regs)
2831 const struct si_cac_config_reg *config_regs = cac_config_regs;
2832 u32 data = 0, offset;
2837 while (config_regs->offset != 0xFFFFFFFF) {
2838 switch (config_regs->type) {
2839 case SISLANDS_CACCONFIG_CGIND:
2840 offset = SMC_CG_IND_START + config_regs->offset;
2841 if (offset < SMC_CG_IND_END)
2842 data = RREG32_SMC(offset);
2845 data = RREG32(config_regs->offset);
2849 data &= ~config_regs->mask;
2850 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2852 switch (config_regs->type) {
2853 case SISLANDS_CACCONFIG_CGIND:
2854 offset = SMC_CG_IND_START + config_regs->offset;
2855 if (offset < SMC_CG_IND_END)
2856 WREG32_SMC(offset, data);
2859 WREG32(config_regs->offset, data);
2867 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2869 struct ni_power_info *ni_pi = ni_get_pi(adev);
2870 struct si_power_info *si_pi = si_get_pi(adev);
2873 if ((ni_pi->enable_cac == false) ||
2874 (ni_pi->cac_configuration_required == false))
2877 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2880 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2883 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2890 static int si_enable_smc_cac(struct amdgpu_device *adev,
2891 struct amdgpu_ps *amdgpu_new_state,
2894 struct ni_power_info *ni_pi = ni_get_pi(adev);
2895 struct si_power_info *si_pi = si_get_pi(adev);
2896 PPSMC_Result smc_result;
2899 if (ni_pi->enable_cac) {
2901 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2902 if (ni_pi->support_cac_long_term_average) {
2903 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2904 if (smc_result != PPSMC_Result_OK)
2905 ni_pi->support_cac_long_term_average = false;
2908 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2909 if (smc_result != PPSMC_Result_OK) {
2911 ni_pi->cac_enabled = false;
2913 ni_pi->cac_enabled = true;
2916 if (si_pi->enable_dte) {
2917 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2918 if (smc_result != PPSMC_Result_OK)
2922 } else if (ni_pi->cac_enabled) {
2923 if (si_pi->enable_dte)
2924 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2926 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2928 ni_pi->cac_enabled = false;
2930 if (ni_pi->support_cac_long_term_average)
2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2937 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2939 struct ni_power_info *ni_pi = ni_get_pi(adev);
2940 struct si_power_info *si_pi = si_get_pi(adev);
2941 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2942 SISLANDS_SMC_SCLK_VALUE sclk_params;
2950 if (si_pi->spll_table_start == 0)
2953 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2954 if (spll_table == NULL)
2957 for (i = 0; i < 256; i++) {
2958 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2961 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2962 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2963 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2964 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2966 fb_div &= ~0x00001FFF;
2970 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2972 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2974 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2976 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2982 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2983 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2984 spll_table->freq[i] = cpu_to_be32(tmp);
2986 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2987 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2988 spll_table->ss[i] = cpu_to_be32(tmp);
2995 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2997 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3001 ni_pi->enable_power_containment = false;
3008 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3011 u16 highest_leakage = 0;
3012 struct si_power_info *si_pi = si_get_pi(adev);
3015 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3016 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3017 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3020 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3021 return highest_leakage;
3026 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3027 u32 evclk, u32 ecclk, u16 *voltage)
3031 struct amdgpu_vce_clock_voltage_dependency_table *table =
3032 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3034 if (((evclk == 0) && (ecclk == 0)) ||
3035 (table && (table->count == 0))) {
3040 for (i = 0; i < table->count; i++) {
3041 if ((evclk <= table->entries[i].evclk) &&
3042 (ecclk <= table->entries[i].ecclk)) {
3043 *voltage = table->entries[i].v;
3049 /* if no match return the highest voltage */
3051 *voltage = table->entries[table->count - 1].v;
3053 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3058 static bool si_dpm_vblank_too_short(void *handle)
3060 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3061 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3062 /* we never hit the non-gddr5 limit so disable it */
3063 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3065 if (vblank_time < switch_limit)
3072 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3073 u32 arb_freq_src, u32 arb_freq_dest)
3075 u32 mc_arb_dram_timing;
3076 u32 mc_arb_dram_timing2;
3080 switch (arb_freq_src) {
3081 case MC_CG_ARB_FREQ_F0:
3082 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3083 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3084 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3086 case MC_CG_ARB_FREQ_F1:
3087 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3088 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3089 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3091 case MC_CG_ARB_FREQ_F2:
3092 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3093 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3094 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3096 case MC_CG_ARB_FREQ_F3:
3097 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3098 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3099 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3105 switch (arb_freq_dest) {
3106 case MC_CG_ARB_FREQ_F0:
3107 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3108 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3109 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3111 case MC_CG_ARB_FREQ_F1:
3112 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3113 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3114 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3116 case MC_CG_ARB_FREQ_F2:
3117 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3118 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3119 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3121 case MC_CG_ARB_FREQ_F3:
3122 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3123 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3124 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3130 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3131 WREG32(MC_CG_CONFIG, mc_cg_config);
3132 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3137 static void ni_update_current_ps(struct amdgpu_device *adev,
3138 struct amdgpu_ps *rps)
3140 struct si_ps *new_ps = si_get_ps(rps);
3141 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3142 struct ni_power_info *ni_pi = ni_get_pi(adev);
3144 eg_pi->current_rps = *rps;
3145 ni_pi->current_ps = *new_ps;
3146 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3147 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3150 static void ni_update_requested_ps(struct amdgpu_device *adev,
3151 struct amdgpu_ps *rps)
3153 struct si_ps *new_ps = si_get_ps(rps);
3154 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3155 struct ni_power_info *ni_pi = ni_get_pi(adev);
3157 eg_pi->requested_rps = *rps;
3158 ni_pi->requested_ps = *new_ps;
3159 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3160 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3163 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3164 struct amdgpu_ps *new_ps,
3165 struct amdgpu_ps *old_ps)
3167 struct si_ps *new_state = si_get_ps(new_ps);
3168 struct si_ps *current_state = si_get_ps(old_ps);
3170 if ((new_ps->vclk == old_ps->vclk) &&
3171 (new_ps->dclk == old_ps->dclk))
3174 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3175 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3178 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3181 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3182 struct amdgpu_ps *new_ps,
3183 struct amdgpu_ps *old_ps)
3185 struct si_ps *new_state = si_get_ps(new_ps);
3186 struct si_ps *current_state = si_get_ps(old_ps);
3188 if ((new_ps->vclk == old_ps->vclk) &&
3189 (new_ps->dclk == old_ps->dclk))
3192 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3193 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3196 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3199 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3203 for (i = 0; i < table->count; i++)
3204 if (voltage <= table->entries[i].value)
3205 return table->entries[i].value;
3207 return table->entries[table->count - 1].value;
3210 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3211 u32 max_clock, u32 requested_clock)
3215 if ((clocks == NULL) || (clocks->count == 0))
3216 return (requested_clock < max_clock) ? requested_clock : max_clock;
3218 for (i = 0; i < clocks->count; i++) {
3219 if (clocks->values[i] >= requested_clock)
3220 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3223 return (clocks->values[clocks->count - 1] < max_clock) ?
3224 clocks->values[clocks->count - 1] : max_clock;
3227 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3228 u32 max_mclk, u32 requested_mclk)
3230 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3231 max_mclk, requested_mclk);
3234 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3235 u32 max_sclk, u32 requested_sclk)
3237 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3238 max_sclk, requested_sclk);
3241 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3246 if ((table == NULL) || (table->count == 0)) {
3251 for (i = 0; i < table->count; i++) {
3252 if (clock < table->entries[i].clk)
3253 clock = table->entries[i].clk;
3258 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3259 u32 clock, u16 max_voltage, u16 *voltage)
3263 if ((table == NULL) || (table->count == 0))
3266 for (i= 0; i < table->count; i++) {
3267 if (clock <= table->entries[i].clk) {
3268 if (*voltage < table->entries[i].v)
3269 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3270 table->entries[i].v : max_voltage);
3275 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3278 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3279 const struct amdgpu_clock_and_voltage_limits *max_limits,
3280 struct rv7xx_pl *pl)
3283 if ((pl->mclk == 0) || (pl->sclk == 0))
3286 if (pl->mclk == pl->sclk)
3289 if (pl->mclk > pl->sclk) {
3290 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3291 pl->sclk = btc_get_valid_sclk(adev,
3294 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3295 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3297 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3298 pl->mclk = btc_get_valid_mclk(adev,
3301 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3305 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3306 u16 max_vddc, u16 max_vddci,
3307 u16 *vddc, u16 *vddci)
3309 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3312 if ((0 == *vddc) || (0 == *vddci))
3315 if (*vddc > *vddci) {
3316 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3317 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3318 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3319 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3322 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3323 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3324 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3325 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3330 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3337 i_c = (i * r_c) / 100;
3346 *p = i_c / (1 << (2 * (*u)));
3349 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3354 if ((fl == 0) || (fh == 0) || (fl > fh))
3357 k = (100 * fh) / fl;
3358 t1 = (t * (k - 100));
3359 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3361 ah = ((a * t) + 5000) / 10000;
3370 static bool r600_is_uvd_state(u32 class, u32 class2)
3372 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3374 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3376 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3378 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3380 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3385 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3387 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3390 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3392 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3395 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3398 pi->max_vddc = vddc;
3401 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3403 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3404 struct amdgpu_atom_ss ss;
3406 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3407 ASIC_INTERNAL_ENGINE_SS, 0);
3408 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3409 ASIC_INTERNAL_MEMORY_SS, 0);
3411 if (pi->sclk_ss || pi->mclk_ss)
3412 pi->dynamic_ss = true;
3414 pi->dynamic_ss = false;
3418 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3419 struct amdgpu_ps *rps)
3421 struct si_ps *ps = si_get_ps(rps);
3422 struct amdgpu_clock_and_voltage_limits *max_limits;
3423 bool disable_mclk_switching = false;
3424 bool disable_sclk_switching = false;
3426 u16 vddc, vddci, min_vce_voltage = 0;
3427 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3428 u32 max_sclk = 0, max_mclk = 0;
3431 if (adev->asic_type == CHIP_HAINAN) {
3432 if ((adev->pdev->revision == 0x81) ||
3433 (adev->pdev->revision == 0xC3) ||
3434 (adev->pdev->device == 0x6664) ||
3435 (adev->pdev->device == 0x6665) ||
3436 (adev->pdev->device == 0x6667)) {
3439 if ((adev->pdev->revision == 0xC3) ||
3440 (adev->pdev->device == 0x6665)) {
3444 } else if (adev->asic_type == CHIP_OLAND) {
3445 if ((adev->pdev->revision == 0xC7) ||
3446 (adev->pdev->revision == 0x80) ||
3447 (adev->pdev->revision == 0x81) ||
3448 (adev->pdev->revision == 0x83) ||
3449 (adev->pdev->revision == 0x87) ||
3450 (adev->pdev->device == 0x6604) ||
3451 (adev->pdev->device == 0x6605)) {
3456 if (rps->vce_active) {
3457 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3458 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3459 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3466 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3467 si_dpm_vblank_too_short(adev))
3468 disable_mclk_switching = true;
3470 if (rps->vclk || rps->dclk) {
3471 disable_mclk_switching = true;
3472 disable_sclk_switching = true;
3475 if (adev->pm.ac_power)
3476 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3478 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3480 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3481 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3482 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3484 if (adev->pm.ac_power == false) {
3485 for (i = 0; i < ps->performance_level_count; i++) {
3486 if (ps->performance_levels[i].mclk > max_limits->mclk)
3487 ps->performance_levels[i].mclk = max_limits->mclk;
3488 if (ps->performance_levels[i].sclk > max_limits->sclk)
3489 ps->performance_levels[i].sclk = max_limits->sclk;
3490 if (ps->performance_levels[i].vddc > max_limits->vddc)
3491 ps->performance_levels[i].vddc = max_limits->vddc;
3492 if (ps->performance_levels[i].vddci > max_limits->vddci)
3493 ps->performance_levels[i].vddci = max_limits->vddci;
3497 /* limit clocks to max supported clocks based on voltage dependency tables */
3498 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3500 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3502 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3505 for (i = 0; i < ps->performance_level_count; i++) {
3506 if (max_sclk_vddc) {
3507 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3508 ps->performance_levels[i].sclk = max_sclk_vddc;
3510 if (max_mclk_vddci) {
3511 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3512 ps->performance_levels[i].mclk = max_mclk_vddci;
3514 if (max_mclk_vddc) {
3515 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3516 ps->performance_levels[i].mclk = max_mclk_vddc;
3519 if (ps->performance_levels[i].mclk > max_mclk)
3520 ps->performance_levels[i].mclk = max_mclk;
3523 if (ps->performance_levels[i].sclk > max_sclk)
3524 ps->performance_levels[i].sclk = max_sclk;
3528 /* XXX validate the min clocks required for display */
3530 if (disable_mclk_switching) {
3531 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3532 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3534 mclk = ps->performance_levels[0].mclk;
3535 vddci = ps->performance_levels[0].vddci;
3538 if (disable_sclk_switching) {
3539 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3540 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3542 sclk = ps->performance_levels[0].sclk;
3543 vddc = ps->performance_levels[0].vddc;
3546 if (rps->vce_active) {
3547 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3548 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3549 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3550 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3553 /* adjusted low state */
3554 ps->performance_levels[0].sclk = sclk;
3555 ps->performance_levels[0].mclk = mclk;
3556 ps->performance_levels[0].vddc = vddc;
3557 ps->performance_levels[0].vddci = vddci;
3559 if (disable_sclk_switching) {
3560 sclk = ps->performance_levels[0].sclk;
3561 for (i = 1; i < ps->performance_level_count; i++) {
3562 if (sclk < ps->performance_levels[i].sclk)
3563 sclk = ps->performance_levels[i].sclk;
3565 for (i = 0; i < ps->performance_level_count; i++) {
3566 ps->performance_levels[i].sclk = sclk;
3567 ps->performance_levels[i].vddc = vddc;
3570 for (i = 1; i < ps->performance_level_count; i++) {
3571 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3572 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3573 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3574 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3578 if (disable_mclk_switching) {
3579 mclk = ps->performance_levels[0].mclk;
3580 for (i = 1; i < ps->performance_level_count; i++) {
3581 if (mclk < ps->performance_levels[i].mclk)
3582 mclk = ps->performance_levels[i].mclk;
3584 for (i = 0; i < ps->performance_level_count; i++) {
3585 ps->performance_levels[i].mclk = mclk;
3586 ps->performance_levels[i].vddci = vddci;
3589 for (i = 1; i < ps->performance_level_count; i++) {
3590 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3591 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3592 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3593 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3597 for (i = 0; i < ps->performance_level_count; i++)
3598 btc_adjust_clock_combinations(adev, max_limits,
3599 &ps->performance_levels[i]);
3601 for (i = 0; i < ps->performance_level_count; i++) {
3602 if (ps->performance_levels[i].vddc < min_vce_voltage)
3603 ps->performance_levels[i].vddc = min_vce_voltage;
3604 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3605 ps->performance_levels[i].sclk,
3606 max_limits->vddc, &ps->performance_levels[i].vddc);
3607 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3608 ps->performance_levels[i].mclk,
3609 max_limits->vddci, &ps->performance_levels[i].vddci);
3610 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3611 ps->performance_levels[i].mclk,
3612 max_limits->vddc, &ps->performance_levels[i].vddc);
3613 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3614 adev->clock.current_dispclk,
3615 max_limits->vddc, &ps->performance_levels[i].vddc);
3618 for (i = 0; i < ps->performance_level_count; i++) {
3619 btc_apply_voltage_delta_rules(adev,
3620 max_limits->vddc, max_limits->vddci,
3621 &ps->performance_levels[i].vddc,
3622 &ps->performance_levels[i].vddci);
3625 ps->dc_compatible = true;
3626 for (i = 0; i < ps->performance_level_count; i++) {
3627 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3628 ps->dc_compatible = false;
3633 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3634 u16 reg_offset, u32 *value)
3636 struct si_power_info *si_pi = si_get_pi(adev);
3638 return amdgpu_si_read_smc_sram_dword(adev,
3639 si_pi->soft_regs_start + reg_offset, value,
3644 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3645 u16 reg_offset, u32 value)
3647 struct si_power_info *si_pi = si_get_pi(adev);
3649 return amdgpu_si_write_smc_sram_dword(adev,
3650 si_pi->soft_regs_start + reg_offset,
3651 value, si_pi->sram_end);
3654 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3657 u32 tmp, width, row, column, bank, density;
3658 bool is_memory_gddr5, is_special;
3660 tmp = RREG32(MC_SEQ_MISC0);
3661 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3662 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3663 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3665 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3666 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3668 tmp = RREG32(MC_ARB_RAMCFG);
3669 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3670 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3671 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3673 density = (1 << (row + column - 20 + bank)) * width;
3675 if ((adev->pdev->device == 0x6819) &&
3676 is_memory_gddr5 && is_special && (density == 0x400))
3682 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3684 struct si_power_info *si_pi = si_get_pi(adev);
3685 u16 vddc, count = 0;
3688 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3689 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3691 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3692 si_pi->leakage_voltage.entries[count].voltage = vddc;
3693 si_pi->leakage_voltage.entries[count].leakage_index =
3694 SISLANDS_LEAKAGE_INDEX0 + i;
3698 si_pi->leakage_voltage.count = count;
3701 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3702 u32 index, u16 *leakage_voltage)
3704 struct si_power_info *si_pi = si_get_pi(adev);
3707 if (leakage_voltage == NULL)
3710 if ((index & 0xff00) != 0xff00)
3713 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3716 if (index < SISLANDS_LEAKAGE_INDEX0)
3719 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3720 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3721 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3728 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3730 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3731 bool want_thermal_protection;
3732 enum amdgpu_dpm_event_src dpm_event_src;
3737 want_thermal_protection = false;
3739 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3740 want_thermal_protection = true;
3741 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3743 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3744 want_thermal_protection = true;
3745 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3747 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3748 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3749 want_thermal_protection = true;
3750 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3754 if (want_thermal_protection) {
3755 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3756 if (pi->thermal_protection)
3757 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3759 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3763 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3764 enum amdgpu_dpm_auto_throttle_src source,
3767 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3770 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3771 pi->active_auto_throttle_sources |= 1 << source;
3772 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3775 if (pi->active_auto_throttle_sources & (1 << source)) {
3776 pi->active_auto_throttle_sources &= ~(1 << source);
3777 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3782 static void si_start_dpm(struct amdgpu_device *adev)
3784 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3787 static void si_stop_dpm(struct amdgpu_device *adev)
3789 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3792 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3795 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3797 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3802 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3807 if (thermal_level == 0) {
3808 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3809 if (ret == PPSMC_Result_OK)
3817 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3819 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3824 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3827 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3834 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3835 PPSMC_Msg msg, u32 parameter)
3837 WREG32(SMC_SCRATCH0, parameter);
3838 return amdgpu_si_send_msg_to_smc(adev, msg);
3841 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3843 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3846 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3850 static int si_dpm_force_performance_level(void *handle,
3851 enum amd_dpm_forced_level level)
3853 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3854 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3855 struct si_ps *ps = si_get_ps(rps);
3856 u32 levels = ps->performance_level_count;
3858 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3859 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3862 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3864 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3865 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3868 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3870 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3871 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3874 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3878 adev->pm.dpm.forced_level = level;
3884 static int si_set_boot_state(struct amdgpu_device *adev)
3886 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3891 static int si_set_sw_state(struct amdgpu_device *adev)
3893 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3897 static int si_halt_smc(struct amdgpu_device *adev)
3899 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3902 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3906 static int si_resume_smc(struct amdgpu_device *adev)
3908 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3911 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3915 static void si_dpm_start_smc(struct amdgpu_device *adev)
3917 amdgpu_si_program_jump_on_start(adev);
3918 amdgpu_si_start_smc(adev);
3919 amdgpu_si_smc_clock(adev, true);
3922 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3924 amdgpu_si_reset_smc(adev);
3925 amdgpu_si_smc_clock(adev, false);
3928 static int si_process_firmware_header(struct amdgpu_device *adev)
3930 struct si_power_info *si_pi = si_get_pi(adev);
3934 ret = amdgpu_si_read_smc_sram_dword(adev,
3935 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3936 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3937 &tmp, si_pi->sram_end);
3941 si_pi->state_table_start = tmp;
3943 ret = amdgpu_si_read_smc_sram_dword(adev,
3944 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3945 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3946 &tmp, si_pi->sram_end);
3950 si_pi->soft_regs_start = tmp;
3952 ret = amdgpu_si_read_smc_sram_dword(adev,
3953 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3954 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3955 &tmp, si_pi->sram_end);
3959 si_pi->mc_reg_table_start = tmp;
3961 ret = amdgpu_si_read_smc_sram_dword(adev,
3962 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3963 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3964 &tmp, si_pi->sram_end);
3968 si_pi->fan_table_start = tmp;
3970 ret = amdgpu_si_read_smc_sram_dword(adev,
3971 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3972 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3973 &tmp, si_pi->sram_end);
3977 si_pi->arb_table_start = tmp;
3979 ret = amdgpu_si_read_smc_sram_dword(adev,
3980 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3981 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3982 &tmp, si_pi->sram_end);
3986 si_pi->cac_table_start = tmp;
3988 ret = amdgpu_si_read_smc_sram_dword(adev,
3989 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3990 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3991 &tmp, si_pi->sram_end);
3995 si_pi->dte_table_start = tmp;
3997 ret = amdgpu_si_read_smc_sram_dword(adev,
3998 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3999 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4000 &tmp, si_pi->sram_end);
4004 si_pi->spll_table_start = tmp;
4006 ret = amdgpu_si_read_smc_sram_dword(adev,
4007 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4008 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4009 &tmp, si_pi->sram_end);
4013 si_pi->papm_cfg_table_start = tmp;
4018 static void si_read_clock_registers(struct amdgpu_device *adev)
4020 struct si_power_info *si_pi = si_get_pi(adev);
4022 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4023 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4024 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4025 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4026 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4027 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4028 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4029 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4030 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4031 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4032 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4033 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4034 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4035 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4036 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4039 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4043 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4045 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4048 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4050 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4054 static int si_enter_ulp_state(struct amdgpu_device *adev)
4056 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4063 static int si_exit_ulp_state(struct amdgpu_device *adev)
4067 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4071 for (i = 0; i < adev->usec_timeout; i++) {
4072 if (RREG32(SMC_RESP_0) == 1)
4081 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4084 PPSMC_Msg msg = has_display ?
4085 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4087 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4091 static void si_program_response_times(struct amdgpu_device *adev)
4093 u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4094 u32 vddc_dly, acpi_dly, vbi_dly;
4095 u32 reference_clock;
4097 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4099 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4101 if (voltage_response_time == 0)
4102 voltage_response_time = 1000;
4104 acpi_delay_time = 15000;
4105 vbi_time_out = 100000;
4107 reference_clock = amdgpu_asic_get_xclk(adev);
4109 vddc_dly = (voltage_response_time * reference_clock) / 100;
4110 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4111 vbi_dly = (vbi_time_out * reference_clock) / 100;
4113 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4114 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4115 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4116 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4119 static void si_program_ds_registers(struct amdgpu_device *adev)
4121 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4124 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4125 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4130 if (eg_pi->sclk_deep_sleep) {
4131 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4132 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4133 ~AUTOSCALE_ON_SS_CLEAR);
4137 static void si_program_display_gap(struct amdgpu_device *adev)
4142 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4143 if (adev->pm.dpm.new_active_crtc_count > 0)
4144 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4146 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4148 if (adev->pm.dpm.new_active_crtc_count > 1)
4149 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4151 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4153 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4155 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4156 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4158 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4159 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4160 /* find the first active crtc */
4161 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4162 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4165 if (i == adev->mode_info.num_crtc)
4170 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4171 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4172 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4175 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4176 * This can be a problem on PowerXpress systems or if you want to use the card
4177 * for offscreen rendering or compute if there are no crtcs enabled.
4179 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4182 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4184 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4188 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4190 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4191 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4195 static void si_setup_bsp(struct amdgpu_device *adev)
4197 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4198 u32 xclk = amdgpu_asic_get_xclk(adev);
4200 r600_calculate_u_and_p(pi->asi,
4206 r600_calculate_u_and_p(pi->pasi,
4213 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4214 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4216 WREG32(CG_BSP, pi->dsp);
4219 static void si_program_git(struct amdgpu_device *adev)
4221 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4224 static void si_program_tp(struct amdgpu_device *adev)
4227 enum r600_td td = R600_TD_DFLT;
4229 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4230 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4232 if (td == R600_TD_AUTO)
4233 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4235 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4237 if (td == R600_TD_UP)
4238 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4240 if (td == R600_TD_DOWN)
4241 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4244 static void si_program_tpp(struct amdgpu_device *adev)
4246 WREG32(CG_TPC, R600_TPC_DFLT);
4249 static void si_program_sstp(struct amdgpu_device *adev)
4251 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4254 static void si_enable_display_gap(struct amdgpu_device *adev)
4256 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4258 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4259 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4260 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4262 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4263 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4264 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4265 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4268 static void si_program_vc(struct amdgpu_device *adev)
4270 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4272 WREG32(CG_FTV, pi->vrc);
4275 static void si_clear_vc(struct amdgpu_device *adev)
4280 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4284 if (memory_clock < 10000)
4286 else if (memory_clock >= 80000)
4287 mc_para_index = 0x0f;
4289 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4290 return mc_para_index;
4293 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4298 if (memory_clock < 12500)
4299 mc_para_index = 0x00;
4300 else if (memory_clock > 47500)
4301 mc_para_index = 0x0f;
4303 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4305 if (memory_clock < 65000)
4306 mc_para_index = 0x00;
4307 else if (memory_clock > 135000)
4308 mc_para_index = 0x0f;
4310 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4312 return mc_para_index;
4315 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4317 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4318 bool strobe_mode = false;
4321 if (mclk <= pi->mclk_strobe_mode_threshold)
4324 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4325 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4327 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4330 result |= SISLANDS_SMC_STROBE_ENABLE;
4335 static int si_upload_firmware(struct amdgpu_device *adev)
4337 struct si_power_info *si_pi = si_get_pi(adev);
4339 amdgpu_si_reset_smc(adev);
4340 amdgpu_si_smc_clock(adev, false);
4342 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4345 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4346 const struct atom_voltage_table *table,
4347 const struct amdgpu_phase_shedding_limits_table *limits)
4349 u32 data, num_bits, num_levels;
4351 if ((table == NULL) || (limits == NULL))
4354 data = table->mask_low;
4356 num_bits = hweight32(data);
4361 num_levels = (1 << num_bits);
4363 if (table->count != num_levels)
4366 if (limits->count != (num_levels - 1))
4372 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4373 u32 max_voltage_steps,
4374 struct atom_voltage_table *voltage_table)
4376 unsigned int i, diff;
4378 if (voltage_table->count <= max_voltage_steps)
4381 diff = voltage_table->count - max_voltage_steps;
4383 for (i= 0; i < max_voltage_steps; i++)
4384 voltage_table->entries[i] = voltage_table->entries[i + diff];
4386 voltage_table->count = max_voltage_steps;
4389 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4390 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4391 struct atom_voltage_table *voltage_table)
4395 if (voltage_dependency_table == NULL)
4398 voltage_table->mask_low = 0;
4399 voltage_table->phase_delay = 0;
4401 voltage_table->count = voltage_dependency_table->count;
4402 for (i = 0; i < voltage_table->count; i++) {
4403 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4404 voltage_table->entries[i].smio_low = 0;
4410 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4412 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4413 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4414 struct si_power_info *si_pi = si_get_pi(adev);
4417 if (pi->voltage_control) {
4418 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4419 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4423 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4424 si_trim_voltage_table_to_fit_state_table(adev,
4425 SISLANDS_MAX_NO_VREG_STEPS,
4426 &eg_pi->vddc_voltage_table);
4427 } else if (si_pi->voltage_control_svi2) {
4428 ret = si_get_svi2_voltage_table(adev,
4429 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4430 &eg_pi->vddc_voltage_table);
4437 if (eg_pi->vddci_control) {
4438 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4439 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4443 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4444 si_trim_voltage_table_to_fit_state_table(adev,
4445 SISLANDS_MAX_NO_VREG_STEPS,
4446 &eg_pi->vddci_voltage_table);
4448 if (si_pi->vddci_control_svi2) {
4449 ret = si_get_svi2_voltage_table(adev,
4450 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4451 &eg_pi->vddci_voltage_table);
4456 if (pi->mvdd_control) {
4457 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4458 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4461 pi->mvdd_control = false;
4465 if (si_pi->mvdd_voltage_table.count == 0) {
4466 pi->mvdd_control = false;
4470 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4471 si_trim_voltage_table_to_fit_state_table(adev,
4472 SISLANDS_MAX_NO_VREG_STEPS,
4473 &si_pi->mvdd_voltage_table);
4476 if (si_pi->vddc_phase_shed_control) {
4477 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4478 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4480 si_pi->vddc_phase_shed_control = false;
4482 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4483 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4484 si_pi->vddc_phase_shed_control = false;
4490 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4491 const struct atom_voltage_table *voltage_table,
4492 SISLANDS_SMC_STATETABLE *table)
4496 for (i = 0; i < voltage_table->count; i++)
4497 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4500 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4501 SISLANDS_SMC_STATETABLE *table)
4503 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4504 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4505 struct si_power_info *si_pi = si_get_pi(adev);
4508 if (si_pi->voltage_control_svi2) {
4509 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4510 si_pi->svc_gpio_id);
4511 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4512 si_pi->svd_gpio_id);
4513 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4516 if (eg_pi->vddc_voltage_table.count) {
4517 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4518 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4519 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4521 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4522 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4523 table->maxVDDCIndexInPPTable = i;
4529 if (eg_pi->vddci_voltage_table.count) {
4530 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4532 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4533 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4537 if (si_pi->mvdd_voltage_table.count) {
4538 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4540 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4541 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4544 if (si_pi->vddc_phase_shed_control) {
4545 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4546 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4547 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4549 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4550 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4552 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4553 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4555 si_pi->vddc_phase_shed_control = false;
4563 static int si_populate_voltage_value(struct amdgpu_device *adev,
4564 const struct atom_voltage_table *table,
4565 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4569 for (i = 0; i < table->count; i++) {
4570 if (value <= table->entries[i].value) {
4571 voltage->index = (u8)i;
4572 voltage->value = cpu_to_be16(table->entries[i].value);
4577 if (i >= table->count)
4583 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4584 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4586 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4587 struct si_power_info *si_pi = si_get_pi(adev);
4589 if (pi->mvdd_control) {
4590 if (mclk <= pi->mvdd_split_frequency)
4593 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4595 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4600 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4601 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4605 bool voltage_found = false;
4606 *std_voltage = be16_to_cpu(voltage->value);
4608 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4609 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4610 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4613 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4614 if (be16_to_cpu(voltage->value) ==
4615 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4616 voltage_found = true;
4617 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4619 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4622 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4627 if (!voltage_found) {
4628 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4629 if (be16_to_cpu(voltage->value) <=
4630 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4631 voltage_found = true;
4632 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4634 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4637 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4643 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4644 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4651 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4652 u16 value, u8 index,
4653 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4655 voltage->index = index;
4656 voltage->value = cpu_to_be16(value);
4661 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4662 const struct amdgpu_phase_shedding_limits_table *limits,
4663 u16 voltage, u32 sclk, u32 mclk,
4664 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4668 for (i = 0; i < limits->count; i++) {
4669 if ((voltage <= limits->entries[i].voltage) &&
4670 (sclk <= limits->entries[i].sclk) &&
4671 (mclk <= limits->entries[i].mclk))
4675 smc_voltage->phase_settings = (u8)i;
4680 static int si_init_arb_table_index(struct amdgpu_device *adev)
4682 struct si_power_info *si_pi = si_get_pi(adev);
4686 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4687 &tmp, si_pi->sram_end);
4692 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4694 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4695 tmp, si_pi->sram_end);
4698 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4700 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4703 static int si_reset_to_default(struct amdgpu_device *adev)
4705 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4709 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4711 struct si_power_info *si_pi = si_get_pi(adev);
4715 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4716 &tmp, si_pi->sram_end);
4720 tmp = (tmp >> 24) & 0xff;
4722 if (tmp == MC_CG_ARB_FREQ_F0)
4725 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4728 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4732 u32 dram_refresh_rate;
4733 u32 mc_arb_rfsh_rate;
4734 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4739 dram_rows = 1 << (tmp + 10);
4741 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4742 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4744 return mc_arb_rfsh_rate;
4747 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4748 struct rv7xx_pl *pl,
4749 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4755 arb_regs->mc_arb_rfsh_rate =
4756 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4758 amdgpu_atombios_set_engine_dram_timings(adev,
4762 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4763 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4764 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4766 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4767 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4768 arb_regs->mc_arb_burst_time = (u8)burst_time;
4773 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4774 struct amdgpu_ps *amdgpu_state,
4775 unsigned int first_arb_set)
4777 struct si_power_info *si_pi = si_get_pi(adev);
4778 struct si_ps *state = si_get_ps(amdgpu_state);
4779 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4782 for (i = 0; i < state->performance_level_count; i++) {
4783 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4786 ret = amdgpu_si_copy_bytes_to_smc(adev,
4787 si_pi->arb_table_start +
4788 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4789 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4791 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4800 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4801 struct amdgpu_ps *amdgpu_new_state)
4803 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4804 SISLANDS_DRIVER_STATE_ARB_INDEX);
4807 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4808 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4810 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4811 struct si_power_info *si_pi = si_get_pi(adev);
4813 if (pi->mvdd_control)
4814 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4815 si_pi->mvdd_bootup_value, voltage);
4820 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4821 struct amdgpu_ps *amdgpu_initial_state,
4822 SISLANDS_SMC_STATETABLE *table)
4824 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4825 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4826 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4827 struct si_power_info *si_pi = si_get_pi(adev);
4831 table->initialState.levels[0].mclk.vDLL_CNTL =
4832 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4833 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4834 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4835 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4836 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4837 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4838 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4839 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4840 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4841 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4842 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4843 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4844 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4845 table->initialState.levels[0].mclk.vMPLL_SS =
4846 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4847 table->initialState.levels[0].mclk.vMPLL_SS2 =
4848 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4850 table->initialState.levels[0].mclk.mclk_value =
4851 cpu_to_be32(initial_state->performance_levels[0].mclk);
4853 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4854 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4855 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4856 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4857 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4858 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4859 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4860 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4861 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4862 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4863 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4864 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4866 table->initialState.levels[0].sclk.sclk_value =
4867 cpu_to_be32(initial_state->performance_levels[0].sclk);
4869 table->initialState.levels[0].arbRefreshState =
4870 SISLANDS_INITIAL_STATE_ARB_INDEX;
4872 table->initialState.levels[0].ACIndex = 0;
4874 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4875 initial_state->performance_levels[0].vddc,
4876 &table->initialState.levels[0].vddc);
4881 ret = si_get_std_voltage_value(adev,
4882 &table->initialState.levels[0].vddc,
4885 si_populate_std_voltage_value(adev, std_vddc,
4886 table->initialState.levels[0].vddc.index,
4887 &table->initialState.levels[0].std_vddc);
4890 if (eg_pi->vddci_control)
4891 si_populate_voltage_value(adev,
4892 &eg_pi->vddci_voltage_table,
4893 initial_state->performance_levels[0].vddci,
4894 &table->initialState.levels[0].vddci);
4896 if (si_pi->vddc_phase_shed_control)
4897 si_populate_phase_shedding_value(adev,
4898 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4899 initial_state->performance_levels[0].vddc,
4900 initial_state->performance_levels[0].sclk,
4901 initial_state->performance_levels[0].mclk,
4902 &table->initialState.levels[0].vddc);
4904 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4906 reg = CG_R(0xffff) | CG_L(0);
4907 table->initialState.levels[0].aT = cpu_to_be32(reg);
4908 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4909 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4911 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4912 table->initialState.levels[0].strobeMode =
4913 si_get_strobe_mode_settings(adev,
4914 initial_state->performance_levels[0].mclk);
4916 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4917 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4919 table->initialState.levels[0].mcFlags = 0;
4922 table->initialState.levelCount = 1;
4924 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4926 table->initialState.levels[0].dpm2.MaxPS = 0;
4927 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4928 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4929 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4930 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4932 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4933 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4935 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4936 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4941 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4942 SISLANDS_SMC_STATETABLE *table)
4944 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4945 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4946 struct si_power_info *si_pi = si_get_pi(adev);
4947 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4948 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4949 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4950 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4951 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4952 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4953 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4954 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4955 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4956 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4957 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4961 table->ACPIState = table->initialState;
4963 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4965 if (pi->acpi_vddc) {
4966 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4967 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4971 ret = si_get_std_voltage_value(adev,
4972 &table->ACPIState.levels[0].vddc, &std_vddc);
4974 si_populate_std_voltage_value(adev, std_vddc,
4975 table->ACPIState.levels[0].vddc.index,
4976 &table->ACPIState.levels[0].std_vddc);
4978 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4980 if (si_pi->vddc_phase_shed_control) {
4981 si_populate_phase_shedding_value(adev,
4982 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4986 &table->ACPIState.levels[0].vddc);
4989 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4990 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4994 ret = si_get_std_voltage_value(adev,
4995 &table->ACPIState.levels[0].vddc, &std_vddc);
4998 si_populate_std_voltage_value(adev, std_vddc,
4999 table->ACPIState.levels[0].vddc.index,
5000 &table->ACPIState.levels[0].std_vddc);
5002 table->ACPIState.levels[0].gen2PCIE =
5003 (u8)amdgpu_get_pcie_gen_support(adev,
5004 si_pi->sys_pcie_mask,
5005 si_pi->boot_pcie_gen,
5008 if (si_pi->vddc_phase_shed_control)
5009 si_populate_phase_shedding_value(adev,
5010 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5011 pi->min_vddc_in_table,
5014 &table->ACPIState.levels[0].vddc);
5017 if (pi->acpi_vddc) {
5018 if (eg_pi->acpi_vddci)
5019 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5021 &table->ACPIState.levels[0].vddci);
5024 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5025 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5027 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5029 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5030 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5032 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5033 cpu_to_be32(dll_cntl);
5034 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5035 cpu_to_be32(mclk_pwrmgt_cntl);
5036 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5037 cpu_to_be32(mpll_ad_func_cntl);
5038 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5039 cpu_to_be32(mpll_dq_func_cntl);
5040 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5041 cpu_to_be32(mpll_func_cntl);
5042 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5043 cpu_to_be32(mpll_func_cntl_1);
5044 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5045 cpu_to_be32(mpll_func_cntl_2);
5046 table->ACPIState.levels[0].mclk.vMPLL_SS =
5047 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5048 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5049 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5051 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5052 cpu_to_be32(spll_func_cntl);
5053 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5054 cpu_to_be32(spll_func_cntl_2);
5055 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5056 cpu_to_be32(spll_func_cntl_3);
5057 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5058 cpu_to_be32(spll_func_cntl_4);
5060 table->ACPIState.levels[0].mclk.mclk_value = 0;
5061 table->ACPIState.levels[0].sclk.sclk_value = 0;
5063 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5065 if (eg_pi->dynamic_ac_timing)
5066 table->ACPIState.levels[0].ACIndex = 0;
5068 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5069 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5070 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5071 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5072 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5074 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5075 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5077 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5078 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5083 static int si_populate_ulv_state(struct amdgpu_device *adev,
5084 SISLANDS_SMC_SWSTATE *state)
5086 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5087 struct si_power_info *si_pi = si_get_pi(adev);
5088 struct si_ulv_param *ulv = &si_pi->ulv;
5089 u32 sclk_in_sr = 1350; /* ??? */
5092 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5095 if (eg_pi->sclk_deep_sleep) {
5096 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5097 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5099 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5101 if (ulv->one_pcie_lane_in_ulv)
5102 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5103 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5104 state->levels[0].ACIndex = 1;
5105 state->levels[0].std_vddc = state->levels[0].vddc;
5106 state->levelCount = 1;
5108 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5114 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5116 struct si_power_info *si_pi = si_get_pi(adev);
5117 struct si_ulv_param *ulv = &si_pi->ulv;
5118 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5121 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5126 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5127 ulv->volt_change_delay);
5129 ret = amdgpu_si_copy_bytes_to_smc(adev,
5130 si_pi->arb_table_start +
5131 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5132 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5134 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5140 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5142 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5144 pi->mvdd_split_frequency = 30000;
5147 static int si_init_smc_table(struct amdgpu_device *adev)
5149 struct si_power_info *si_pi = si_get_pi(adev);
5150 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5151 const struct si_ulv_param *ulv = &si_pi->ulv;
5152 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5157 si_populate_smc_voltage_tables(adev, table);
5159 switch (adev->pm.int_thermal_type) {
5160 case THERMAL_TYPE_SI:
5161 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5162 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5164 case THERMAL_TYPE_NONE:
5165 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5168 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5172 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5173 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5175 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5176 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5177 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5180 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5181 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5183 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5184 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5186 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5187 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5189 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5190 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5191 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5192 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5196 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5200 ret = si_populate_smc_acpi_state(adev, table);
5204 table->driverState = table->initialState;
5206 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5207 SISLANDS_INITIAL_STATE_ARB_INDEX);
5211 if (ulv->supported && ulv->pl.vddc) {
5212 ret = si_populate_ulv_state(adev, &table->ULVState);
5216 ret = si_program_ulv_memory_timing_parameters(adev);
5220 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5221 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5223 lane_width = amdgpu_get_pcie_lanes(adev);
5224 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5226 table->ULVState = table->initialState;
5229 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5230 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5234 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5236 SISLANDS_SMC_SCLK_VALUE *sclk)
5238 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5239 struct si_power_info *si_pi = si_get_pi(adev);
5240 struct atom_clock_dividers dividers;
5241 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5242 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5243 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5244 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5245 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5246 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5248 u32 reference_clock = adev->clock.spll.reference_freq;
5249 u32 reference_divider;
5253 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5254 engine_clock, false, ÷rs);
5258 reference_divider = 1 + dividers.ref_div;
5260 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5261 do_div(tmp, reference_clock);
5264 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5265 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5266 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5268 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5269 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5271 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5272 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5273 spll_func_cntl_3 |= SPLL_DITHEN;
5276 struct amdgpu_atom_ss ss;
5277 u32 vco_freq = engine_clock * dividers.post_div;
5279 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5280 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5281 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5282 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5284 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5285 cg_spll_spread_spectrum |= CLK_S(clk_s);
5286 cg_spll_spread_spectrum |= SSEN;
5288 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5289 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5293 sclk->sclk_value = engine_clock;
5294 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5295 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5296 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5297 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5298 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5299 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5304 static int si_populate_sclk_value(struct amdgpu_device *adev,
5306 SISLANDS_SMC_SCLK_VALUE *sclk)
5308 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5311 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5313 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5314 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5315 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5316 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5317 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5318 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5319 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5325 static int si_populate_mclk_value(struct amdgpu_device *adev,
5328 SISLANDS_SMC_MCLK_VALUE *mclk,
5332 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5333 struct si_power_info *si_pi = si_get_pi(adev);
5334 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5335 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5336 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5337 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5338 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5339 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5340 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5341 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5342 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5343 struct atom_mpll_param mpll_param;
5346 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5350 mpll_func_cntl &= ~BWCTRL_MASK;
5351 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5353 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5354 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5355 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5357 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5358 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5360 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5361 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5362 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5363 YCLK_POST_DIV(mpll_param.post_div);
5367 struct amdgpu_atom_ss ss;
5370 u32 reference_clock = adev->clock.mpll.reference_freq;
5372 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5373 freq_nom = memory_clock * 4;
5375 freq_nom = memory_clock * 2;
5377 tmp = freq_nom / reference_clock;
5379 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5380 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5381 u32 clks = reference_clock * 5 / ss.rate;
5382 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5384 mpll_ss1 &= ~CLKV_MASK;
5385 mpll_ss1 |= CLKV(clkv);
5387 mpll_ss2 &= ~CLKS_MASK;
5388 mpll_ss2 |= CLKS(clks);
5392 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5393 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5396 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5398 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5400 mclk->mclk_value = cpu_to_be32(memory_clock);
5401 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5402 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5403 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5404 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5405 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5406 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5407 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5408 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5409 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5414 static void si_populate_smc_sp(struct amdgpu_device *adev,
5415 struct amdgpu_ps *amdgpu_state,
5416 SISLANDS_SMC_SWSTATE *smc_state)
5418 struct si_ps *ps = si_get_ps(amdgpu_state);
5419 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5422 for (i = 0; i < ps->performance_level_count - 1; i++)
5423 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5425 smc_state->levels[ps->performance_level_count - 1].bSP =
5426 cpu_to_be32(pi->psp);
5429 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5430 struct rv7xx_pl *pl,
5431 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5433 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5434 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5435 struct si_power_info *si_pi = si_get_pi(adev);
5439 bool gmc_pg = false;
5441 if (eg_pi->pcie_performance_request &&
5442 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5443 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5445 level->gen2PCIE = (u8)pl->pcie_gen;
5447 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5453 if (pi->mclk_stutter_mode_threshold &&
5454 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5455 !eg_pi->uvd_enabled &&
5456 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5457 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5458 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5461 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5464 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5465 if (pl->mclk > pi->mclk_edc_enable_threshold)
5466 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5468 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5469 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5471 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5473 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5474 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5475 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5476 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5478 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5480 dll_state_on = false;
5483 level->strobeMode = si_get_strobe_mode_settings(adev,
5486 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5489 ret = si_populate_mclk_value(adev,
5493 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5497 ret = si_populate_voltage_value(adev,
5498 &eg_pi->vddc_voltage_table,
5499 pl->vddc, &level->vddc);
5504 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5508 ret = si_populate_std_voltage_value(adev, std_vddc,
5509 level->vddc.index, &level->std_vddc);
5513 if (eg_pi->vddci_control) {
5514 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5515 pl->vddci, &level->vddci);
5520 if (si_pi->vddc_phase_shed_control) {
5521 ret = si_populate_phase_shedding_value(adev,
5522 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5531 level->MaxPoweredUpCU = si_pi->max_cu;
5533 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5538 static int si_populate_smc_t(struct amdgpu_device *adev,
5539 struct amdgpu_ps *amdgpu_state,
5540 SISLANDS_SMC_SWSTATE *smc_state)
5542 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5543 struct si_ps *state = si_get_ps(amdgpu_state);
5549 if (state->performance_level_count >= 9)
5552 if (state->performance_level_count < 2) {
5553 a_t = CG_R(0xffff) | CG_L(0);
5554 smc_state->levels[0].aT = cpu_to_be32(a_t);
5558 smc_state->levels[0].aT = cpu_to_be32(0);
5560 for (i = 0; i <= state->performance_level_count - 2; i++) {
5561 ret = r600_calculate_at(
5562 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5564 state->performance_levels[i + 1].sclk,
5565 state->performance_levels[i].sclk,
5570 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5571 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5574 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5575 a_t |= CG_R(t_l * pi->bsp / 20000);
5576 smc_state->levels[i].aT = cpu_to_be32(a_t);
5578 high_bsp = (i == state->performance_level_count - 2) ?
5580 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5581 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5587 static int si_disable_ulv(struct amdgpu_device *adev)
5589 struct si_power_info *si_pi = si_get_pi(adev);
5590 struct si_ulv_param *ulv = &si_pi->ulv;
5593 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5599 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5600 struct amdgpu_ps *amdgpu_state)
5602 const struct si_power_info *si_pi = si_get_pi(adev);
5603 const struct si_ulv_param *ulv = &si_pi->ulv;
5604 const struct si_ps *state = si_get_ps(amdgpu_state);
5607 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5610 /* XXX validate against display requirements! */
5612 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5613 if (adev->clock.current_dispclk <=
5614 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5616 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5621 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5627 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5628 struct amdgpu_ps *amdgpu_new_state)
5630 const struct si_power_info *si_pi = si_get_pi(adev);
5631 const struct si_ulv_param *ulv = &si_pi->ulv;
5633 if (ulv->supported) {
5634 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5635 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5641 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5642 struct amdgpu_ps *amdgpu_state,
5643 SISLANDS_SMC_SWSTATE *smc_state)
5645 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5646 struct ni_power_info *ni_pi = ni_get_pi(adev);
5647 struct si_power_info *si_pi = si_get_pi(adev);
5648 struct si_ps *state = si_get_ps(amdgpu_state);
5651 u32 sclk_in_sr = 1350; /* ??? */
5653 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5656 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5658 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5659 eg_pi->uvd_enabled = true;
5660 if (eg_pi->smu_uvd_hs)
5661 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5663 eg_pi->uvd_enabled = false;
5666 if (state->dc_compatible)
5667 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5669 smc_state->levelCount = 0;
5670 for (i = 0; i < state->performance_level_count; i++) {
5671 if (eg_pi->sclk_deep_sleep) {
5672 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5673 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5674 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5676 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5680 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5681 &smc_state->levels[i]);
5682 smc_state->levels[i].arbRefreshState =
5683 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5688 if (ni_pi->enable_power_containment)
5689 smc_state->levels[i].displayWatermark =
5690 (state->performance_levels[i].sclk < threshold) ?
5691 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5693 smc_state->levels[i].displayWatermark = (i < 2) ?
5694 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5696 if (eg_pi->dynamic_ac_timing)
5697 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5699 smc_state->levels[i].ACIndex = 0;
5701 smc_state->levelCount++;
5704 si_write_smc_soft_register(adev,
5705 SI_SMC_SOFT_REGISTER_watermark_threshold,
5708 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5710 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5712 ni_pi->enable_power_containment = false;
5714 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5716 ni_pi->enable_sq_ramping = false;
5718 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5721 static int si_upload_sw_state(struct amdgpu_device *adev,
5722 struct amdgpu_ps *amdgpu_new_state)
5724 struct si_power_info *si_pi = si_get_pi(adev);
5725 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5727 u32 address = si_pi->state_table_start +
5728 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5729 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5730 ((new_state->performance_level_count - 1) *
5731 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5732 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5734 memset(smc_state, 0, state_size);
5736 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5740 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5741 state_size, si_pi->sram_end);
5744 static int si_upload_ulv_state(struct amdgpu_device *adev)
5746 struct si_power_info *si_pi = si_get_pi(adev);
5747 struct si_ulv_param *ulv = &si_pi->ulv;
5750 if (ulv->supported && ulv->pl.vddc) {
5751 u32 address = si_pi->state_table_start +
5752 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5753 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5754 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5756 memset(smc_state, 0, state_size);
5758 ret = si_populate_ulv_state(adev, smc_state);
5760 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5761 state_size, si_pi->sram_end);
5767 static int si_upload_smc_data(struct amdgpu_device *adev)
5769 struct amdgpu_crtc *amdgpu_crtc = NULL;
5772 if (adev->pm.dpm.new_active_crtc_count == 0)
5775 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5776 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5777 amdgpu_crtc = adev->mode_info.crtcs[i];
5782 if (amdgpu_crtc == NULL)
5785 if (amdgpu_crtc->line_time <= 0)
5788 if (si_write_smc_soft_register(adev,
5789 SI_SMC_SOFT_REGISTER_crtc_index,
5790 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5793 if (si_write_smc_soft_register(adev,
5794 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5795 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5798 if (si_write_smc_soft_register(adev,
5799 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5800 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5806 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5807 struct si_mc_reg_table *table)
5812 for (i = 0, j = table->last; i < table->last; i++) {
5813 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5815 switch (table->mc_reg_address[i].s1) {
5817 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5818 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5819 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5820 for (k = 0; k < table->num_entries; k++)
5821 table->mc_reg_table_entry[k].mc_data[j] =
5822 ((temp_reg & 0xffff0000)) |
5823 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5826 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5828 temp_reg = RREG32(MC_PMG_CMD_MRS);
5829 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5830 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5831 for (k = 0; k < table->num_entries; k++) {
5832 table->mc_reg_table_entry[k].mc_data[j] =
5833 (temp_reg & 0xffff0000) |
5834 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5835 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5836 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5840 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5841 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5843 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5844 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5845 for (k = 0; k < table->num_entries; k++)
5846 table->mc_reg_table_entry[k].mc_data[j] =
5847 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5851 case MC_SEQ_RESERVE_M:
5852 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5853 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5854 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5855 for(k = 0; k < table->num_entries; k++)
5856 table->mc_reg_table_entry[k].mc_data[j] =
5857 (temp_reg & 0xffff0000) |
5858 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5871 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5875 case MC_SEQ_RAS_TIMING:
5876 *out_reg = MC_SEQ_RAS_TIMING_LP;
5878 case MC_SEQ_CAS_TIMING:
5879 *out_reg = MC_SEQ_CAS_TIMING_LP;
5881 case MC_SEQ_MISC_TIMING:
5882 *out_reg = MC_SEQ_MISC_TIMING_LP;
5884 case MC_SEQ_MISC_TIMING2:
5885 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5887 case MC_SEQ_RD_CTL_D0:
5888 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5890 case MC_SEQ_RD_CTL_D1:
5891 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5893 case MC_SEQ_WR_CTL_D0:
5894 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5896 case MC_SEQ_WR_CTL_D1:
5897 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5899 case MC_PMG_CMD_EMRS:
5900 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5902 case MC_PMG_CMD_MRS:
5903 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5905 case MC_PMG_CMD_MRS1:
5906 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5908 case MC_SEQ_PMG_TIMING:
5909 *out_reg = MC_SEQ_PMG_TIMING_LP;
5911 case MC_PMG_CMD_MRS2:
5912 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5914 case MC_SEQ_WR_CTL_2:
5915 *out_reg = MC_SEQ_WR_CTL_2_LP;
5925 static void si_set_valid_flag(struct si_mc_reg_table *table)
5929 for (i = 0; i < table->last; i++) {
5930 for (j = 1; j < table->num_entries; j++) {
5931 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5932 table->valid_flag |= 1 << i;
5939 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5944 for (i = 0; i < table->last; i++)
5945 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5946 address : table->mc_reg_address[i].s1;
5950 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5951 struct si_mc_reg_table *si_table)
5955 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5957 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5960 for (i = 0; i < table->last; i++)
5961 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5962 si_table->last = table->last;
5964 for (i = 0; i < table->num_entries; i++) {
5965 si_table->mc_reg_table_entry[i].mclk_max =
5966 table->mc_reg_table_entry[i].mclk_max;
5967 for (j = 0; j < table->last; j++) {
5968 si_table->mc_reg_table_entry[i].mc_data[j] =
5969 table->mc_reg_table_entry[i].mc_data[j];
5972 si_table->num_entries = table->num_entries;
5977 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5979 struct si_power_info *si_pi = si_get_pi(adev);
5980 struct atom_mc_reg_table *table;
5981 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5982 u8 module_index = rv770_get_memory_module_index(adev);
5985 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5989 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5990 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5991 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5992 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5993 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5994 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5995 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5996 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5997 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5998 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5999 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6000 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6001 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6002 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6004 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6008 ret = si_copy_vbios_mc_reg_table(table, si_table);
6012 si_set_s0_mc_reg_index(si_table);
6014 ret = si_set_mc_special_registers(adev, si_table);
6018 si_set_valid_flag(si_table);
6027 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6028 SMC_SIslands_MCRegisters *mc_reg_table)
6030 struct si_power_info *si_pi = si_get_pi(adev);
6033 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6034 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6035 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6037 mc_reg_table->address[i].s0 =
6038 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6039 mc_reg_table->address[i].s1 =
6040 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6044 mc_reg_table->last = (u8)i;
6047 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6048 SMC_SIslands_MCRegisterSet *data,
6049 u32 num_entries, u32 valid_flag)
6053 for(i = 0, j = 0; j < num_entries; j++) {
6054 if (valid_flag & (1 << j)) {
6055 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6061 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6062 struct rv7xx_pl *pl,
6063 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6065 struct si_power_info *si_pi = si_get_pi(adev);
6068 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6069 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6073 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6076 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6077 mc_reg_table_data, si_pi->mc_reg_table.last,
6078 si_pi->mc_reg_table.valid_flag);
6081 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6082 struct amdgpu_ps *amdgpu_state,
6083 SMC_SIslands_MCRegisters *mc_reg_table)
6085 struct si_ps *state = si_get_ps(amdgpu_state);
6088 for (i = 0; i < state->performance_level_count; i++) {
6089 si_convert_mc_reg_table_entry_to_smc(adev,
6090 &state->performance_levels[i],
6091 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6095 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6096 struct amdgpu_ps *amdgpu_boot_state)
6098 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6099 struct si_power_info *si_pi = si_get_pi(adev);
6100 struct si_ulv_param *ulv = &si_pi->ulv;
6101 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6103 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6105 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6107 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6109 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6110 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6112 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6113 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6114 si_pi->mc_reg_table.last,
6115 si_pi->mc_reg_table.valid_flag);
6117 if (ulv->supported && ulv->pl.vddc != 0)
6118 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6119 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6121 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6122 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6123 si_pi->mc_reg_table.last,
6124 si_pi->mc_reg_table.valid_flag);
6126 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6128 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6129 (u8 *)smc_mc_reg_table,
6130 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6133 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6134 struct amdgpu_ps *amdgpu_new_state)
6136 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6137 struct si_power_info *si_pi = si_get_pi(adev);
6138 u32 address = si_pi->mc_reg_table_start +
6139 offsetof(SMC_SIslands_MCRegisters,
6140 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6141 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6143 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6145 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6147 return amdgpu_si_copy_bytes_to_smc(adev, address,
6148 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6149 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6153 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6156 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6158 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6161 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6162 struct amdgpu_ps *amdgpu_state)
6164 struct si_ps *state = si_get_ps(amdgpu_state);
6166 u16 pcie_speed, max_speed = 0;
6168 for (i = 0; i < state->performance_level_count; i++) {
6169 pcie_speed = state->performance_levels[i].pcie_gen;
6170 if (max_speed < pcie_speed)
6171 max_speed = pcie_speed;
6176 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6180 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6181 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6183 return (u16)speed_cntl;
6186 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6187 struct amdgpu_ps *amdgpu_new_state,
6188 struct amdgpu_ps *amdgpu_current_state)
6190 struct si_power_info *si_pi = si_get_pi(adev);
6191 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6192 enum amdgpu_pcie_gen current_link_speed;
6194 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6195 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6197 current_link_speed = si_pi->force_pcie_gen;
6199 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6200 si_pi->pspp_notify_required = false;
6201 if (target_link_speed > current_link_speed) {
6202 switch (target_link_speed) {
6203 #if defined(CONFIG_ACPI)
6204 case AMDGPU_PCIE_GEN3:
6205 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6207 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6208 if (current_link_speed == AMDGPU_PCIE_GEN2)
6211 case AMDGPU_PCIE_GEN2:
6212 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6217 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6221 if (target_link_speed < current_link_speed)
6222 si_pi->pspp_notify_required = true;
6226 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6227 struct amdgpu_ps *amdgpu_new_state,
6228 struct amdgpu_ps *amdgpu_current_state)
6230 struct si_power_info *si_pi = si_get_pi(adev);
6231 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6234 if (si_pi->pspp_notify_required) {
6235 if (target_link_speed == AMDGPU_PCIE_GEN3)
6236 request = PCIE_PERF_REQ_PECI_GEN3;
6237 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6238 request = PCIE_PERF_REQ_PECI_GEN2;
6240 request = PCIE_PERF_REQ_PECI_GEN1;
6242 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6243 (si_get_current_pcie_speed(adev) > 0))
6246 #if defined(CONFIG_ACPI)
6247 amdgpu_acpi_pcie_performance_request(adev, request, false);
6253 static int si_ds_request(struct amdgpu_device *adev,
6254 bool ds_status_on, u32 count_write)
6256 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6258 if (eg_pi->sclk_deep_sleep) {
6260 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6264 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6265 PPSMC_Result_OK) ? 0 : -EINVAL;
6271 static void si_set_max_cu_value(struct amdgpu_device *adev)
6273 struct si_power_info *si_pi = si_get_pi(adev);
6275 if (adev->asic_type == CHIP_VERDE) {
6276 switch (adev->pdev->device) {
6312 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6313 struct amdgpu_clock_voltage_dependency_table *table)
6317 u16 leakage_voltage;
6320 for (i = 0; i < table->count; i++) {
6321 switch (si_get_leakage_voltage_from_leakage_index(adev,
6322 table->entries[i].v,
6323 &leakage_voltage)) {
6325 table->entries[i].v = leakage_voltage;
6335 for (j = (table->count - 2); j >= 0; j--) {
6336 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6337 table->entries[j].v : table->entries[j + 1].v;
6343 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6347 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6348 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6350 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6351 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6352 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6354 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6355 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6356 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6358 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6362 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6363 struct amdgpu_ps *amdgpu_new_state,
6364 struct amdgpu_ps *amdgpu_current_state)
6367 u32 new_lane_width =
6368 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6369 u32 current_lane_width =
6370 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6372 if (new_lane_width != current_lane_width) {
6373 amdgpu_set_pcie_lanes(adev, new_lane_width);
6374 lane_width = amdgpu_get_pcie_lanes(adev);
6375 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6379 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6381 si_read_clock_registers(adev);
6382 si_enable_acpi_power_management(adev);
6385 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6388 u32 thermal_int = RREG32(CG_THERMAL_INT);
6391 PPSMC_Result result;
6393 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6394 WREG32(CG_THERMAL_INT, thermal_int);
6395 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6396 if (result != PPSMC_Result_OK) {
6397 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6401 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6402 WREG32(CG_THERMAL_INT, thermal_int);
6408 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6409 int min_temp, int max_temp)
6411 int low_temp = 0 * 1000;
6412 int high_temp = 255 * 1000;
6414 if (low_temp < min_temp)
6415 low_temp = min_temp;
6416 if (high_temp > max_temp)
6417 high_temp = max_temp;
6418 if (high_temp < low_temp) {
6419 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6423 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6424 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6425 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6427 adev->pm.dpm.thermal.min_temp = low_temp;
6428 adev->pm.dpm.thermal.max_temp = high_temp;
6433 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6435 struct si_power_info *si_pi = si_get_pi(adev);
6438 if (si_pi->fan_ctrl_is_in_default_mode) {
6439 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6440 si_pi->fan_ctrl_default_mode = tmp;
6441 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6443 si_pi->fan_ctrl_is_in_default_mode = false;
6446 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6448 WREG32(CG_FDO_CTRL2, tmp);
6450 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6451 tmp |= FDO_PWM_MODE(mode);
6452 WREG32(CG_FDO_CTRL2, tmp);
6455 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6457 struct si_power_info *si_pi = si_get_pi(adev);
6458 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6460 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6461 u16 fdo_min, slope1, slope2;
6462 u32 reference_clock, tmp;
6466 if (!si_pi->fan_table_start) {
6467 adev->pm.dpm.fan.ucode_fan_control = false;
6471 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6474 adev->pm.dpm.fan.ucode_fan_control = false;
6478 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6479 do_div(tmp64, 10000);
6480 fdo_min = (u16)tmp64;
6482 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6483 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6485 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6486 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6488 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6489 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6491 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6492 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6493 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6494 fan_table.slope1 = cpu_to_be16(slope1);
6495 fan_table.slope2 = cpu_to_be16(slope2);
6496 fan_table.fdo_min = cpu_to_be16(fdo_min);
6497 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6498 fan_table.hys_up = cpu_to_be16(1);
6499 fan_table.hys_slope = cpu_to_be16(1);
6500 fan_table.temp_resp_lim = cpu_to_be16(5);
6501 reference_clock = amdgpu_asic_get_xclk(adev);
6503 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6504 reference_clock) / 1600);
6505 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6507 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6508 fan_table.temp_src = (uint8_t)tmp;
6510 ret = amdgpu_si_copy_bytes_to_smc(adev,
6511 si_pi->fan_table_start,
6517 DRM_ERROR("Failed to load fan table to the SMC.");
6518 adev->pm.dpm.fan.ucode_fan_control = false;
6524 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6526 struct si_power_info *si_pi = si_get_pi(adev);
6529 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6530 if (ret == PPSMC_Result_OK) {
6531 si_pi->fan_is_controlled_by_smc = true;
6538 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6540 struct si_power_info *si_pi = si_get_pi(adev);
6543 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6545 if (ret == PPSMC_Result_OK) {
6546 si_pi->fan_is_controlled_by_smc = false;
6553 static int si_dpm_get_fan_speed_percent(void *handle,
6558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6560 if (adev->pm.no_fan)
6563 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6564 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6569 tmp64 = (u64)duty * 100;
6570 do_div(tmp64, duty100);
6571 *speed = (u32)tmp64;
6579 static int si_dpm_set_fan_speed_percent(void *handle,
6582 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6583 struct si_power_info *si_pi = si_get_pi(adev);
6588 if (adev->pm.no_fan)
6591 if (si_pi->fan_is_controlled_by_smc)
6597 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6602 tmp64 = (u64)speed * duty100;
6606 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6607 tmp |= FDO_STATIC_DUTY(duty);
6608 WREG32(CG_FDO_CTRL0, tmp);
6613 static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
6615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6618 /* stop auto-manage */
6619 if (adev->pm.dpm.fan.ucode_fan_control)
6620 si_fan_ctrl_stop_smc_fan_control(adev);
6621 si_fan_ctrl_set_static_mode(adev, mode);
6623 /* restart auto-manage */
6624 if (adev->pm.dpm.fan.ucode_fan_control)
6625 si_thermal_start_smc_fan_control(adev);
6627 si_fan_ctrl_set_default_mode(adev);
6631 static u32 si_dpm_get_fan_control_mode(void *handle)
6633 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6634 struct si_power_info *si_pi = si_get_pi(adev);
6637 if (si_pi->fan_is_controlled_by_smc)
6640 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6641 return (tmp >> FDO_PWM_MODE_SHIFT);
6645 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6649 u32 xclk = amdgpu_asic_get_xclk(adev);
6651 if (adev->pm.no_fan)
6654 if (adev->pm.fan_pulses_per_revolution == 0)
6657 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6658 if (tach_period == 0)
6661 *speed = 60 * xclk * 10000 / tach_period;
6666 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6669 u32 tach_period, tmp;
6670 u32 xclk = amdgpu_asic_get_xclk(adev);
6672 if (adev->pm.no_fan)
6675 if (adev->pm.fan_pulses_per_revolution == 0)
6678 if ((speed < adev->pm.fan_min_rpm) ||
6679 (speed > adev->pm.fan_max_rpm))
6682 if (adev->pm.dpm.fan.ucode_fan_control)
6683 si_fan_ctrl_stop_smc_fan_control(adev);
6685 tach_period = 60 * xclk * 10000 / (8 * speed);
6686 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6687 tmp |= TARGET_PERIOD(tach_period);
6688 WREG32(CG_TACH_CTRL, tmp);
6690 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6696 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6698 struct si_power_info *si_pi = si_get_pi(adev);
6701 if (!si_pi->fan_ctrl_is_in_default_mode) {
6702 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6703 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6704 WREG32(CG_FDO_CTRL2, tmp);
6706 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6707 tmp |= TMIN(si_pi->t_min);
6708 WREG32(CG_FDO_CTRL2, tmp);
6709 si_pi->fan_ctrl_is_in_default_mode = true;
6713 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6715 if (adev->pm.dpm.fan.ucode_fan_control) {
6716 si_fan_ctrl_start_smc_fan_control(adev);
6717 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6721 static void si_thermal_initialize(struct amdgpu_device *adev)
6725 if (adev->pm.fan_pulses_per_revolution) {
6726 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6727 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6728 WREG32(CG_TACH_CTRL, tmp);
6731 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6732 tmp |= TACH_PWM_RESP_RATE(0x28);
6733 WREG32(CG_FDO_CTRL2, tmp);
6736 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6740 si_thermal_initialize(adev);
6741 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6744 ret = si_thermal_enable_alert(adev, true);
6747 if (adev->pm.dpm.fan.ucode_fan_control) {
6748 ret = si_halt_smc(adev);
6751 ret = si_thermal_setup_fan_table(adev);
6754 ret = si_resume_smc(adev);
6757 si_thermal_start_smc_fan_control(adev);
6763 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6765 if (!adev->pm.no_fan) {
6766 si_fan_ctrl_set_default_mode(adev);
6767 si_fan_ctrl_stop_smc_fan_control(adev);
6771 static int si_dpm_enable(struct amdgpu_device *adev)
6773 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6774 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6775 struct si_power_info *si_pi = si_get_pi(adev);
6776 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6779 if (amdgpu_si_is_smc_running(adev))
6781 if (pi->voltage_control || si_pi->voltage_control_svi2)
6782 si_enable_voltage_control(adev, true);
6783 if (pi->mvdd_control)
6784 si_get_mvdd_configuration(adev);
6785 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6786 ret = si_construct_voltage_tables(adev);
6788 DRM_ERROR("si_construct_voltage_tables failed\n");
6792 if (eg_pi->dynamic_ac_timing) {
6793 ret = si_initialize_mc_reg_table(adev);
6795 eg_pi->dynamic_ac_timing = false;
6798 si_enable_spread_spectrum(adev, true);
6799 if (pi->thermal_protection)
6800 si_enable_thermal_protection(adev, true);
6802 si_program_git(adev);
6803 si_program_tp(adev);
6804 si_program_tpp(adev);
6805 si_program_sstp(adev);
6806 si_enable_display_gap(adev);
6807 si_program_vc(adev);
6808 ret = si_upload_firmware(adev);
6810 DRM_ERROR("si_upload_firmware failed\n");
6813 ret = si_process_firmware_header(adev);
6815 DRM_ERROR("si_process_firmware_header failed\n");
6818 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6820 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6823 ret = si_init_smc_table(adev);
6825 DRM_ERROR("si_init_smc_table failed\n");
6828 ret = si_init_smc_spll_table(adev);
6830 DRM_ERROR("si_init_smc_spll_table failed\n");
6833 ret = si_init_arb_table_index(adev);
6835 DRM_ERROR("si_init_arb_table_index failed\n");
6838 if (eg_pi->dynamic_ac_timing) {
6839 ret = si_populate_mc_reg_table(adev, boot_ps);
6841 DRM_ERROR("si_populate_mc_reg_table failed\n");
6845 ret = si_initialize_smc_cac_tables(adev);
6847 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6850 ret = si_initialize_hardware_cac_manager(adev);
6852 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6855 ret = si_initialize_smc_dte_tables(adev);
6857 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6860 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6862 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6865 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6867 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6870 si_program_response_times(adev);
6871 si_program_ds_registers(adev);
6872 si_dpm_start_smc(adev);
6873 ret = si_notify_smc_display_change(adev, false);
6875 DRM_ERROR("si_notify_smc_display_change failed\n");
6878 si_enable_sclk_control(adev, true);
6881 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6882 si_thermal_start_thermal_controller(adev);
6887 static int si_set_temperature_range(struct amdgpu_device *adev)
6891 ret = si_thermal_enable_alert(adev, false);
6894 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6897 ret = si_thermal_enable_alert(adev, true);
6904 static void si_dpm_disable(struct amdgpu_device *adev)
6906 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6907 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6909 if (!amdgpu_si_is_smc_running(adev))
6911 si_thermal_stop_thermal_controller(adev);
6912 si_disable_ulv(adev);
6914 if (pi->thermal_protection)
6915 si_enable_thermal_protection(adev, false);
6916 si_enable_power_containment(adev, boot_ps, false);
6917 si_enable_smc_cac(adev, boot_ps, false);
6918 si_enable_spread_spectrum(adev, false);
6919 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6921 si_reset_to_default(adev);
6922 si_dpm_stop_smc(adev);
6923 si_force_switch_to_arb_f0(adev);
6925 ni_update_current_ps(adev, boot_ps);
6928 static int si_dpm_pre_set_power_state(void *handle)
6930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6931 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6932 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6933 struct amdgpu_ps *new_ps = &requested_ps;
6935 ni_update_requested_ps(adev, new_ps);
6936 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6941 static int si_power_control_set_level(struct amdgpu_device *adev)
6943 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6946 ret = si_restrict_performance_levels_before_switch(adev);
6949 ret = si_halt_smc(adev);
6952 ret = si_populate_smc_tdp_limits(adev, new_ps);
6955 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6958 ret = si_resume_smc(adev);
6961 ret = si_set_sw_state(adev);
6967 static int si_dpm_set_power_state(void *handle)
6969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6970 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6971 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6972 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6975 ret = si_disable_ulv(adev);
6977 DRM_ERROR("si_disable_ulv failed\n");
6980 ret = si_restrict_performance_levels_before_switch(adev);
6982 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6985 if (eg_pi->pcie_performance_request)
6986 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6987 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6988 ret = si_enable_power_containment(adev, new_ps, false);
6990 DRM_ERROR("si_enable_power_containment failed\n");
6993 ret = si_enable_smc_cac(adev, new_ps, false);
6995 DRM_ERROR("si_enable_smc_cac failed\n");
6998 ret = si_halt_smc(adev);
7000 DRM_ERROR("si_halt_smc failed\n");
7003 ret = si_upload_sw_state(adev, new_ps);
7005 DRM_ERROR("si_upload_sw_state failed\n");
7008 ret = si_upload_smc_data(adev);
7010 DRM_ERROR("si_upload_smc_data failed\n");
7013 ret = si_upload_ulv_state(adev);
7015 DRM_ERROR("si_upload_ulv_state failed\n");
7018 if (eg_pi->dynamic_ac_timing) {
7019 ret = si_upload_mc_reg_table(adev, new_ps);
7021 DRM_ERROR("si_upload_mc_reg_table failed\n");
7025 ret = si_program_memory_timing_parameters(adev, new_ps);
7027 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7030 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7032 ret = si_resume_smc(adev);
7034 DRM_ERROR("si_resume_smc failed\n");
7037 ret = si_set_sw_state(adev);
7039 DRM_ERROR("si_set_sw_state failed\n");
7042 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7043 if (eg_pi->pcie_performance_request)
7044 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7045 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7047 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7050 ret = si_enable_smc_cac(adev, new_ps, true);
7052 DRM_ERROR("si_enable_smc_cac failed\n");
7055 ret = si_enable_power_containment(adev, new_ps, true);
7057 DRM_ERROR("si_enable_power_containment failed\n");
7061 ret = si_power_control_set_level(adev);
7063 DRM_ERROR("si_power_control_set_level failed\n");
7070 static void si_dpm_post_set_power_state(void *handle)
7072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7073 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7074 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7076 ni_update_current_ps(adev, new_ps);
7080 void si_dpm_reset_asic(struct amdgpu_device *adev)
7082 si_restrict_performance_levels_before_switch(adev);
7083 si_disable_ulv(adev);
7084 si_set_boot_state(adev);
7088 static void si_dpm_display_configuration_changed(void *handle)
7090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7092 si_program_display_gap(adev);
7096 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7097 struct amdgpu_ps *rps,
7098 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7101 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7102 rps->class = le16_to_cpu(non_clock_info->usClassification);
7103 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7105 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7106 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7107 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7108 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7109 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7110 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7116 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7117 adev->pm.dpm.boot_ps = rps;
7118 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7119 adev->pm.dpm.uvd_ps = rps;
7122 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7123 struct amdgpu_ps *rps, int index,
7124 union pplib_clock_info *clock_info)
7126 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7127 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7128 struct si_power_info *si_pi = si_get_pi(adev);
7129 struct si_ps *ps = si_get_ps(rps);
7130 u16 leakage_voltage;
7131 struct rv7xx_pl *pl = &ps->performance_levels[index];
7134 ps->performance_level_count = index + 1;
7136 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7137 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7138 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7139 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7141 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7142 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7143 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7144 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7145 si_pi->sys_pcie_mask,
7146 si_pi->boot_pcie_gen,
7147 clock_info->si.ucPCIEGen);
7149 /* patch up vddc if necessary */
7150 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7153 pl->vddc = leakage_voltage;
7155 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7156 pi->acpi_vddc = pl->vddc;
7157 eg_pi->acpi_vddci = pl->vddci;
7158 si_pi->acpi_pcie_gen = pl->pcie_gen;
7161 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7163 /* XXX disable for A0 tahiti */
7164 si_pi->ulv.supported = false;
7165 si_pi->ulv.pl = *pl;
7166 si_pi->ulv.one_pcie_lane_in_ulv = false;
7167 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7168 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7169 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7172 if (pi->min_vddc_in_table > pl->vddc)
7173 pi->min_vddc_in_table = pl->vddc;
7175 if (pi->max_vddc_in_table < pl->vddc)
7176 pi->max_vddc_in_table = pl->vddc;
7178 /* patch up boot state */
7179 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7180 u16 vddc, vddci, mvdd;
7181 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7182 pl->mclk = adev->clock.default_mclk;
7183 pl->sclk = adev->clock.default_sclk;
7186 si_pi->mvdd_bootup_value = mvdd;
7189 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7190 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7191 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7192 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7193 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7194 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7198 union pplib_power_state {
7199 struct _ATOM_PPLIB_STATE v1;
7200 struct _ATOM_PPLIB_STATE_V2 v2;
7203 static int si_parse_power_table(struct amdgpu_device *adev)
7205 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7206 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7207 union pplib_power_state *power_state;
7208 int i, j, k, non_clock_array_index, clock_array_index;
7209 union pplib_clock_info *clock_info;
7210 struct _StateArray *state_array;
7211 struct _ClockInfoArray *clock_info_array;
7212 struct _NonClockInfoArray *non_clock_info_array;
7213 union power_info *power_info;
7214 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7217 u8 *power_state_offset;
7220 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7221 &frev, &crev, &data_offset))
7223 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7225 amdgpu_add_thermal_controller(adev);
7227 state_array = (struct _StateArray *)
7228 (mode_info->atom_context->bios + data_offset +
7229 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7230 clock_info_array = (struct _ClockInfoArray *)
7231 (mode_info->atom_context->bios + data_offset +
7232 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7233 non_clock_info_array = (struct _NonClockInfoArray *)
7234 (mode_info->atom_context->bios + data_offset +
7235 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7237 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
7238 sizeof(struct amdgpu_ps),
7240 if (!adev->pm.dpm.ps)
7242 power_state_offset = (u8 *)state_array->states;
7243 for (i = 0; i < state_array->ucNumEntries; i++) {
7245 power_state = (union pplib_power_state *)power_state_offset;
7246 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7247 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7248 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7249 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7251 kfree(adev->pm.dpm.ps);
7254 adev->pm.dpm.ps[i].ps_priv = ps;
7255 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7257 non_clock_info_array->ucEntrySize);
7259 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7260 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7261 clock_array_index = idx[j];
7262 if (clock_array_index >= clock_info_array->ucNumEntries)
7264 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7266 clock_info = (union pplib_clock_info *)
7267 ((u8 *)&clock_info_array->clockInfo[0] +
7268 (clock_array_index * clock_info_array->ucEntrySize));
7269 si_parse_pplib_clock_info(adev,
7270 &adev->pm.dpm.ps[i], k,
7274 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7276 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7278 /* fill in the vce power states */
7279 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7281 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7282 clock_info = (union pplib_clock_info *)
7283 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7284 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7285 sclk |= clock_info->si.ucEngineClockHigh << 16;
7286 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7287 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7288 adev->pm.dpm.vce_states[i].sclk = sclk;
7289 adev->pm.dpm.vce_states[i].mclk = mclk;
7295 static int si_dpm_init(struct amdgpu_device *adev)
7297 struct rv7xx_power_info *pi;
7298 struct evergreen_power_info *eg_pi;
7299 struct ni_power_info *ni_pi;
7300 struct si_power_info *si_pi;
7301 struct atom_clock_dividers dividers;
7304 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7307 adev->pm.dpm.priv = si_pi;
7312 si_pi->sys_pcie_mask =
7313 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7314 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7315 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7317 si_set_max_cu_value(adev);
7319 rv770_get_max_vddc(adev);
7320 si_get_leakage_vddc(adev);
7321 si_patch_dependency_tables_based_on_leakage(adev);
7324 eg_pi->acpi_vddci = 0;
7325 pi->min_vddc_in_table = 0;
7326 pi->max_vddc_in_table = 0;
7328 ret = amdgpu_get_platform_caps(adev);
7332 ret = amdgpu_parse_extended_power_table(adev);
7336 ret = si_parse_power_table(adev);
7340 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7342 sizeof(struct amdgpu_clock_voltage_dependency_entry),
7344 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7345 amdgpu_free_extended_power_table(adev);
7348 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7349 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7350 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7351 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7352 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7353 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7354 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7355 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7356 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7358 if (adev->pm.dpm.voltage_response_time == 0)
7359 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7360 if (adev->pm.dpm.backbias_response_time == 0)
7361 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7363 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7364 0, false, ÷rs);
7366 pi->ref_div = dividers.ref_div + 1;
7368 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7370 eg_pi->smu_uvd_hs = false;
7372 pi->mclk_strobe_mode_threshold = 40000;
7373 if (si_is_special_1gb_platform(adev))
7374 pi->mclk_stutter_mode_threshold = 0;
7376 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7377 pi->mclk_edc_enable_threshold = 40000;
7378 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7380 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7382 pi->voltage_control =
7383 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7384 VOLTAGE_OBJ_GPIO_LUT);
7385 if (!pi->voltage_control) {
7386 si_pi->voltage_control_svi2 =
7387 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7389 if (si_pi->voltage_control_svi2)
7390 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7391 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7395 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7396 VOLTAGE_OBJ_GPIO_LUT);
7398 eg_pi->vddci_control =
7399 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7400 VOLTAGE_OBJ_GPIO_LUT);
7401 if (!eg_pi->vddci_control)
7402 si_pi->vddci_control_svi2 =
7403 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7406 si_pi->vddc_phase_shed_control =
7407 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7408 VOLTAGE_OBJ_PHASE_LUT);
7410 rv770_get_engine_memory_ss(adev);
7412 pi->asi = RV770_ASI_DFLT;
7413 pi->pasi = CYPRESS_HASI_DFLT;
7414 pi->vrc = SISLANDS_VRC_DFLT;
7416 pi->gfx_clock_gating = true;
7418 eg_pi->sclk_deep_sleep = true;
7419 si_pi->sclk_deep_sleep_above_low = false;
7421 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7422 pi->thermal_protection = true;
7424 pi->thermal_protection = false;
7426 eg_pi->dynamic_ac_timing = true;
7428 eg_pi->light_sleep = true;
7429 #if defined(CONFIG_ACPI)
7430 eg_pi->pcie_performance_request =
7431 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7433 eg_pi->pcie_performance_request = false;
7436 si_pi->sram_end = SMC_RAM_END;
7438 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7439 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7440 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7441 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7442 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7443 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7444 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7446 si_initialize_powertune_defaults(adev);
7448 /* make sure dc limits are valid */
7449 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7450 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7451 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7452 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7454 si_pi->fan_ctrl_is_in_default_mode = true;
7459 static void si_dpm_fini(struct amdgpu_device *adev)
7463 if (adev->pm.dpm.ps)
7464 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7465 kfree(adev->pm.dpm.ps[i].ps_priv);
7466 kfree(adev->pm.dpm.ps);
7467 kfree(adev->pm.dpm.priv);
7468 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7469 amdgpu_free_extended_power_table(adev);
7472 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7475 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7476 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7477 struct amdgpu_ps *rps = &eg_pi->current_rps;
7478 struct si_ps *ps = si_get_ps(rps);
7479 struct rv7xx_pl *pl;
7481 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7482 CURRENT_STATE_INDEX_SHIFT;
7484 if (current_index >= ps->performance_level_count) {
7485 seq_printf(m, "invalid dpm profile %d\n", current_index);
7487 pl = &ps->performance_levels[current_index];
7488 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7489 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7490 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7494 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7495 struct amdgpu_irq_src *source,
7497 enum amdgpu_interrupt_state state)
7502 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7504 case AMDGPU_IRQ_STATE_DISABLE:
7505 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7506 cg_thermal_int |= THERM_INT_MASK_HIGH;
7507 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7509 case AMDGPU_IRQ_STATE_ENABLE:
7510 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7511 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7512 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7519 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7521 case AMDGPU_IRQ_STATE_DISABLE:
7522 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7523 cg_thermal_int |= THERM_INT_MASK_LOW;
7524 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7526 case AMDGPU_IRQ_STATE_ENABLE:
7527 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7528 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7529 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7542 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7543 struct amdgpu_irq_src *source,
7544 struct amdgpu_iv_entry *entry)
7546 bool queue_thermal = false;
7551 switch (entry->src_id) {
7552 case 230: /* thermal low to high */
7553 DRM_DEBUG("IH: thermal low to high\n");
7554 adev->pm.dpm.thermal.high_to_low = false;
7555 queue_thermal = true;
7557 case 231: /* thermal high to low */
7558 DRM_DEBUG("IH: thermal high to low\n");
7559 adev->pm.dpm.thermal.high_to_low = true;
7560 queue_thermal = true;
7567 schedule_work(&adev->pm.dpm.thermal.work);
7572 static int si_dpm_late_init(void *handle)
7575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7577 if (!adev->pm.dpm_enabled)
7580 ret = si_set_temperature_range(adev);
7584 si_dpm_powergate_uvd(adev, true);
7590 * si_dpm_init_microcode - load ucode images from disk
7592 * @adev: amdgpu_device pointer
7594 * Use the firmware interface to load the ucode images into
7595 * the driver (not loaded into hw).
7596 * Returns 0 on success, error on failure.
7598 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7600 const char *chip_name;
7605 switch (adev->asic_type) {
7607 chip_name = "tahiti";
7610 if ((adev->pdev->revision == 0x81) &&
7611 ((adev->pdev->device == 0x6810) ||
7612 (adev->pdev->device == 0x6811)))
7613 chip_name = "pitcairn_k";
7615 chip_name = "pitcairn";
7618 if (((adev->pdev->device == 0x6820) &&
7619 ((adev->pdev->revision == 0x81) ||
7620 (adev->pdev->revision == 0x83))) ||
7621 ((adev->pdev->device == 0x6821) &&
7622 ((adev->pdev->revision == 0x83) ||
7623 (adev->pdev->revision == 0x87))) ||
7624 ((adev->pdev->revision == 0x87) &&
7625 ((adev->pdev->device == 0x6823) ||
7626 (adev->pdev->device == 0x682b))))
7627 chip_name = "verde_k";
7629 chip_name = "verde";
7632 if (((adev->pdev->revision == 0x81) &&
7633 ((adev->pdev->device == 0x6600) ||
7634 (adev->pdev->device == 0x6604) ||
7635 (adev->pdev->device == 0x6605) ||
7636 (adev->pdev->device == 0x6610))) ||
7637 ((adev->pdev->revision == 0x83) &&
7638 (adev->pdev->device == 0x6610)))
7639 chip_name = "oland_k";
7641 chip_name = "oland";
7644 if (((adev->pdev->revision == 0x81) &&
7645 (adev->pdev->device == 0x6660)) ||
7646 ((adev->pdev->revision == 0x83) &&
7647 ((adev->pdev->device == 0x6660) ||
7648 (adev->pdev->device == 0x6663) ||
7649 (adev->pdev->device == 0x6665) ||
7650 (adev->pdev->device == 0x6667))))
7651 chip_name = "hainan_k";
7652 else if ((adev->pdev->revision == 0xc3) &&
7653 (adev->pdev->device == 0x6665))
7654 chip_name = "banks_k_2";
7656 chip_name = "hainan";
7661 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7662 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7665 err = amdgpu_ucode_validate(adev->pm.fw);
7669 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7671 release_firmware(adev->pm.fw);
7678 static int si_dpm_sw_init(void *handle)
7681 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7683 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7687 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7691 /* default to balanced state */
7692 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7693 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7694 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7695 adev->pm.default_sclk = adev->clock.default_sclk;
7696 adev->pm.default_mclk = adev->clock.default_mclk;
7697 adev->pm.current_sclk = adev->clock.default_sclk;
7698 adev->pm.current_mclk = adev->clock.default_mclk;
7699 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7701 if (amdgpu_dpm == 0)
7704 ret = si_dpm_init_microcode(adev);
7708 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7709 mutex_lock(&adev->pm.mutex);
7710 ret = si_dpm_init(adev);
7713 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7714 if (amdgpu_dpm == 1)
7715 amdgpu_pm_print_power_states(adev);
7716 mutex_unlock(&adev->pm.mutex);
7717 DRM_INFO("amdgpu: dpm initialized\n");
7723 mutex_unlock(&adev->pm.mutex);
7724 DRM_ERROR("amdgpu: dpm initialization failed\n");
7728 static int si_dpm_sw_fini(void *handle)
7730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7732 flush_work(&adev->pm.dpm.thermal.work);
7734 mutex_lock(&adev->pm.mutex);
7736 mutex_unlock(&adev->pm.mutex);
7741 static int si_dpm_hw_init(void *handle)
7745 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7750 mutex_lock(&adev->pm.mutex);
7751 si_dpm_setup_asic(adev);
7752 ret = si_dpm_enable(adev);
7754 adev->pm.dpm_enabled = false;
7756 adev->pm.dpm_enabled = true;
7757 mutex_unlock(&adev->pm.mutex);
7758 amdgpu_pm_compute_clocks(adev);
7762 static int si_dpm_hw_fini(void *handle)
7764 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7766 if (adev->pm.dpm_enabled) {
7767 mutex_lock(&adev->pm.mutex);
7768 si_dpm_disable(adev);
7769 mutex_unlock(&adev->pm.mutex);
7775 static int si_dpm_suspend(void *handle)
7777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7779 if (adev->pm.dpm_enabled) {
7780 mutex_lock(&adev->pm.mutex);
7782 si_dpm_disable(adev);
7783 /* reset the power state */
7784 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7785 mutex_unlock(&adev->pm.mutex);
7790 static int si_dpm_resume(void *handle)
7793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7795 if (adev->pm.dpm_enabled) {
7796 /* asic init will reset to the boot state */
7797 mutex_lock(&adev->pm.mutex);
7798 si_dpm_setup_asic(adev);
7799 ret = si_dpm_enable(adev);
7801 adev->pm.dpm_enabled = false;
7803 adev->pm.dpm_enabled = true;
7804 mutex_unlock(&adev->pm.mutex);
7805 if (adev->pm.dpm_enabled)
7806 amdgpu_pm_compute_clocks(adev);
7811 static bool si_dpm_is_idle(void *handle)
7817 static int si_dpm_wait_for_idle(void *handle)
7823 static int si_dpm_soft_reset(void *handle)
7828 static int si_dpm_set_clockgating_state(void *handle,
7829 enum amd_clockgating_state state)
7834 static int si_dpm_set_powergating_state(void *handle,
7835 enum amd_powergating_state state)
7840 /* get temperature in millidegrees */
7841 static int si_dpm_get_temp(void *handle)
7844 int actual_temp = 0;
7845 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7847 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7853 actual_temp = temp & 0x1ff;
7855 actual_temp = (actual_temp * 1000);
7860 static u32 si_dpm_get_sclk(void *handle, bool low)
7862 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7863 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7864 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7867 return requested_state->performance_levels[0].sclk;
7869 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7872 static u32 si_dpm_get_mclk(void *handle, bool low)
7874 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7875 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7876 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7879 return requested_state->performance_levels[0].mclk;
7881 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7884 static void si_dpm_print_power_state(void *handle,
7887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7888 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7889 struct si_ps *ps = si_get_ps(rps);
7890 struct rv7xx_pl *pl;
7893 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7894 amdgpu_dpm_print_cap_info(rps->caps);
7895 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7896 for (i = 0; i < ps->performance_level_count; i++) {
7897 pl = &ps->performance_levels[i];
7898 if (adev->asic_type >= CHIP_TAHITI)
7899 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7900 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7902 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
7903 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7905 amdgpu_dpm_print_ps_status(adev, rps);
7908 static int si_dpm_early_init(void *handle)
7911 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7913 adev->powerplay.pp_funcs = &si_dpm_funcs;
7914 adev->powerplay.pp_handle = adev;
7915 si_dpm_set_irq_funcs(adev);
7919 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7920 const struct rv7xx_pl *si_cpl2)
7922 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7923 (si_cpl1->sclk == si_cpl2->sclk) &&
7924 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7925 (si_cpl1->vddc == si_cpl2->vddc) &&
7926 (si_cpl1->vddci == si_cpl2->vddci));
7929 static int si_check_state_equal(void *handle,
7934 struct si_ps *si_cps;
7935 struct si_ps *si_rps;
7937 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
7938 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
7939 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7941 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7944 si_cps = si_get_ps((struct amdgpu_ps *)cps);
7945 si_rps = si_get_ps((struct amdgpu_ps *)rps);
7947 if (si_cps == NULL) {
7948 printk("si_cps is NULL\n");
7953 if (si_cps->performance_level_count != si_rps->performance_level_count) {
7958 for (i = 0; i < si_cps->performance_level_count; i++) {
7959 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7960 &(si_rps->performance_levels[i]))) {
7966 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7967 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7968 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7973 static int si_dpm_read_sensor(void *handle, int idx,
7974 void *value, int *size)
7976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7977 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7978 struct amdgpu_ps *rps = &eg_pi->current_rps;
7979 struct si_ps *ps = si_get_ps(rps);
7980 uint32_t sclk, mclk;
7982 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7983 CURRENT_STATE_INDEX_SHIFT;
7985 /* size must be at least 4 bytes for all sensors */
7990 case AMDGPU_PP_SENSOR_GFX_SCLK:
7991 if (pl_index < ps->performance_level_count) {
7992 sclk = ps->performance_levels[pl_index].sclk;
7993 *((uint32_t *)value) = sclk;
7998 case AMDGPU_PP_SENSOR_GFX_MCLK:
7999 if (pl_index < ps->performance_level_count) {
8000 mclk = ps->performance_levels[pl_index].mclk;
8001 *((uint32_t *)value) = mclk;
8006 case AMDGPU_PP_SENSOR_GPU_TEMP:
8007 *((uint32_t *)value) = si_dpm_get_temp(adev);
8015 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8017 .early_init = si_dpm_early_init,
8018 .late_init = si_dpm_late_init,
8019 .sw_init = si_dpm_sw_init,
8020 .sw_fini = si_dpm_sw_fini,
8021 .hw_init = si_dpm_hw_init,
8022 .hw_fini = si_dpm_hw_fini,
8023 .suspend = si_dpm_suspend,
8024 .resume = si_dpm_resume,
8025 .is_idle = si_dpm_is_idle,
8026 .wait_for_idle = si_dpm_wait_for_idle,
8027 .soft_reset = si_dpm_soft_reset,
8028 .set_clockgating_state = si_dpm_set_clockgating_state,
8029 .set_powergating_state = si_dpm_set_powergating_state,
8032 const struct amdgpu_ip_block_version si_smu_ip_block =
8034 .type = AMD_IP_BLOCK_TYPE_SMC,
8038 .funcs = &si_dpm_ip_funcs,
8041 static const struct amd_pm_funcs si_dpm_funcs = {
8042 .pre_set_power_state = &si_dpm_pre_set_power_state,
8043 .set_power_state = &si_dpm_set_power_state,
8044 .post_set_power_state = &si_dpm_post_set_power_state,
8045 .display_configuration_changed = &si_dpm_display_configuration_changed,
8046 .get_sclk = &si_dpm_get_sclk,
8047 .get_mclk = &si_dpm_get_mclk,
8048 .print_power_state = &si_dpm_print_power_state,
8049 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8050 .force_performance_level = &si_dpm_force_performance_level,
8051 .vblank_too_short = &si_dpm_vblank_too_short,
8052 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8053 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8054 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8055 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8056 .check_state_equal = &si_check_state_equal,
8057 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8058 .read_sensor = &si_dpm_read_sensor,
8061 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8062 .set = si_dpm_set_interrupt_state,
8063 .process = si_dpm_process_interrupt,
8066 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8068 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8069 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;