drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "gc/gc_10_1_0_offset.h"
  31 #include "gc/gc_10_1_0_sh_mask.h"
  32 #include "hdp/hdp_5_0_0_offset.h"
  33 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  34 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  35
  36 #include "soc15_common.h"
  37 #include "soc15.h"
  38 #include "navi10_sdma_pkt_open.h"
  39 #include "nbio_v2_3.h"
  40 #include "sdma_v5_0.h"
  41
  42 /*(DEBLOBBED)*/
  43
  44 #define SDMA1_REG_OFFSET 0x600
  45 #define SDMA0_HYP_DEC_REG_START 0x5880
  46 #define SDMA0_HYP_DEC_REG_END 0x5893
  47 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  48
  49 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  55         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  56         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  57         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  58         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  59         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  60         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  61         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  62         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  63         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  64         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  65         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  66         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  67         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  79 };
  80
  81 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
  82 };
  83
  84 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  85 {
  86         u32 base;
  87
  88         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  89             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  90                 base = adev->reg_offset[GC_HWIP][0][1];
  91                 if (instance == 1)
  92                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
  93         } else {
  94                 base = adev->reg_offset[GC_HWIP][0][0];
  95                 if (instance == 1)
  96                         internal_offset += SDMA1_REG_OFFSET;
  97         }
  98
  99         return base + internal_offset;
 100 }
 101
 102 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 103 {
 104         switch (adev->asic_type) {
 105         case CHIP_NAVI10:
 106                 soc15_program_register_sequence(adev,
 107                                                 golden_settings_sdma_5,
 108                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 109                 soc15_program_register_sequence(adev,
 110                                                 golden_settings_sdma_nv10,
 111                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 112                 break;
 113         default:
 114                 break;
 115         }
 116 }
 117
 118 /**
 119  * sdma_v5_0_init_microcode - load ucode images from disk
 120  *
 121  * @adev: amdgpu_device pointer
 122  *
 123  * Use the firmware interface to load the ucode images into
 124  * the driver (not loaded into hw).
 125  * Returns 0 on success, error on failure.
 126  */
 127
 128 // emulation only, won't work on real chip
 129 // navi10 real chip need to use PSP to load firmware
 130 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 131 {
 132         const char *chip_name;
 133         char fw_name[30];
 134         int err = 0, i;
 135         struct amdgpu_firmware_info *info = NULL;
 136         const struct common_firmware_header *header = NULL;
 137         const struct sdma_firmware_header_v1_0 *hdr;
 138
 139         DRM_DEBUG("\n");
 140
 141         switch (adev->asic_type) {
 142         case CHIP_NAVI10:
 143                 chip_name = "navi10";
 144                 break;
 145         default:
 146                 BUG();
 147         }
 148
 149         for (i = 0; i < adev->sdma.num_instances; i++) {
 150                 if (i == 0)
 151                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 152                 else
 153                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 154                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 155                 if (err)
 156                         goto out;
 157                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 158                 if (err)
 159                         goto out;
 160                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 161                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 162                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 163                 if (adev->sdma.instance[i].feature_version >= 20)
 164                         adev->sdma.instance[i].burst_nop = true;
 165                 DRM_DEBUG("psp_load == '%s'\n",
 166                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 167
 168                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 169                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 170                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 171                         info->fw = adev->sdma.instance[i].fw;
 172                         header = (const struct common_firmware_header *)info->fw->data;
 173                         adev->firmware.fw_size +=
 174                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 175                 }
 176         }
 177 out:
 178         if (err) {
 179                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 180                 for (i = 0; i < adev->sdma.num_instances; i++) {
 181                         release_firmware(adev->sdma.instance[i].fw);
 182                         adev->sdma.instance[i].fw = NULL;
 183                 }
 184         }
 185         return err;
 186 }
 187
 188 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 189 {
 190         unsigned ret;
 191
 192         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 193         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 194         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 195         amdgpu_ring_write(ring, 1);
 196         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 197         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 198
 199         return ret;
 200 }
 201
 202 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 203                                            unsigned offset)
 204 {
 205         unsigned cur;
 206
 207         BUG_ON(offset > ring->buf_mask);
 208         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 209
 210         cur = (ring->wptr - 1) & ring->buf_mask;
 211         if (cur > offset)
 212                 ring->ring[offset] = cur - offset;
 213         else
 214                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 215 }
 216
 217 /**
 218  * sdma_v5_0_ring_get_rptr - get the current read pointer
 219  *
 220  * @ring: amdgpu ring pointer
 221  *
 222  * Get the current rptr from the hardware (NAVI10+).
 223  */
 224 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 225 {
 226         u64 *rptr;
 227
 228         /* XXX check if swapping is necessary on BE */
 229         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 230
 231         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 232         return ((*rptr) >> 2);
 233 }
 234
 235 /**
 236  * sdma_v5_0_ring_get_wptr - get the current write pointer
 237  *
 238  * @ring: amdgpu ring pointer
 239  *
 240  * Get the current wptr from the hardware (NAVI10+).
 241  */
 242 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 243 {
 244         struct amdgpu_device *adev = ring->adev;
 245         u64 *wptr = NULL;
 246         uint64_t local_wptr = 0;
 247
 248         if (ring->use_doorbell) {
 249                 /* XXX check if swapping is necessary on BE */
 250                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 251                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 252                 *wptr = (*wptr) >> 2;
 253                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 254         } else {
 255                 u32 lowbit, highbit;
 256
 257                 wptr = &local_wptr;
 258                 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 259                 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 260
 261                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 262                                 ring->me, highbit, lowbit);
 263                 *wptr = highbit;
 264                 *wptr = (*wptr) << 32;
 265                 *wptr |= lowbit;
 266         }
 267
 268         return *wptr;
 269 }
 270
 271 /**
 272  * sdma_v5_0_ring_set_wptr - commit the write pointer
 273  *
 274  * @ring: amdgpu ring pointer
 275  *
 276  * Write the wptr back to the hardware (NAVI10+).
 277  */
 278 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 279 {
 280         struct amdgpu_device *adev = ring->adev;
 281
 282         DRM_DEBUG("Setting write pointer\n");
 283         if (ring->use_doorbell) {
 284                 DRM_DEBUG("Using doorbell -- "
 285                                 "wptr_offs == 0x%08x "
 286                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 287                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 288                                 ring->wptr_offs,
 289                                 lower_32_bits(ring->wptr << 2),
 290                                 upper_32_bits(ring->wptr << 2));
 291                 /* XXX check if swapping is necessary on BE */
 292                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 293                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 294                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 295                                 ring->doorbell_index, ring->wptr << 2);
 296                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 297         } else {
 298                 DRM_DEBUG("Not using doorbell -- "
 299                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 300                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 301                                 ring->me,
 302                                 lower_32_bits(ring->wptr << 2),
 303                                 ring->me,
 304                                 upper_32_bits(ring->wptr << 2));
 305                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 306                         lower_32_bits(ring->wptr << 2));
 307                 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 308                         upper_32_bits(ring->wptr << 2));
 309         }
 310 }
 311
 312 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 313 {
 314         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 315         int i;
 316
 317         for (i = 0; i < count; i++)
 318                 if (sdma && sdma->burst_nop && (i == 0))
 319                         amdgpu_ring_write(ring, ring->funcs->nop |
 320                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 321                 else
 322                         amdgpu_ring_write(ring, ring->funcs->nop);
 323 }
 324
 325 /**
 326  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 327  *
 328  * @ring: amdgpu ring pointer
 329  * @ib: IB object to schedule
 330  *
 331  * Schedule an IB in the DMA ring (NAVI10).
 332  */
 333 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 334                                    struct amdgpu_job *job,
 335                                    struct amdgpu_ib *ib,
 336                                    uint32_t flags)
 337 {
 338         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 339         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 340
 341         /* IB packet must end on a 8 DW boundary */
 342         sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 343
 344         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 345                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 346         /* base must be 32 byte aligned */
 347         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 348         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 349         amdgpu_ring_write(ring, ib->length_dw);
 350         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 351         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 352 }
 353
 354 /**
 355  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 356  *
 357  * @ring: amdgpu ring pointer
 358  *
 359  * Emit an hdp flush packet on the requested DMA ring.
 360  */
 361 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 362 {
 363         struct amdgpu_device *adev = ring->adev;
 364         u32 ref_and_mask = 0;
 365         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 366
 367         if (ring->me == 0)
 368                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 369         else
 370                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 371
 372         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 373                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 374                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 375         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
 376         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
 377         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 378         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 379         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 380                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 381 }
 382
 383 /**
 384  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 385  *
 386  * @ring: amdgpu ring pointer
 387  * @fence: amdgpu fence object
 388  *
 389  * Add a DMA fence packet to the ring to write
 390  * the fence seq number and DMA trap packet to generate
 391  * an interrupt if needed (NAVI10).
 392  */
 393 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 394                                       unsigned flags)
 395 {
 396         struct amdgpu_device *adev = ring->adev;
 397         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 398         /* write the fence */
 399         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 400                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 401         /* zero in first two bits */
 402         BUG_ON(addr & 0x3);
 403         amdgpu_ring_write(ring, lower_32_bits(addr));
 404         amdgpu_ring_write(ring, upper_32_bits(addr));
 405         amdgpu_ring_write(ring, lower_32_bits(seq));
 406
 407         /* optionally write high bits as well */
 408         if (write64bit) {
 409                 addr += 4;
 410                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 411                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 412                 /* zero in first two bits */
 413                 BUG_ON(addr & 0x3);
 414                 amdgpu_ring_write(ring, lower_32_bits(addr));
 415                 amdgpu_ring_write(ring, upper_32_bits(addr));
 416                 amdgpu_ring_write(ring, upper_32_bits(seq));
 417         }
 418
 419         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
 420         if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) {
 421                 /* generate an interrupt */
 422                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 423                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 424         }
 425 }
 426
 427
 428 /**
 429  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 430  *
 431  * @adev: amdgpu_device pointer
 432  *
 433  * Stop the gfx async dma ring buffers (NAVI10).
 434  */
 435 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 436 {
 437         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 438         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 439         u32 rb_cntl, ib_cntl;
 440         int i;
 441
 442         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 443             (adev->mman.buffer_funcs_ring == sdma1))
 444                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 445
 446         for (i = 0; i < adev->sdma.num_instances; i++) {
 447                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 448                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 449                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 450                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 451                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 452                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 453         }
 454
 455         sdma0->sched.ready = false;
 456         sdma1->sched.ready = false;
 457 }
 458
 459 /**
 460  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 461  *
 462  * @adev: amdgpu_device pointer
 463  *
 464  * Stop the compute async dma queues (NAVI10).
 465  */
 466 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 467 {
 468         /* XXX todo */
 469 }
 470
 471 /**
 472  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 473  *
 474  * @adev: amdgpu_device pointer
 475  * @enable: enable/disable the DMA MEs context switch.
 476  *
 477  * Halt or unhalt the async dma engines context switch (NAVI10).
 478  */
 479 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 480 {
 481         u32 f32_cntl, phase_quantum = 0;
 482         int i;
 483
 484         if (amdgpu_sdma_phase_quantum) {
 485                 unsigned value = amdgpu_sdma_phase_quantum;
 486                 unsigned unit = 0;
 487
 488                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 489                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 490                         value = (value + 1) >> 1;
 491                         unit++;
 492                 }
 493                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 494                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 495                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 496                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 497                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 498                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 499                         WARN_ONCE(1,
 500                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 501                                   value << unit);
 502                 }
 503                 phase_quantum =
 504                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 505                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 506         }
 507
 508         for (i = 0; i < adev->sdma.num_instances; i++) {
 509                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 510                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 511                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 512                 if (enable && amdgpu_sdma_phase_quantum) {
 513                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 514                                phase_quantum);
 515                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 516                                phase_quantum);
 517                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 518                                phase_quantum);
 519                 }
 520                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 521         }
 522
 523 }
 524
 525 /**
 526  * sdma_v5_0_enable - stop the async dma engines
 527  *
 528  * @adev: amdgpu_device pointer
 529  * @enable: enable/disable the DMA MEs.
 530  *
 531  * Halt or unhalt the async dma engines (NAVI10).
 532  */
 533 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 534 {
 535         u32 f32_cntl;
 536         int i;
 537
 538         if (enable == false) {
 539                 sdma_v5_0_gfx_stop(adev);
 540                 sdma_v5_0_rlc_stop(adev);
 541         }
 542
 543         for (i = 0; i < adev->sdma.num_instances; i++) {
 544                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 545                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 546                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 547         }
 548 }
 549
 550 /**
 551  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 552  *
 553  * @adev: amdgpu_device pointer
 554  *
 555  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 556  * Returns 0 for success, error for failure.
 557  */
 558 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 559 {
 560         struct amdgpu_ring *ring;
 561         u32 rb_cntl, ib_cntl;
 562         u32 rb_bufsz;
 563         u32 wb_offset;
 564         u32 doorbell;
 565         u32 doorbell_offset;
 566         u32 temp;
 567         u32 wptr_poll_cntl;
 568         u64 wptr_gpu_addr;
 569         int i, r;
 570
 571         for (i = 0; i < adev->sdma.num_instances; i++) {
 572                 ring = &adev->sdma.instance[i].ring;
 573                 wb_offset = (ring->rptr_offs * 4);
 574
 575                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 576
 577                 /* Set ring buffer size in dwords */
 578                 rb_bufsz = order_base_2(ring->ring_size / 4);
 579                 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 580                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 581 #ifdef __BIG_ENDIAN
 582                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 583                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 584                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 585 #endif
 586                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 587
 588                 /* Initialize the ring buffer's read and write pointers */
 589                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 590                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 591                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 592                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 593
 594                 /* setup the wptr shadow polling */
 595                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 596                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 597                        lower_32_bits(wptr_gpu_addr));
 598                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 599                        upper_32_bits(wptr_gpu_addr));
 600                 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
 601                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 602                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 603                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 604                                                F32_POLL_ENABLE, 1);
 605                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 606                        wptr_poll_cntl);
 607
 608                 /* set the wb address whether it's enabled or not */
 609                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 610                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 611                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 612                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 613
 614                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 615
 616                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 617                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 618
 619                 ring->wptr = 0;
 620
 621                 /* before programing wptr to a less value, need set minor_ptr_update first */
 622                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 623
 624                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 625                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 626                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 627                 }
 628
 629                 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 630                 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 631
 632                 if (ring->use_doorbell) {
 633                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 634                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 635                                         OFFSET, ring->doorbell_index);
 636                 } else {
 637                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 638                 }
 639                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 640                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 641
 642                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 643                                                       ring->doorbell_index, 20);
 644
 645                 if (amdgpu_sriov_vf(adev))
 646                         sdma_v5_0_ring_set_wptr(ring);
 647
 648                 /* set minor_ptr_update to 0 after wptr programed */
 649                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 650
 651                 /* set utc l1 enable flag always to 1 */
 652                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 653                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 654
 655                 /* enable MCBP */
 656                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 657                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 658
 659                 /* Set up RESP_MODE to non-copy addresses */
 660                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 661                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 662                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 663                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 664
 665                 /* program default cache read and write policy */
 666                 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 667                 /* clean read policy and write policy bits */
 668                 temp &= 0xFF0FFF;
 669                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 670                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 671
 672                 if (!amdgpu_sriov_vf(adev)) {
 673                         /* unhalt engine */
 674                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 675                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 676                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 677                 }
 678
 679                 /* enable DMA RB */
 680                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 681                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 682
 683                 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 684                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 685 #ifdef __BIG_ENDIAN
 686                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 687 #endif
 688                 /* enable DMA IBs */
 689                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 690
 691                 ring->sched.ready = true;
 692
 693                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 694                         sdma_v5_0_ctx_switch_enable(adev, true);
 695                         sdma_v5_0_enable(adev, true);
 696                 }
 697
 698                 r = amdgpu_ring_test_ring(ring);
 699                 if (r) {
 700                         ring->sched.ready = false;
 701                         return r;
 702                 }
 703
 704                 if (adev->mman.buffer_funcs_ring == ring)
 705                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 706         }
 707
 708         return 0;
 709 }
 710
 711 /**
 712  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 713  *
 714  * @adev: amdgpu_device pointer
 715  *
 716  * Set up the compute DMA queues and enable them (NAVI10).
 717  * Returns 0 for success, error for failure.
 718  */
 719 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 720 {
 721         return 0;
 722 }
 723
 724 /**
 725  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 726  *
 727  * @adev: amdgpu_device pointer
 728  *
 729  * Loads the sDMA0/1 ucode.
 730  * Returns 0 for success, -EINVAL if the ucode is not available.
 731  */
 732 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 733 {
 734         const struct sdma_firmware_header_v1_0 *hdr;
 735         const __le32 *fw_data;
 736         u32 fw_size;
 737         int i, j;
 738
 739         /* halt the MEs */
 740         sdma_v5_0_enable(adev, false);
 741
 742         for (i = 0; i < adev->sdma.num_instances; i++) {
 743                 if (!adev->sdma.instance[i].fw)
 744                         return -EINVAL;
 745
 746                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 747                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 748                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 749
 750                 fw_data = (const __le32 *)
 751                         (adev->sdma.instance[i].fw->data +
 752                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 753
 754                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 755
 756                 for (j = 0; j < fw_size; j++) {
 757                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 758                                 msleep(1);
 759                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 760                 }
 761
 762                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 763         }
 764
 765         return 0;
 766 }
 767
 768 /**
 769  * sdma_v5_0_start - setup and start the async dma engines
 770  *
 771  * @adev: amdgpu_device pointer
 772  *
 773  * Set up the DMA engines and enable them (NAVI10).
 774  * Returns 0 for success, error for failure.
 775  */
 776 static int sdma_v5_0_start(struct amdgpu_device *adev)
 777 {
 778         int r = 0;
 779
 780         if (amdgpu_sriov_vf(adev)) {
 781                 sdma_v5_0_ctx_switch_enable(adev, false);
 782                 sdma_v5_0_enable(adev, false);
 783
 784                 /* set RB registers */
 785                 r = sdma_v5_0_gfx_resume(adev);
 786                 return r;
 787         }
 788
 789         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 790                 r = sdma_v5_0_load_microcode(adev);
 791                 if (r)
 792                         return r;
 793
 794                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 795                 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d)
 796                         msleep(1000);
 797         }
 798
 799         /* unhalt the MEs */
 800         sdma_v5_0_enable(adev, true);
 801         /* enable sdma ring preemption */
 802         sdma_v5_0_ctx_switch_enable(adev, true);
 803
 804         /* start the gfx rings and rlc compute queues */
 805         r = sdma_v5_0_gfx_resume(adev);
 806         if (r)
 807                 return r;
 808         r = sdma_v5_0_rlc_resume(adev);
 809
 810         return r;
 811 }
 812
 813 /**
 814  * sdma_v5_0_ring_test_ring - simple async dma engine test
 815  *
 816  * @ring: amdgpu_ring structure holding ring information
 817  *
 818  * Test the DMA engine by writing using it to write an
 819  * value to memory. (NAVI10).
 820  * Returns 0 for success, error for failure.
 821  */
 822 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 823 {
 824         struct amdgpu_device *adev = ring->adev;
 825         unsigned i;
 826         unsigned index;
 827         int r;
 828         u32 tmp;
 829         u64 gpu_addr;
 830
 831         r = amdgpu_device_wb_get(adev, &index);
 832         if (r) {
 833                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 834                 return r;
 835         }
 836
 837         gpu_addr = adev->wb.gpu_addr + (index * 4);
 838         tmp = 0xCAFEDEAD;
 839         adev->wb.wb[index] = cpu_to_le32(tmp);
 840
 841         r = amdgpu_ring_alloc(ring, 5);
 842         if (r) {
 843                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 844                 amdgpu_device_wb_free(adev, index);
 845                 return r;
 846         }
 847
 848         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 849                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 850         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 851         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 852         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 853         amdgpu_ring_write(ring, 0xDEADBEEF);
 854         amdgpu_ring_commit(ring);
 855
 856         for (i = 0; i < adev->usec_timeout; i++) {
 857                 tmp = le32_to_cpu(adev->wb.wb[index]);
 858                 if (tmp == 0xDEADBEEF)
 859                         break;
 860                 if (amdgpu_emu_mode == 1)
 861                         msleep(1);
 862                 else
 863                         DRM_UDELAY(1);
 864         }
 865
 866         if (i < adev->usec_timeout) {
 867                 if (amdgpu_emu_mode == 1)
 868                         DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i);
 869                 else
 870                         DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 871         } else {
 872                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 873                           ring->idx, tmp);
 874                 r = -EINVAL;
 875         }
 876         amdgpu_device_wb_free(adev, index);
 877
 878         return r;
 879 }
 880
 881 /**
 882  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
 883  *
 884  * @ring: amdgpu_ring structure holding ring information
 885  *
 886  * Test a simple IB in the DMA ring (NAVI10).
 887  * Returns 0 on success, error on failure.
 888  */
 889 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 890 {
 891         struct amdgpu_device *adev = ring->adev;
 892         struct amdgpu_ib ib;
 893         struct dma_fence *f = NULL;
 894         unsigned index;
 895         long r;
 896         u32 tmp = 0;
 897         u64 gpu_addr;
 898
 899         r = amdgpu_device_wb_get(adev, &index);
 900         if (r) {
 901                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 902                 return r;
 903         }
 904
 905         gpu_addr = adev->wb.gpu_addr + (index * 4);
 906         tmp = 0xCAFEDEAD;
 907         adev->wb.wb[index] = cpu_to_le32(tmp);
 908         memset(&ib, 0, sizeof(ib));
 909         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 910         if (r) {
 911                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 912                 goto err0;
 913         }
 914
 915         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 916                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 917         ib.ptr[1] = lower_32_bits(gpu_addr);
 918         ib.ptr[2] = upper_32_bits(gpu_addr);
 919         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 920         ib.ptr[4] = 0xDEADBEEF;
 921         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 922         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 923         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 924         ib.length_dw = 8;
 925
 926         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 927         if (r)
 928                 goto err1;
 929
 930         r = dma_fence_wait_timeout(f, false, timeout);
 931         if (r == 0) {
 932                 DRM_ERROR("amdgpu: IB test timed out\n");
 933                 r = -ETIMEDOUT;
 934                 goto err1;
 935         } else if (r < 0) {
 936                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 937                 goto err1;
 938         }
 939         tmp = le32_to_cpu(adev->wb.wb[index]);
 940         if (tmp == 0xDEADBEEF) {
 941                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 942                 r = 0;
 943         } else {
 944                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 945                 r = -EINVAL;
 946         }
 947
 948 err1:
 949         amdgpu_ib_free(adev, &ib, NULL);
 950         dma_fence_put(f);
 951 err0:
 952         amdgpu_device_wb_free(adev, index);
 953         return r;
 954 }
 955
 956
 957 /**
 958  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
 959  *
 960  * @ib: indirect buffer to fill with commands
 961  * @pe: addr of the page entry
 962  * @src: src addr to copy from
 963  * @count: number of page entries to update
 964  *
 965  * Update PTEs by copying them from the GART using sDMA (NAVI10).
 966  */
 967 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
 968                                   uint64_t pe, uint64_t src,
 969                                   unsigned count)
 970 {
 971         unsigned bytes = count * 8;
 972
 973         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 974                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 975         ib->ptr[ib->length_dw++] = bytes - 1;
 976         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 977         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 978         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 979         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 980         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 981
 982 }
 983
 984 /**
 985  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
 986  *
 987  * @ib: indirect buffer to fill with commands
 988  * @pe: addr of the page entry
 989  * @addr: dst addr to write into pe
 990  * @count: number of page entries to update
 991  * @incr: increase next addr by incr bytes
 992  * @flags: access flags
 993  *
 994  * Update PTEs by writing them manually using sDMA (NAVI10).
 995  */
 996 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 997                                    uint64_t value, unsigned count,
 998                                    uint32_t incr)
 999 {
1000         unsigned ndw = count * 2;
1001
1002         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1003                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1004         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1005         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1006         ib->ptr[ib->length_dw++] = ndw - 1;
1007         for (; ndw > 0; ndw -= 2) {
1008                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1009                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1010                 value += incr;
1011         }
1012 }
1013
1014 /**
1015  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1016  *
1017  * @ib: indirect buffer to fill with commands
1018  * @pe: addr of the page entry
1019  * @addr: dst addr to write into pe
1020  * @count: number of page entries to update
1021  * @incr: increase next addr by incr bytes
1022  * @flags: access flags
1023  *
1024  * Update the page tables using sDMA (NAVI10).
1025  */
1026 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1027                                      uint64_t pe,
1028                                      uint64_t addr, unsigned count,
1029                                      uint32_t incr, uint64_t flags)
1030 {
1031         /* for physically contiguous pages (vram) */
1032         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1033         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1034         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1035         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1036         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1037         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1038         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1039         ib->ptr[ib->length_dw++] = incr; /* increment size */
1040         ib->ptr[ib->length_dw++] = 0;
1041         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1042 }
1043
1044 /**
1045  * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw
1046  *
1047  * @ib: indirect buffer to fill with padding
1048  *
1049  */
1050 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1051 {
1052         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1053         u32 pad_count;
1054         int i;
1055
1056         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1057         for (i = 0; i < pad_count; i++)
1058                 if (sdma && sdma->burst_nop && (i == 0))
1059                         ib->ptr[ib->length_dw++] =
1060                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1061                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1062                 else
1063                         ib->ptr[ib->length_dw++] =
1064                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1065 }
1066
1067
1068 /**
1069  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1070  *
1071  * @ring: amdgpu_ring pointer
1072  *
1073  * Make sure all previous operations are completed (CIK).
1074  */
1075 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1076 {
1077         uint32_t seq = ring->fence_drv.sync_seq;
1078         uint64_t addr = ring->fence_drv.gpu_addr;
1079
1080         /* wait for idle */
1081         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1082                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1083                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1084                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1085         amdgpu_ring_write(ring, addr & 0xfffffffc);
1086         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1087         amdgpu_ring_write(ring, seq); /* reference */
1088         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1089         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1090                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1091 }
1092
1093
1094 /**
1095  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1096  *
1097  * @ring: amdgpu_ring pointer
1098  * @vm: amdgpu_vm pointer
1099  *
1100  * Update the page table base and flush the VM TLB
1101  * using sDMA (NAVI10).
1102  */
1103 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1104                                          unsigned vmid, uint64_t pd_addr)
1105 {
1106         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1107 }
1108
1109 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1110                                      uint32_t reg, uint32_t val)
1111 {
1112         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1113                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1114         amdgpu_ring_write(ring, reg);
1115         amdgpu_ring_write(ring, val);
1116 }
1117
1118 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1119                                          uint32_t val, uint32_t mask)
1120 {
1121         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1122                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1123                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1124         amdgpu_ring_write(ring, reg << 2);
1125         amdgpu_ring_write(ring, 0);
1126         amdgpu_ring_write(ring, val); /* reference */
1127         amdgpu_ring_write(ring, mask); /* mask */
1128         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1129                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1130 }
1131
1132 static int sdma_v5_0_early_init(void *handle)
1133 {
1134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1135
1136         adev->sdma.num_instances = 2;
1137
1138         sdma_v5_0_set_ring_funcs(adev);
1139         sdma_v5_0_set_buffer_funcs(adev);
1140         sdma_v5_0_set_vm_pte_funcs(adev);
1141         sdma_v5_0_set_irq_funcs(adev);
1142
1143         return 0;
1144 }
1145
1146
1147 static int sdma_v5_0_sw_init(void *handle)
1148 {
1149         struct amdgpu_ring *ring;
1150         int r, i;
1151         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1152
1153         /* SDMA trap event */
1154         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1155                               SDMA0_5_0__SRCID__SDMA_TRAP,
1156                               &adev->sdma.trap_irq);
1157         if (r)
1158                 return r;
1159
1160         /* SDMA trap event */
1161         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1162                               SDMA1_5_0__SRCID__SDMA_TRAP,
1163                               &adev->sdma.trap_irq);
1164         if (r)
1165                 return r;
1166
1167         r = sdma_v5_0_init_microcode(adev);
1168         if (r) {
1169                 DRM_ERROR("Failed to load sdma firmware!\n");
1170                 return r;
1171         }
1172
1173         for (i = 0; i < adev->sdma.num_instances; i++) {
1174                 ring = &adev->sdma.instance[i].ring;
1175                 ring->ring_obj = NULL;
1176                 ring->use_doorbell = true;
1177
1178                 DRM_INFO("use_doorbell being set to: [%s]\n",
1179                                 ring->use_doorbell?"true":"false");
1180
1181                 ring->doorbell_index = (i == 0) ?
1182                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1183                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1184
1185                 sprintf(ring->name, "sdma%d", i);
1186                 r = amdgpu_ring_init(adev, ring, 1024,
1187                                      &adev->sdma.trap_irq,
1188                                      (i == 0) ?
1189                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1190                                      AMDGPU_SDMA_IRQ_INSTANCE1);
1191                 if (r)
1192                         return r;
1193         }
1194
1195         return r;
1196 }
1197
1198 static int sdma_v5_0_sw_fini(void *handle)
1199 {
1200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1201         int i;
1202
1203         for (i = 0; i < adev->sdma.num_instances; i++)
1204                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1205
1206         return 0;
1207 }
1208
1209 static int sdma_v5_0_hw_init(void *handle)
1210 {
1211         int r;
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213
1214         sdma_v5_0_init_golden_registers(adev);
1215
1216         r = sdma_v5_0_start(adev);
1217
1218         return r;
1219 }
1220
1221 static int sdma_v5_0_hw_fini(void *handle)
1222 {
1223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224
1225         if (amdgpu_sriov_vf(adev))
1226                 return 0;
1227
1228         sdma_v5_0_ctx_switch_enable(adev, false);
1229         sdma_v5_0_enable(adev, false);
1230
1231         return 0;
1232 }
1233
1234 static int sdma_v5_0_suspend(void *handle)
1235 {
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237
1238         return sdma_v5_0_hw_fini(adev);
1239 }
1240
1241 static int sdma_v5_0_resume(void *handle)
1242 {
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245         return sdma_v5_0_hw_init(adev);
1246 }
1247
1248 static bool sdma_v5_0_is_idle(void *handle)
1249 {
1250         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1251         u32 i;
1252
1253         for (i = 0; i < adev->sdma.num_instances; i++) {
1254                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1255
1256                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1257                         return false;
1258         }
1259
1260         return true;
1261 }
1262
1263 static int sdma_v5_0_wait_for_idle(void *handle)
1264 {
1265         unsigned i;
1266         u32 sdma0, sdma1;
1267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268
1269         for (i = 0; i < adev->usec_timeout; i++) {
1270                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1271                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1272
1273                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1274                         return 0;
1275                 udelay(1);
1276         }
1277         return -ETIMEDOUT;
1278 }
1279
1280 static int sdma_v5_0_soft_reset(void *handle)
1281 {
1282         /* todo */
1283
1284         return 0;
1285 }
1286
1287 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1288 {
1289         int i, r = 0;
1290         struct amdgpu_device *adev = ring->adev;
1291         u32 index = 0;
1292         u64 sdma_gfx_preempt;
1293
1294         amdgpu_sdma_get_index_from_ring(ring, &index);
1295         if (index == 0)
1296                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1297         else
1298                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1299
1300         /* assert preemption condition */
1301         amdgpu_ring_set_preempt_cond_exec(ring, false);
1302
1303         /* emit the trailing fence */
1304         ring->trail_seq += 1;
1305         amdgpu_ring_alloc(ring, 10);
1306         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1307                                   ring->trail_seq, 0);
1308         amdgpu_ring_commit(ring);
1309
1310         /* assert IB preemption */
1311         WREG32(sdma_gfx_preempt, 1);
1312
1313         /* poll the trailing fence */
1314         for (i = 0; i < adev->usec_timeout; i++) {
1315                 if (ring->trail_seq ==
1316                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1317                         break;
1318                 DRM_UDELAY(1);
1319         }
1320
1321         if (i >= adev->usec_timeout) {
1322                 r = -EINVAL;
1323                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1324         }
1325
1326         /* deassert IB preemption */
1327         WREG32(sdma_gfx_preempt, 0);
1328
1329         /* deassert the preemption condition */
1330         amdgpu_ring_set_preempt_cond_exec(ring, true);
1331         return r;
1332 }
1333
1334 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1335                                         struct amdgpu_irq_src *source,
1336                                         unsigned type,
1337                                         enum amdgpu_interrupt_state state)
1338 {
1339         u32 sdma_cntl;
1340
1341         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1342                 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1343                 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1344
1345         sdma_cntl = RREG32(reg_offset);
1346         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1347                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1348         WREG32(reg_offset, sdma_cntl);
1349
1350         return 0;
1351 }
1352
1353 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1354                                       struct amdgpu_irq_src *source,
1355                                       struct amdgpu_iv_entry *entry)
1356 {
1357         DRM_DEBUG("IH: SDMA trap\n");
1358         switch (entry->client_id) {
1359         case SOC15_IH_CLIENTID_SDMA0:
1360                 switch (entry->ring_id) {
1361                 case 0:
1362                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1363                         break;
1364                 case 1:
1365                         /* XXX compute */
1366                         break;
1367                 case 2:
1368                         /* XXX compute */
1369                         break;
1370                 case 3:
1371                         /* XXX page queue*/
1372                         break;
1373                 }
1374                 break;
1375         case SOC15_IH_CLIENTID_SDMA1:
1376                 switch (entry->ring_id) {
1377                 case 0:
1378                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1379                         break;
1380                 case 1:
1381                         /* XXX compute */
1382                         break;
1383                 case 2:
1384                         /* XXX compute */
1385                         break;
1386                 case 3:
1387                         /* XXX page queue*/
1388                         break;
1389                 }
1390                 break;
1391         }
1392         return 0;
1393 }
1394
1395 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1396                                               struct amdgpu_irq_src *source,
1397                                               struct amdgpu_iv_entry *entry)
1398 {
1399         return 0;
1400 }
1401
1402 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1403                                                        bool enable)
1404 {
1405         uint32_t data, def;
1406         int i;
1407
1408         for (i = 0; i < adev->sdma.num_instances; i++) {
1409                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1410                         /* Enable sdma clock gating */
1411                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1412                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1413                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1414                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1415                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1416                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1417                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1418                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1419                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1420                         if (def != data)
1421                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1422                 } else {
1423                         /* Disable sdma clock gating */
1424                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1425                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1426                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1427                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1428                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1429                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1430                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1431                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1432                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1433                         if (def != data)
1434                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1435                 }
1436         }
1437 }
1438
1439 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1440                                                       bool enable)
1441 {
1442         uint32_t data, def;
1443         int i;
1444
1445         for (i = 0; i < adev->sdma.num_instances; i++) {
1446                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1447                         /* Enable sdma mem light sleep */
1448                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1449                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1450                         if (def != data)
1451                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1452
1453                 } else {
1454                         /* Disable sdma mem light sleep */
1455                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1456                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1457                         if (def != data)
1458                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1459
1460                 }
1461         }
1462 }
1463
1464 static int sdma_v5_0_set_clockgating_state(void *handle,
1465                                            enum amd_clockgating_state state)
1466 {
1467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468
1469         if (amdgpu_sriov_vf(adev))
1470                 return 0;
1471
1472         switch (adev->asic_type) {
1473         case CHIP_NAVI10:
1474                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1475                                 state == AMD_CG_STATE_GATE ? true : false);
1476                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1477                                 state == AMD_CG_STATE_GATE ? true : false);
1478                 break;
1479         default:
1480                 break;
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int sdma_v5_0_set_powergating_state(void *handle,
1487                                           enum amd_powergating_state state)
1488 {
1489         return 0;
1490 }
1491
1492 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1493 {
1494         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1495         int data;
1496
1497         if (amdgpu_sriov_vf(adev))
1498                 *flags = 0;
1499
1500         /* AMD_CG_SUPPORT_SDMA_MGCG */
1501         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1502         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1503                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1504
1505         /* AMD_CG_SUPPORT_SDMA_LS */
1506         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1507         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1508                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1509 }
1510
1511 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1512         .name = "sdma_v5_0",
1513         .early_init = sdma_v5_0_early_init,
1514         .late_init = NULL,
1515         .sw_init = sdma_v5_0_sw_init,
1516         .sw_fini = sdma_v5_0_sw_fini,
1517         .hw_init = sdma_v5_0_hw_init,
1518         .hw_fini = sdma_v5_0_hw_fini,
1519         .suspend = sdma_v5_0_suspend,
1520         .resume = sdma_v5_0_resume,
1521         .is_idle = sdma_v5_0_is_idle,
1522         .wait_for_idle = sdma_v5_0_wait_for_idle,
1523         .soft_reset = sdma_v5_0_soft_reset,
1524         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1525         .set_powergating_state = sdma_v5_0_set_powergating_state,
1526         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1527 };
1528
1529 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1530         .type = AMDGPU_RING_TYPE_SDMA,
1531         .align_mask = 0xf,
1532         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1533         .support_64bit_ptrs = true,
1534         .vmhub = AMDGPU_GFXHUB,
1535         .get_rptr = sdma_v5_0_ring_get_rptr,
1536         .get_wptr = sdma_v5_0_ring_get_wptr,
1537         .set_wptr = sdma_v5_0_ring_set_wptr,
1538         .emit_frame_size =
1539                 5 + /* sdma_v5_0_ring_init_cond_exec */
1540                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1541                 3 + /* hdp_invalidate */
1542                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1543                 /* sdma_v5_0_ring_emit_vm_flush */
1544                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1545                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1546                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1547         .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */
1548         .emit_ib = sdma_v5_0_ring_emit_ib,
1549         .emit_fence = sdma_v5_0_ring_emit_fence,
1550         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1551         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1552         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1553         .test_ring = sdma_v5_0_ring_test_ring,
1554         .test_ib = sdma_v5_0_ring_test_ib,
1555         .insert_nop = sdma_v5_0_ring_insert_nop,
1556         .pad_ib = sdma_v5_0_ring_pad_ib,
1557         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1558         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1559         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1560         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1561         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1562 };
1563
1564 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1565 {
1566         int i;
1567
1568         for (i = 0; i < adev->sdma.num_instances; i++) {
1569                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1570                 adev->sdma.instance[i].ring.me = i;
1571         }
1572 }
1573
1574 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1575         .set = sdma_v5_0_set_trap_irq_state,
1576         .process = sdma_v5_0_process_trap_irq,
1577 };
1578
1579 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1580         .process = sdma_v5_0_process_illegal_inst_irq,
1581 };
1582
1583 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1584 {
1585         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1586                                         adev->sdma.num_instances;
1587         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1588         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1589 }
1590
1591 /**
1592  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1593  *
1594  * @ring: amdgpu_ring structure holding ring information
1595  * @src_offset: src GPU address
1596  * @dst_offset: dst GPU address
1597  * @byte_count: number of bytes to xfer
1598  *
1599  * Copy GPU buffers using the DMA engine (NAVI10).
1600  * Used by the amdgpu ttm implementation to move pages if
1601  * registered as the asic copy callback.
1602  */
1603 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1604                                        uint64_t src_offset,
1605                                        uint64_t dst_offset,
1606                                        uint32_t byte_count)
1607 {
1608         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1609                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1610         ib->ptr[ib->length_dw++] = byte_count - 1;
1611         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1612         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1613         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1614         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1615         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1616 }
1617
1618 /**
1619  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1620  *
1621  * @ring: amdgpu_ring structure holding ring information
1622  * @src_data: value to write to buffer
1623  * @dst_offset: dst GPU address
1624  * @byte_count: number of bytes to xfer
1625  *
1626  * Fill GPU buffers using the DMA engine (NAVI10).
1627  */
1628 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1629                                        uint32_t src_data,
1630                                        uint64_t dst_offset,
1631                                        uint32_t byte_count)
1632 {
1633         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1634         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1635         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1636         ib->ptr[ib->length_dw++] = src_data;
1637         ib->ptr[ib->length_dw++] = byte_count - 1;
1638 }
1639
1640 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1641         .copy_max_bytes = 0x400000,
1642         .copy_num_dw = 7,
1643         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1644
1645         .fill_max_bytes = 0x400000,
1646         .fill_num_dw = 5,
1647         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1648 };
1649
1650 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1651 {
1652         if (adev->mman.buffer_funcs == NULL) {
1653                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1654                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1655         }
1656 }
1657
1658 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1659         .copy_pte_num_dw = 7,
1660         .copy_pte = sdma_v5_0_vm_copy_pte,
1661         .write_pte = sdma_v5_0_vm_write_pte,
1662         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1663 };
1664
1665 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1666 {
1667         struct drm_gpu_scheduler *sched;
1668         unsigned i;
1669
1670         if (adev->vm_manager.vm_pte_funcs == NULL) {
1671                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1672                 for (i = 0; i < adev->sdma.num_instances; i++) {
1673                         sched = &adev->sdma.instance[i].ring.sched;
1674                         adev->vm_manager.vm_pte_rqs[i] =
1675                                 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1676                 }
1677                 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1678         }
1679 }
1680
1681 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1682         .type = AMD_IP_BLOCK_TYPE_SDMA,
1683         .major = 5,
1684         .minor = 0,
1685         .rev = 0,
1686         .funcs = &sdma_v5_0_ip_funcs,
1687 };