drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 #include "vi.h"
  33 #include "vid.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44
  45 #include "bif/bif_5_0_d.h"
  46 #include "bif/bif_5_0_sh_mask.h"
  47
  48 #include "tonga_sdma_pkt_open.h"
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  56
  57 /*(DEBLOBBED)*/
  58
  59
  60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  61 {
  62         SDMA0_REGISTER_OFFSET,
  63         SDMA1_REGISTER_OFFSET
  64 };
  65
  66 static const u32 golden_settings_tonga_a11[] =
  67 {
  68         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  69         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  70         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  71         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  72         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  73         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  74         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  75         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  76         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  77         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  78 };
  79
  80 static const u32 tonga_mgcg_cgcg_init[] =
  81 {
  82         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  83         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  84 };
  85
  86 static const u32 golden_settings_fiji_a10[] =
  87 {
  88         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  89         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  93         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  94         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  95         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  96 };
  97
  98 static const u32 fiji_mgcg_cgcg_init[] =
  99 {
 100         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 101         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 102 };
 103
 104 static const u32 golden_settings_polaris11_a11[] =
 105 {
 106         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 108         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 110         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 111         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 112         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 113         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 114         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 115         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 116 };
 117
 118 static const u32 golden_settings_polaris10_a11[] =
 119 {
 120         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130 };
 131
 132 static const u32 cz_golden_settings_a11[] =
 133 {
 134         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 135         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 136         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 137         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 138         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 139         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 140         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 141         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 142         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 143         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 144         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 145         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 146 };
 147
 148 static const u32 cz_mgcg_cgcg_init[] =
 149 {
 150         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 151         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 152 };
 153
 154 static const u32 stoney_golden_settings_a11[] =
 155 {
 156         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 157         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 158         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 159         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 160 };
 161
 162 static const u32 stoney_mgcg_cgcg_init[] =
 163 {
 164         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 165 };
 166
 167 /*
 168  * sDMA - System DMA
 169  * Starting with CIK, the GPU has new asynchronous
 170  * DMA engines.  These engines are used for compute
 171  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 172  * and each one supports 1 ring buffer used for gfx
 173  * and 2 queues used for compute.
 174  *
 175  * The programming model is very similar to the CP
 176  * (ring buffer, IBs, etc.), but sDMA has it's own
 177  * packet format that is different from the PM4 format
 178  * used by the CP. sDMA supports copying data, writing
 179  * embedded data, solid fills, and a number of other
 180  * things.  It also has support for tiling/detiling of
 181  * buffers.
 182  */
 183
 184 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 185 {
 186         switch (adev->asic_type) {
 187         case CHIP_FIJI:
 188                 amdgpu_device_program_register_sequence(adev,
 189                                                         fiji_mgcg_cgcg_init,
 190                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 191                 amdgpu_device_program_register_sequence(adev,
 192                                                         golden_settings_fiji_a10,
 193                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 194                 break;
 195         case CHIP_TONGA:
 196                 amdgpu_device_program_register_sequence(adev,
 197                                                         tonga_mgcg_cgcg_init,
 198                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 199                 amdgpu_device_program_register_sequence(adev,
 200                                                         golden_settings_tonga_a11,
 201                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 202                 break;
 203         case CHIP_POLARIS11:
 204         case CHIP_POLARIS12:
 205         case CHIP_VEGAM:
 206                 amdgpu_device_program_register_sequence(adev,
 207                                                         golden_settings_polaris11_a11,
 208                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 209                 break;
 210         case CHIP_POLARIS10:
 211                 amdgpu_device_program_register_sequence(adev,
 212                                                         golden_settings_polaris10_a11,
 213                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 214                 break;
 215         case CHIP_CARRIZO:
 216                 amdgpu_device_program_register_sequence(adev,
 217                                                         cz_mgcg_cgcg_init,
 218                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 219                 amdgpu_device_program_register_sequence(adev,
 220                                                         cz_golden_settings_a11,
 221                                                         ARRAY_SIZE(cz_golden_settings_a11));
 222                 break;
 223         case CHIP_STONEY:
 224                 amdgpu_device_program_register_sequence(adev,
 225                                                         stoney_mgcg_cgcg_init,
 226                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 227                 amdgpu_device_program_register_sequence(adev,
 228                                                         stoney_golden_settings_a11,
 229                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 230                 break;
 231         default:
 232                 break;
 233         }
 234 }
 235
 236 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 237 {
 238         int i;
 239         for (i = 0; i < adev->sdma.num_instances; i++) {
 240                 release_firmware(adev->sdma.instance[i].fw);
 241                 adev->sdma.instance[i].fw = NULL;
 242         }
 243 }
 244
 245 /**
 246  * sdma_v3_0_init_microcode - load ucode images from disk
 247  *
 248  * @adev: amdgpu_device pointer
 249  *
 250  * Use the firmware interface to load the ucode images into
 251  * the driver (not loaded into hw).
 252  * Returns 0 on success, error on failure.
 253  */
 254 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 255 {
 256         const char *chip_name;
 257         char fw_name[30];
 258         int err = 0, i;
 259         struct amdgpu_firmware_info *info = NULL;
 260         const struct common_firmware_header *header = NULL;
 261         const struct sdma_firmware_header_v1_0 *hdr;
 262
 263         DRM_DEBUG("\n");
 264
 265         switch (adev->asic_type) {
 266         case CHIP_TONGA:
 267                 chip_name = "tonga";
 268                 break;
 269         case CHIP_FIJI:
 270                 chip_name = "fiji";
 271                 break;
 272         case CHIP_POLARIS10:
 273                 chip_name = "polaris10";
 274                 break;
 275         case CHIP_POLARIS11:
 276                 chip_name = "polaris11";
 277                 break;
 278         case CHIP_POLARIS12:
 279                 chip_name = "polaris12";
 280                 break;
 281         case CHIP_VEGAM:
 282                 chip_name = "vegam";
 283                 break;
 284         case CHIP_CARRIZO:
 285                 chip_name = "carrizo";
 286                 break;
 287         case CHIP_STONEY:
 288                 chip_name = "stoney";
 289                 break;
 290         default: BUG();
 291         }
 292
 293         for (i = 0; i < adev->sdma.num_instances; i++) {
 294                 if (i == 0)
 295                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 296                 else
 297                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 298                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 299                 if (err)
 300                         goto out;
 301                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 302                 if (err)
 303                         goto out;
 304                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 305                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 306                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 307                 if (adev->sdma.instance[i].feature_version >= 20)
 308                         adev->sdma.instance[i].burst_nop = true;
 309
 310                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 311                 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 312                 info->fw = adev->sdma.instance[i].fw;
 313                 header = (const struct common_firmware_header *)info->fw->data;
 314                 adev->firmware.fw_size +=
 315                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 316
 317         }
 318 out:
 319         if (err) {
 320                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 321                 for (i = 0; i < adev->sdma.num_instances; i++) {
 322                         release_firmware(adev->sdma.instance[i].fw);
 323                         adev->sdma.instance[i].fw = NULL;
 324                 }
 325         }
 326         return err;
 327 }
 328
 329 /**
 330  * sdma_v3_0_ring_get_rptr - get the current read pointer
 331  *
 332  * @ring: amdgpu ring pointer
 333  *
 334  * Get the current rptr from the hardware (VI+).
 335  */
 336 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 337 {
 338         /* XXX check if swapping is necessary on BE */
 339         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 340 }
 341
 342 /**
 343  * sdma_v3_0_ring_get_wptr - get the current write pointer
 344  *
 345  * @ring: amdgpu ring pointer
 346  *
 347  * Get the current wptr from the hardware (VI+).
 348  */
 349 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 350 {
 351         struct amdgpu_device *adev = ring->adev;
 352         u32 wptr;
 353
 354         if (ring->use_doorbell || ring->use_pollmem) {
 355                 /* XXX check if swapping is necessary on BE */
 356                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 357         } else {
 358                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 359         }
 360
 361         return wptr;
 362 }
 363
 364 /**
 365  * sdma_v3_0_ring_set_wptr - commit the write pointer
 366  *
 367  * @ring: amdgpu ring pointer
 368  *
 369  * Write the wptr back to the hardware (VI+).
 370  */
 371 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 372 {
 373         struct amdgpu_device *adev = ring->adev;
 374
 375         if (ring->use_doorbell) {
 376                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 377                 /* XXX check if swapping is necessary on BE */
 378                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 379                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
 380         } else if (ring->use_pollmem) {
 381                 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
 382
 383                 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
 384         } else {
 385                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 386         }
 387 }
 388
 389 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 390 {
 391         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 392         int i;
 393
 394         for (i = 0; i < count; i++)
 395                 if (sdma && sdma->burst_nop && (i == 0))
 396                         amdgpu_ring_write(ring, ring->funcs->nop |
 397                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 398                 else
 399                         amdgpu_ring_write(ring, ring->funcs->nop);
 400 }
 401
 402 /**
 403  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 404  *
 405  * @ring: amdgpu ring pointer
 406  * @ib: IB object to schedule
 407  *
 408  * Schedule an IB in the DMA ring (VI).
 409  */
 410 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 411                                    struct amdgpu_job *job,
 412                                    struct amdgpu_ib *ib,
 413                                    uint32_t flags)
 414 {
 415         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 416
 417         /* IB packet must end on a 8 DW boundary */
 418         sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 419
 420         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 421                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 422         /* base must be 32 byte aligned */
 423         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 424         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 425         amdgpu_ring_write(ring, ib->length_dw);
 426         amdgpu_ring_write(ring, 0);
 427         amdgpu_ring_write(ring, 0);
 428
 429 }
 430
 431 /**
 432  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 433  *
 434  * @ring: amdgpu ring pointer
 435  *
 436  * Emit an hdp flush packet on the requested DMA ring.
 437  */
 438 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 439 {
 440         u32 ref_and_mask = 0;
 441
 442         if (ring->me == 0)
 443                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 444         else
 445                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 446
 447         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 448                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 449                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 450         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 451         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 452         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 453         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 454         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 455                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 456 }
 457
 458 /**
 459  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 460  *
 461  * @ring: amdgpu ring pointer
 462  * @fence: amdgpu fence object
 463  *
 464  * Add a DMA fence packet to the ring to write
 465  * the fence seq number and DMA trap packet to generate
 466  * an interrupt if needed (VI).
 467  */
 468 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 469                                       unsigned flags)
 470 {
 471         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 472         /* write the fence */
 473         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 474         amdgpu_ring_write(ring, lower_32_bits(addr));
 475         amdgpu_ring_write(ring, upper_32_bits(addr));
 476         amdgpu_ring_write(ring, lower_32_bits(seq));
 477
 478         /* optionally write high bits as well */
 479         if (write64bit) {
 480                 addr += 4;
 481                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 482                 amdgpu_ring_write(ring, lower_32_bits(addr));
 483                 amdgpu_ring_write(ring, upper_32_bits(addr));
 484                 amdgpu_ring_write(ring, upper_32_bits(seq));
 485         }
 486
 487         /* generate an interrupt */
 488         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 489         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 490 }
 491
 492 /**
 493  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 494  *
 495  * @adev: amdgpu_device pointer
 496  *
 497  * Stop the gfx async dma ring buffers (VI).
 498  */
 499 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 500 {
 501         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 502         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 503         u32 rb_cntl, ib_cntl;
 504         int i;
 505
 506         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 507             (adev->mman.buffer_funcs_ring == sdma1))
 508                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 509
 510         for (i = 0; i < adev->sdma.num_instances; i++) {
 511                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 512                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 513                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 514                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 515                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 516                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 517         }
 518         sdma0->sched.ready = false;
 519         sdma1->sched.ready = false;
 520 }
 521
 522 /**
 523  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 524  *
 525  * @adev: amdgpu_device pointer
 526  *
 527  * Stop the compute async dma queues (VI).
 528  */
 529 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 530 {
 531         /* XXX todo */
 532 }
 533
 534 /**
 535  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 536  *
 537  * @adev: amdgpu_device pointer
 538  * @enable: enable/disable the DMA MEs context switch.
 539  *
 540  * Halt or unhalt the async dma engines context switch (VI).
 541  */
 542 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 543 {
 544         u32 f32_cntl, phase_quantum = 0;
 545         int i;
 546
 547         if (amdgpu_sdma_phase_quantum) {
 548                 unsigned value = amdgpu_sdma_phase_quantum;
 549                 unsigned unit = 0;
 550
 551                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 552                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 553                         value = (value + 1) >> 1;
 554                         unit++;
 555                 }
 556                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 557                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 558                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 559                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 560                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 561                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 562                         WARN_ONCE(1,
 563                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 564                                   value << unit);
 565                 }
 566                 phase_quantum =
 567                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 568                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 569         }
 570
 571         for (i = 0; i < adev->sdma.num_instances; i++) {
 572                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 573                 if (enable) {
 574                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 575                                         AUTO_CTXSW_ENABLE, 1);
 576                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 577                                         ATC_L1_ENABLE, 1);
 578                         if (amdgpu_sdma_phase_quantum) {
 579                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 580                                        phase_quantum);
 581                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 582                                        phase_quantum);
 583                         }
 584                 } else {
 585                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 586                                         AUTO_CTXSW_ENABLE, 0);
 587                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 588                                         ATC_L1_ENABLE, 1);
 589                 }
 590
 591                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 592         }
 593 }
 594
 595 /**
 596  * sdma_v3_0_enable - stop the async dma engines
 597  *
 598  * @adev: amdgpu_device pointer
 599  * @enable: enable/disable the DMA MEs.
 600  *
 601  * Halt or unhalt the async dma engines (VI).
 602  */
 603 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 604 {
 605         u32 f32_cntl;
 606         int i;
 607
 608         if (!enable) {
 609                 sdma_v3_0_gfx_stop(adev);
 610                 sdma_v3_0_rlc_stop(adev);
 611         }
 612
 613         for (i = 0; i < adev->sdma.num_instances; i++) {
 614                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 615                 if (enable)
 616                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 617                 else
 618                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 619                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 620         }
 621 }
 622
 623 /**
 624  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 625  *
 626  * @adev: amdgpu_device pointer
 627  *
 628  * Set up the gfx DMA ring buffers and enable them (VI).
 629  * Returns 0 for success, error for failure.
 630  */
 631 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 632 {
 633         struct amdgpu_ring *ring;
 634         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 635         u32 rb_bufsz;
 636         u32 wb_offset;
 637         u32 doorbell;
 638         u64 wptr_gpu_addr;
 639         int i, j, r;
 640
 641         for (i = 0; i < adev->sdma.num_instances; i++) {
 642                 ring = &adev->sdma.instance[i].ring;
 643                 amdgpu_ring_clear_ring(ring);
 644                 wb_offset = (ring->rptr_offs * 4);
 645
 646                 mutex_lock(&adev->srbm_mutex);
 647                 for (j = 0; j < 16; j++) {
 648                         vi_srbm_select(adev, 0, 0, 0, j);
 649                         /* SDMA GFX */
 650                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 651                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 652                 }
 653                 vi_srbm_select(adev, 0, 0, 0, 0);
 654                 mutex_unlock(&adev->srbm_mutex);
 655
 656                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 657                        adev->gfx.config.gb_addr_config & 0x70);
 658
 659                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 660
 661                 /* Set ring buffer size in dwords */
 662                 rb_bufsz = order_base_2(ring->ring_size / 4);
 663                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 664                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 665 #ifdef __BIG_ENDIAN
 666                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 667                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 668                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 669 #endif
 670                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 671
 672                 /* Initialize the ring buffer's read and write pointers */
 673                 ring->wptr = 0;
 674                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 675                 sdma_v3_0_ring_set_wptr(ring);
 676                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 677                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 678
 679                 /* set the wb address whether it's enabled or not */
 680                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 681                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 682                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 683                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 684
 685                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 686
 687                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 688                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 689
 690                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 691
 692                 if (ring->use_doorbell) {
 693                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 694                                                  OFFSET, ring->doorbell_index);
 695                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 696                 } else {
 697                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 698                 }
 699                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 700
 701                 /* setup the wptr shadow polling */
 702                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 703
 704                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 705                        lower_32_bits(wptr_gpu_addr));
 706                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 707                        upper_32_bits(wptr_gpu_addr));
 708                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 709                 if (ring->use_pollmem) {
 710                         /*wptr polling is not enogh fast, directly clean the wptr register */
 711                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 712                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 713                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 714                                                        ENABLE, 1);
 715                 } else {
 716                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 717                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 718                                                        ENABLE, 0);
 719                 }
 720                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 721
 722                 /* enable DMA RB */
 723                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 724                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 725
 726                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 727                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 728 #ifdef __BIG_ENDIAN
 729                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 730 #endif
 731                 /* enable DMA IBs */
 732                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 733
 734                 ring->sched.ready = true;
 735         }
 736
 737         /* unhalt the MEs */
 738         sdma_v3_0_enable(adev, true);
 739         /* enable sdma ring preemption */
 740         sdma_v3_0_ctx_switch_enable(adev, true);
 741
 742         for (i = 0; i < adev->sdma.num_instances; i++) {
 743                 ring = &adev->sdma.instance[i].ring;
 744                 r = amdgpu_ring_test_helper(ring);
 745                 if (r)
 746                         return r;
 747
 748                 if (adev->mman.buffer_funcs_ring == ring)
 749                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 750         }
 751
 752         return 0;
 753 }
 754
 755 /**
 756  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 757  *
 758  * @adev: amdgpu_device pointer
 759  *
 760  * Set up the compute DMA queues and enable them (VI).
 761  * Returns 0 for success, error for failure.
 762  */
 763 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 764 {
 765         /* XXX todo */
 766         return 0;
 767 }
 768
 769 /**
 770  * sdma_v3_0_start - setup and start the async dma engines
 771  *
 772  * @adev: amdgpu_device pointer
 773  *
 774  * Set up the DMA engines and enable them (VI).
 775  * Returns 0 for success, error for failure.
 776  */
 777 static int sdma_v3_0_start(struct amdgpu_device *adev)
 778 {
 779         int r;
 780
 781         /* disable sdma engine before programing it */
 782         sdma_v3_0_ctx_switch_enable(adev, false);
 783         sdma_v3_0_enable(adev, false);
 784
 785         /* start the gfx rings and rlc compute queues */
 786         r = sdma_v3_0_gfx_resume(adev);
 787         if (r)
 788                 return r;
 789         r = sdma_v3_0_rlc_resume(adev);
 790         if (r)
 791                 return r;
 792
 793         return 0;
 794 }
 795
 796 /**
 797  * sdma_v3_0_ring_test_ring - simple async dma engine test
 798  *
 799  * @ring: amdgpu_ring structure holding ring information
 800  *
 801  * Test the DMA engine by writing using it to write an
 802  * value to memory. (VI).
 803  * Returns 0 for success, error for failure.
 804  */
 805 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 806 {
 807         struct amdgpu_device *adev = ring->adev;
 808         unsigned i;
 809         unsigned index;
 810         int r;
 811         u32 tmp;
 812         u64 gpu_addr;
 813
 814         r = amdgpu_device_wb_get(adev, &index);
 815         if (r)
 816                 return r;
 817
 818         gpu_addr = adev->wb.gpu_addr + (index * 4);
 819         tmp = 0xCAFEDEAD;
 820         adev->wb.wb[index] = cpu_to_le32(tmp);
 821
 822         r = amdgpu_ring_alloc(ring, 5);
 823         if (r)
 824                 goto error_free_wb;
 825
 826         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 827                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 828         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 829         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 830         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 831         amdgpu_ring_write(ring, 0xDEADBEEF);
 832         amdgpu_ring_commit(ring);
 833
 834         for (i = 0; i < adev->usec_timeout; i++) {
 835                 tmp = le32_to_cpu(adev->wb.wb[index]);
 836                 if (tmp == 0xDEADBEEF)
 837                         break;
 838                 udelay(1);
 839         }
 840
 841         if (i >= adev->usec_timeout)
 842                 r = -ETIMEDOUT;
 843
 844 error_free_wb:
 845         amdgpu_device_wb_free(adev, index);
 846         return r;
 847 }
 848
 849 /**
 850  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 851  *
 852  * @ring: amdgpu_ring structure holding ring information
 853  *
 854  * Test a simple IB in the DMA ring (VI).
 855  * Returns 0 on success, error on failure.
 856  */
 857 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 858 {
 859         struct amdgpu_device *adev = ring->adev;
 860         struct amdgpu_ib ib;
 861         struct dma_fence *f = NULL;
 862         unsigned index;
 863         u32 tmp = 0;
 864         u64 gpu_addr;
 865         long r;
 866
 867         r = amdgpu_device_wb_get(adev, &index);
 868         if (r)
 869                 return r;
 870
 871         gpu_addr = adev->wb.gpu_addr + (index * 4);
 872         tmp = 0xCAFEDEAD;
 873         adev->wb.wb[index] = cpu_to_le32(tmp);
 874         memset(&ib, 0, sizeof(ib));
 875         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 876         if (r)
 877                 goto err0;
 878
 879         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 880                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 881         ib.ptr[1] = lower_32_bits(gpu_addr);
 882         ib.ptr[2] = upper_32_bits(gpu_addr);
 883         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 884         ib.ptr[4] = 0xDEADBEEF;
 885         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 886         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 887         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 888         ib.length_dw = 8;
 889
 890         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 891         if (r)
 892                 goto err1;
 893
 894         r = dma_fence_wait_timeout(f, false, timeout);
 895         if (r == 0) {
 896                 r = -ETIMEDOUT;
 897                 goto err1;
 898         } else if (r < 0) {
 899                 goto err1;
 900         }
 901         tmp = le32_to_cpu(adev->wb.wb[index]);
 902         if (tmp == 0xDEADBEEF)
 903                 r = 0;
 904         else
 905                 r = -EINVAL;
 906 err1:
 907         amdgpu_ib_free(adev, &ib, NULL);
 908         dma_fence_put(f);
 909 err0:
 910         amdgpu_device_wb_free(adev, index);
 911         return r;
 912 }
 913
 914 /**
 915  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 916  *
 917  * @ib: indirect buffer to fill with commands
 918  * @pe: addr of the page entry
 919  * @src: src addr to copy from
 920  * @count: number of page entries to update
 921  *
 922  * Update PTEs by copying them from the GART using sDMA (CIK).
 923  */
 924 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 925                                   uint64_t pe, uint64_t src,
 926                                   unsigned count)
 927 {
 928         unsigned bytes = count * 8;
 929
 930         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 931                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 932         ib->ptr[ib->length_dw++] = bytes;
 933         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 934         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 935         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 936         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 937         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 938 }
 939
 940 /**
 941  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 942  *
 943  * @ib: indirect buffer to fill with commands
 944  * @pe: addr of the page entry
 945  * @value: dst addr to write into pe
 946  * @count: number of page entries to update
 947  * @incr: increase next addr by incr bytes
 948  *
 949  * Update PTEs by writing them manually using sDMA (CIK).
 950  */
 951 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 952                                    uint64_t value, unsigned count,
 953                                    uint32_t incr)
 954 {
 955         unsigned ndw = count * 2;
 956
 957         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 958                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 959         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 960         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 961         ib->ptr[ib->length_dw++] = ndw;
 962         for (; ndw > 0; ndw -= 2) {
 963                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 964                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 965                 value += incr;
 966         }
 967 }
 968
 969 /**
 970  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 971  *
 972  * @ib: indirect buffer to fill with commands
 973  * @pe: addr of the page entry
 974  * @addr: dst addr to write into pe
 975  * @count: number of page entries to update
 976  * @incr: increase next addr by incr bytes
 977  * @flags: access flags
 978  *
 979  * Update the page tables using sDMA (CIK).
 980  */
 981 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 982                                      uint64_t addr, unsigned count,
 983                                      uint32_t incr, uint64_t flags)
 984 {
 985         /* for physically contiguous pages (vram) */
 986         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 987         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 988         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 989         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 990         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 991         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 992         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 993         ib->ptr[ib->length_dw++] = incr; /* increment size */
 994         ib->ptr[ib->length_dw++] = 0;
 995         ib->ptr[ib->length_dw++] = count; /* number of entries */
 996 }
 997
 998 /**
 999  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1000  *
1001  * @ib: indirect buffer to fill with padding
1002  *
1003  */
1004 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1005 {
1006         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1007         u32 pad_count;
1008         int i;
1009
1010         pad_count = (-ib->length_dw) & 7;
1011         for (i = 0; i < pad_count; i++)
1012                 if (sdma && sdma->burst_nop && (i == 0))
1013                         ib->ptr[ib->length_dw++] =
1014                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1015                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1016                 else
1017                         ib->ptr[ib->length_dw++] =
1018                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1019 }
1020
1021 /**
1022  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1023  *
1024  * @ring: amdgpu_ring pointer
1025  *
1026  * Make sure all previous operations are completed (CIK).
1027  */
1028 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1029 {
1030         uint32_t seq = ring->fence_drv.sync_seq;
1031         uint64_t addr = ring->fence_drv.gpu_addr;
1032
1033         /* wait for idle */
1034         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1035                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1036                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1037                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1038         amdgpu_ring_write(ring, addr & 0xfffffffc);
1039         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1040         amdgpu_ring_write(ring, seq); /* reference */
1041         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1042         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1043                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1044 }
1045
1046 /**
1047  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1048  *
1049  * @ring: amdgpu_ring pointer
1050  * @vm: amdgpu_vm pointer
1051  *
1052  * Update the page table base and flush the VM TLB
1053  * using sDMA (VI).
1054  */
1055 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1056                                          unsigned vmid, uint64_t pd_addr)
1057 {
1058         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1059
1060         /* wait for flush */
1061         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1062                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1063                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1064         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1065         amdgpu_ring_write(ring, 0);
1066         amdgpu_ring_write(ring, 0); /* reference */
1067         amdgpu_ring_write(ring, 0); /* mask */
1068         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1069                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1070 }
1071
1072 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1073                                      uint32_t reg, uint32_t val)
1074 {
1075         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1076                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1077         amdgpu_ring_write(ring, reg);
1078         amdgpu_ring_write(ring, val);
1079 }
1080
1081 static int sdma_v3_0_early_init(void *handle)
1082 {
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         switch (adev->asic_type) {
1086         case CHIP_STONEY:
1087                 adev->sdma.num_instances = 1;
1088                 break;
1089         default:
1090                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1091                 break;
1092         }
1093
1094         sdma_v3_0_set_ring_funcs(adev);
1095         sdma_v3_0_set_buffer_funcs(adev);
1096         sdma_v3_0_set_vm_pte_funcs(adev);
1097         sdma_v3_0_set_irq_funcs(adev);
1098
1099         return 0;
1100 }
1101
1102 static int sdma_v3_0_sw_init(void *handle)
1103 {
1104         struct amdgpu_ring *ring;
1105         int r, i;
1106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107
1108         /* SDMA trap event */
1109         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1110                               &adev->sdma.trap_irq);
1111         if (r)
1112                 return r;
1113
1114         /* SDMA Privileged inst */
1115         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1116                               &adev->sdma.illegal_inst_irq);
1117         if (r)
1118                 return r;
1119
1120         /* SDMA Privileged inst */
1121         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1122                               &adev->sdma.illegal_inst_irq);
1123         if (r)
1124                 return r;
1125
1126         r = sdma_v3_0_init_microcode(adev);
1127         if (r) {
1128                 DRM_ERROR("Failed to load sdma firmware!\n");
1129                 return r;
1130         }
1131
1132         for (i = 0; i < adev->sdma.num_instances; i++) {
1133                 ring = &adev->sdma.instance[i].ring;
1134                 ring->ring_obj = NULL;
1135                 if (!amdgpu_sriov_vf(adev)) {
1136                         ring->use_doorbell = true;
1137                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1138                 } else {
1139                         ring->use_pollmem = true;
1140                 }
1141
1142                 sprintf(ring->name, "sdma%d", i);
1143                 r = amdgpu_ring_init(adev, ring, 1024,
1144                                      &adev->sdma.trap_irq,
1145                                      (i == 0) ?
1146                                      AMDGPU_SDMA_IRQ_INSTANCE0 :
1147                                      AMDGPU_SDMA_IRQ_INSTANCE1);
1148                 if (r)
1149                         return r;
1150         }
1151
1152         return r;
1153 }
1154
1155 static int sdma_v3_0_sw_fini(void *handle)
1156 {
1157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158         int i;
1159
1160         for (i = 0; i < adev->sdma.num_instances; i++)
1161                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1162
1163         sdma_v3_0_free_microcode(adev);
1164         return 0;
1165 }
1166
1167 static int sdma_v3_0_hw_init(void *handle)
1168 {
1169         int r;
1170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172         sdma_v3_0_init_golden_registers(adev);
1173
1174         r = sdma_v3_0_start(adev);
1175         if (r)
1176                 return r;
1177
1178         return r;
1179 }
1180
1181 static int sdma_v3_0_hw_fini(void *handle)
1182 {
1183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184
1185         sdma_v3_0_ctx_switch_enable(adev, false);
1186         sdma_v3_0_enable(adev, false);
1187
1188         return 0;
1189 }
1190
1191 static int sdma_v3_0_suspend(void *handle)
1192 {
1193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195         return sdma_v3_0_hw_fini(adev);
1196 }
1197
1198 static int sdma_v3_0_resume(void *handle)
1199 {
1200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1201
1202         return sdma_v3_0_hw_init(adev);
1203 }
1204
1205 static bool sdma_v3_0_is_idle(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208         u32 tmp = RREG32(mmSRBM_STATUS2);
1209
1210         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1211                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1212             return false;
1213
1214         return true;
1215 }
1216
1217 static int sdma_v3_0_wait_for_idle(void *handle)
1218 {
1219         unsigned i;
1220         u32 tmp;
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         for (i = 0; i < adev->usec_timeout; i++) {
1224                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1225                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1226
1227                 if (!tmp)
1228                         return 0;
1229                 udelay(1);
1230         }
1231         return -ETIMEDOUT;
1232 }
1233
1234 static bool sdma_v3_0_check_soft_reset(void *handle)
1235 {
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237         u32 srbm_soft_reset = 0;
1238         u32 tmp = RREG32(mmSRBM_STATUS2);
1239
1240         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1241             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1242                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1243                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1244         }
1245
1246         if (srbm_soft_reset) {
1247                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1248                 return true;
1249         } else {
1250                 adev->sdma.srbm_soft_reset = 0;
1251                 return false;
1252         }
1253 }
1254
1255 static int sdma_v3_0_pre_soft_reset(void *handle)
1256 {
1257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258         u32 srbm_soft_reset = 0;
1259
1260         if (!adev->sdma.srbm_soft_reset)
1261                 return 0;
1262
1263         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1264
1265         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1266             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1267                 sdma_v3_0_ctx_switch_enable(adev, false);
1268                 sdma_v3_0_enable(adev, false);
1269         }
1270
1271         return 0;
1272 }
1273
1274 static int sdma_v3_0_post_soft_reset(void *handle)
1275 {
1276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277         u32 srbm_soft_reset = 0;
1278
1279         if (!adev->sdma.srbm_soft_reset)
1280                 return 0;
1281
1282         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1283
1284         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1285             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1286                 sdma_v3_0_gfx_resume(adev);
1287                 sdma_v3_0_rlc_resume(adev);
1288         }
1289
1290         return 0;
1291 }
1292
1293 static int sdma_v3_0_soft_reset(void *handle)
1294 {
1295         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296         u32 srbm_soft_reset = 0;
1297         u32 tmp;
1298
1299         if (!adev->sdma.srbm_soft_reset)
1300                 return 0;
1301
1302         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1303
1304         if (srbm_soft_reset) {
1305                 tmp = RREG32(mmSRBM_SOFT_RESET);
1306                 tmp |= srbm_soft_reset;
1307                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1308                 WREG32(mmSRBM_SOFT_RESET, tmp);
1309                 tmp = RREG32(mmSRBM_SOFT_RESET);
1310
1311                 udelay(50);
1312
1313                 tmp &= ~srbm_soft_reset;
1314                 WREG32(mmSRBM_SOFT_RESET, tmp);
1315                 tmp = RREG32(mmSRBM_SOFT_RESET);
1316
1317                 /* Wait a little for things to settle down */
1318                 udelay(50);
1319         }
1320
1321         return 0;
1322 }
1323
1324 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1325                                         struct amdgpu_irq_src *source,
1326                                         unsigned type,
1327                                         enum amdgpu_interrupt_state state)
1328 {
1329         u32 sdma_cntl;
1330
1331         switch (type) {
1332         case AMDGPU_SDMA_IRQ_INSTANCE0:
1333                 switch (state) {
1334                 case AMDGPU_IRQ_STATE_DISABLE:
1335                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1336                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1337                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1338                         break;
1339                 case AMDGPU_IRQ_STATE_ENABLE:
1340                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1342                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1343                         break;
1344                 default:
1345                         break;
1346                 }
1347                 break;
1348         case AMDGPU_SDMA_IRQ_INSTANCE1:
1349                 switch (state) {
1350                 case AMDGPU_IRQ_STATE_DISABLE:
1351                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1352                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1353                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1354                         break;
1355                 case AMDGPU_IRQ_STATE_ENABLE:
1356                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1358                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1359                         break;
1360                 default:
1361                         break;
1362                 }
1363                 break;
1364         default:
1365                 break;
1366         }
1367         return 0;
1368 }
1369
1370 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1371                                       struct amdgpu_irq_src *source,
1372                                       struct amdgpu_iv_entry *entry)
1373 {
1374         u8 instance_id, queue_id;
1375
1376         instance_id = (entry->ring_id & 0x3) >> 0;
1377         queue_id = (entry->ring_id & 0xc) >> 2;
1378         DRM_DEBUG("IH: SDMA trap\n");
1379         switch (instance_id) {
1380         case 0:
1381                 switch (queue_id) {
1382                 case 0:
1383                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1384                         break;
1385                 case 1:
1386                         /* XXX compute */
1387                         break;
1388                 case 2:
1389                         /* XXX compute */
1390                         break;
1391                 }
1392                 break;
1393         case 1:
1394                 switch (queue_id) {
1395                 case 0:
1396                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1397                         break;
1398                 case 1:
1399                         /* XXX compute */
1400                         break;
1401                 case 2:
1402                         /* XXX compute */
1403                         break;
1404                 }
1405                 break;
1406         }
1407         return 0;
1408 }
1409
1410 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1411                                               struct amdgpu_irq_src *source,
1412                                               struct amdgpu_iv_entry *entry)
1413 {
1414         u8 instance_id, queue_id;
1415
1416         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1417         instance_id = (entry->ring_id & 0x3) >> 0;
1418         queue_id = (entry->ring_id & 0xc) >> 2;
1419
1420         if (instance_id <= 1 && queue_id == 0)
1421                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1422         return 0;
1423 }
1424
1425 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1426                 struct amdgpu_device *adev,
1427                 bool enable)
1428 {
1429         uint32_t temp, data;
1430         int i;
1431
1432         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1433                 for (i = 0; i < adev->sdma.num_instances; i++) {
1434                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1435                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1436                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1437                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1438                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1439                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1440                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1441                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1442                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1443                         if (data != temp)
1444                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1445                 }
1446         } else {
1447                 for (i = 0; i < adev->sdma.num_instances; i++) {
1448                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1449                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1450                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1451                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1452                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1453                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1454                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1455                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1456                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1457
1458                         if (data != temp)
1459                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1460                 }
1461         }
1462 }
1463
1464 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1465                 struct amdgpu_device *adev,
1466                 bool enable)
1467 {
1468         uint32_t temp, data;
1469         int i;
1470
1471         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1472                 for (i = 0; i < adev->sdma.num_instances; i++) {
1473                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1474                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1475
1476                         if (temp != data)
1477                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1478                 }
1479         } else {
1480                 for (i = 0; i < adev->sdma.num_instances; i++) {
1481                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1482                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1483
1484                         if (temp != data)
1485                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1486                 }
1487         }
1488 }
1489
1490 static int sdma_v3_0_set_clockgating_state(void *handle,
1491                                           enum amd_clockgating_state state)
1492 {
1493         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1494
1495         if (amdgpu_sriov_vf(adev))
1496                 return 0;
1497
1498         switch (adev->asic_type) {
1499         case CHIP_FIJI:
1500         case CHIP_CARRIZO:
1501         case CHIP_STONEY:
1502                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1503                                 state == AMD_CG_STATE_GATE);
1504                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1505                                 state == AMD_CG_STATE_GATE);
1506                 break;
1507         default:
1508                 break;
1509         }
1510         return 0;
1511 }
1512
1513 static int sdma_v3_0_set_powergating_state(void *handle,
1514                                           enum amd_powergating_state state)
1515 {
1516         return 0;
1517 }
1518
1519 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1520 {
1521         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1522         int data;
1523
1524         if (amdgpu_sriov_vf(adev))
1525                 *flags = 0;
1526
1527         /* AMD_CG_SUPPORT_SDMA_MGCG */
1528         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1529         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1530                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1531
1532         /* AMD_CG_SUPPORT_SDMA_LS */
1533         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1534         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1535                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1536 }
1537
1538 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1539         .name = "sdma_v3_0",
1540         .early_init = sdma_v3_0_early_init,
1541         .late_init = NULL,
1542         .sw_init = sdma_v3_0_sw_init,
1543         .sw_fini = sdma_v3_0_sw_fini,
1544         .hw_init = sdma_v3_0_hw_init,
1545         .hw_fini = sdma_v3_0_hw_fini,
1546         .suspend = sdma_v3_0_suspend,
1547         .resume = sdma_v3_0_resume,
1548         .is_idle = sdma_v3_0_is_idle,
1549         .wait_for_idle = sdma_v3_0_wait_for_idle,
1550         .check_soft_reset = sdma_v3_0_check_soft_reset,
1551         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1552         .post_soft_reset = sdma_v3_0_post_soft_reset,
1553         .soft_reset = sdma_v3_0_soft_reset,
1554         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1555         .set_powergating_state = sdma_v3_0_set_powergating_state,
1556         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1557 };
1558
1559 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1560         .type = AMDGPU_RING_TYPE_SDMA,
1561         .align_mask = 0xf,
1562         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1563         .support_64bit_ptrs = false,
1564         .get_rptr = sdma_v3_0_ring_get_rptr,
1565         .get_wptr = sdma_v3_0_ring_get_wptr,
1566         .set_wptr = sdma_v3_0_ring_set_wptr,
1567         .emit_frame_size =
1568                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1569                 3 + /* hdp invalidate */
1570                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1571                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1572                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1573         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1574         .emit_ib = sdma_v3_0_ring_emit_ib,
1575         .emit_fence = sdma_v3_0_ring_emit_fence,
1576         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1577         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1578         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1579         .test_ring = sdma_v3_0_ring_test_ring,
1580         .test_ib = sdma_v3_0_ring_test_ib,
1581         .insert_nop = sdma_v3_0_ring_insert_nop,
1582         .pad_ib = sdma_v3_0_ring_pad_ib,
1583         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1584 };
1585
1586 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1587 {
1588         int i;
1589
1590         for (i = 0; i < adev->sdma.num_instances; i++) {
1591                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1592                 adev->sdma.instance[i].ring.me = i;
1593         }
1594 }
1595
1596 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1597         .set = sdma_v3_0_set_trap_irq_state,
1598         .process = sdma_v3_0_process_trap_irq,
1599 };
1600
1601 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1602         .process = sdma_v3_0_process_illegal_inst_irq,
1603 };
1604
1605 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1606 {
1607         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1608         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1609         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1610 }
1611
1612 /**
1613  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1614  *
1615  * @ring: amdgpu_ring structure holding ring information
1616  * @src_offset: src GPU address
1617  * @dst_offset: dst GPU address
1618  * @byte_count: number of bytes to xfer
1619  *
1620  * Copy GPU buffers using the DMA engine (VI).
1621  * Used by the amdgpu ttm implementation to move pages if
1622  * registered as the asic copy callback.
1623  */
1624 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1625                                        uint64_t src_offset,
1626                                        uint64_t dst_offset,
1627                                        uint32_t byte_count)
1628 {
1629         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1630                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1631         ib->ptr[ib->length_dw++] = byte_count;
1632         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1633         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1634         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1635         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1636         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1637 }
1638
1639 /**
1640  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1641  *
1642  * @ring: amdgpu_ring structure holding ring information
1643  * @src_data: value to write to buffer
1644  * @dst_offset: dst GPU address
1645  * @byte_count: number of bytes to xfer
1646  *
1647  * Fill GPU buffers using the DMA engine (VI).
1648  */
1649 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1650                                        uint32_t src_data,
1651                                        uint64_t dst_offset,
1652                                        uint32_t byte_count)
1653 {
1654         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1655         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1656         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1657         ib->ptr[ib->length_dw++] = src_data;
1658         ib->ptr[ib->length_dw++] = byte_count;
1659 }
1660
1661 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1662         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1663         .copy_num_dw = 7,
1664         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1665
1666         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1667         .fill_num_dw = 5,
1668         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1669 };
1670
1671 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1672 {
1673         adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1674         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1675 }
1676
1677 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1678         .copy_pte_num_dw = 7,
1679         .copy_pte = sdma_v3_0_vm_copy_pte,
1680
1681         .write_pte = sdma_v3_0_vm_write_pte,
1682         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1683 };
1684
1685 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1686 {
1687         unsigned i;
1688
1689         adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1690         for (i = 0; i < adev->sdma.num_instances; i++) {
1691                 adev->vm_manager.vm_pte_scheds[i] =
1692                          &adev->sdma.instance[i].ring.sched;
1693         }
1694         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1695 }
1696
1697 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1698 {
1699         .type = AMD_IP_BLOCK_TYPE_SDMA,
1700         .major = 3,
1701         .minor = 0,
1702         .rev = 0,
1703         .funcs = &sdma_v3_0_ip_funcs,
1704 };
1705
1706 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1707 {
1708         .type = AMD_IP_BLOCK_TYPE_SDMA,
1709         .major = 3,
1710         .minor = 1,
1711         .rev = 0,
1712         .funcs = &sdma_v3_0_ip_funcs,
1713 };