drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_4.h"
  26 #include "amdgpu_ras.h"
  27
  28 #include "nbio/nbio_7_4_offset.h"
  29 #include "nbio/nbio_7_4_sh_mask.h"
  30 #include "nbio/nbio_7_4_0_smn.h"
  31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  32 #include <uapi/linux/kfd_ioctl.h>
  33
  34 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
  35
  36 /*
  37  * These are nbio v7_4_1 registers mask. Temporarily define these here since
  38  * nbio v7_4_1 header is incomplete.
  39  */
  40 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK      0x00001000L
  41 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK      0x00002000L
  42 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK      0x00004000L
  43 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK      0x00008000L
  44 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK      0x00010000L
  45 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK      0x00020000L
  46
  47 #define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
  48 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
  49 //BIF_MMSCH1_DOORBELL_RANGE
  50 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
  51 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
  52 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
  53 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
  54
  55 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
  56                                         void *ras_error_status);
  57
  58 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
  59 {
  60         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
  61                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
  62         WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
  63                 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
  64 }
  65
  66 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
  67 {
  68         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  69
  70         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  71         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  72
  73         return tmp;
  74 }
  75
  76 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
  77 {
  78         if (enable)
  79                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  80                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  81         else
  82                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  83 }
  84
  85 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
  86                                 struct amdgpu_ring *ring)
  87 {
  88         if (!ring || !ring->funcs->emit_wreg)
  89                 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  90         else
  91                 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  92 }
  93
  94 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
  95 {
  96         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  97 }
  98
  99 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
 100                         bool use_doorbell, int doorbell_index, int doorbell_size)
 101 {
 102         u32 reg, doorbell_range;
 103
 104         if (instance < 2)
 105                 reg = instance +
 106                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 107         else
 108                 /*
 109                  * These registers address of SDMA2~7 is not consecutive
 110                  * from SDMA0~1. Need plus 4 dwords offset.
 111                  *
 112                  *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
 113                  *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
 114                  *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
 115                  */
 116                 reg = instance + 0x4 +
 117                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
 118
 119         doorbell_range = RREG32(reg);
 120
 121         if (use_doorbell) {
 122                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
 123                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
 124         } else
 125                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 126
 127         WREG32(reg, doorbell_range);
 128 }
 129
 130 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
 131                                          int doorbell_index, int instance)
 132 {
 133         u32 reg;
 134         u32 doorbell_range;
 135
 136         if (instance)
 137                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
 138         else
 139                 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
 140
 141         doorbell_range = RREG32(reg);
 142
 143         if (use_doorbell) {
 144                 doorbell_range = REG_SET_FIELD(doorbell_range,
 145                                                BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
 146                                                doorbell_index);
 147                 doorbell_range = REG_SET_FIELD(doorbell_range,
 148                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
 149         } else
 150                 doorbell_range = REG_SET_FIELD(doorbell_range,
 151                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
 152
 153         WREG32(reg, doorbell_range);
 154 }
 155
 156 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
 157                                                bool enable)
 158 {
 159         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 160 }
 161
 162 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 163                                                         bool enable)
 164 {
 165         u32 tmp = 0;
 166
 167         if (enable) {
 168                 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 169                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 170                       REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 171
 172                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
 173                              lower_32_bits(adev->doorbell.base));
 174                 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 175                              upper_32_bits(adev->doorbell.base));
 176         }
 177
 178         WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 179 }
 180
 181 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
 182                                         bool use_doorbell, int doorbell_index)
 183 {
 184         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 185
 186         if (use_doorbell) {
 187                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 188                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 189         } else
 190                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 191
 192         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 193 }
 194
 195
 196 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 197                                                        bool enable)
 198 {
 199         //TODO: Add support for v7.4
 200 }
 201
 202 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 203                                                       bool enable)
 204 {
 205         uint32_t def, data;
 206
 207         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 208         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 209                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 210                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 211                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 212         } else {
 213                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 214                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 215                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 216         }
 217
 218         if (def != data)
 219                 WREG32_PCIE(smnPCIE_CNTL2, data);
 220 }
 221
 222 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
 223                                             u32 *flags)
 224 {
 225         int data;
 226
 227         /* AMD_CG_SUPPORT_BIF_MGCG */
 228         data = RREG32_PCIE(smnCPM_CONTROL);
 229         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 230                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 231
 232         /* AMD_CG_SUPPORT_BIF_LS */
 233         data = RREG32_PCIE(smnPCIE_CNTL2);
 234         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 235                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 236 }
 237
 238 static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
 239 {
 240         u32 interrupt_cntl;
 241
 242         /* setup interrupt control */
 243         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 244         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 245         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 246          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 247          */
 248         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 249         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 250         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 251         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 252 }
 253
 254 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 255 {
 256         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 257 }
 258
 259 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 260 {
 261         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 262 }
 263
 264 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
 265 {
 266         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 267 }
 268
 269 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
 270 {
 271         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 272 }
 273
 274 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
 275         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 276         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 277         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 278         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 279         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 280         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 281         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 282         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 283         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 284         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 285         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 286         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 287         .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
 288         .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
 289         .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
 290         .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
 291         .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
 292         .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
 293 };
 294
 295 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
 296 {
 297         uint32_t reg;
 298
 299         reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
 300         if (reg & 1)
 301                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 302
 303         if (reg & 0x80000000)
 304                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 305
 306         if (!reg) {
 307                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 308                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 309         }
 310 }
 311
 312 static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
 313 {
 314
 315 }
 316
 317 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
 318 {
 319         uint32_t bif_doorbell_intr_cntl;
 320         struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
 321         struct ras_err_data err_data = {0, 0, 0, NULL};
 322
 323         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 324         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 325                 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
 326                 /* driver has to clear the interrupt status when bif ring is disabled */
 327                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 328                                                 BIF_DOORBELL_INT_CNTL,
 329                                                 RAS_CNTLR_INTERRUPT_CLEAR, 1);
 330                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 331
 332                 /*
 333                  * clear error status after ras_controller_intr according to
 334                  * hw team and count ue number for query
 335                  */
 336                 nbio_v7_4_query_ras_error_count(adev, &err_data);
 337
 338                 /* logging on error counter and printing for awareness */
 339                 obj->err_data.ue_count += err_data.ue_count;
 340                 obj->err_data.ce_count += err_data.ce_count;
 341
 342                 if (err_data.ce_count)
 343                         DRM_INFO("%ld correctable errors detected in %s block\n",
 344                                 obj->err_data.ce_count, adev->nbio.ras_if->name);
 345
 346                 if (err_data.ue_count)
 347                         DRM_INFO("%ld uncorrectable errors detected in %s block\n",
 348                                 obj->err_data.ue_count, adev->nbio.ras_if->name);
 349
 350                 DRM_WARN("RAS controller interrupt triggered by NBIF error\n");
 351
 352                 /* ras_controller_int is dedicated for nbif ras error,
 353                  * not the global interrupt for sync flood
 354                  */
 355                 amdgpu_ras_reset_gpu(adev);
 356         }
 357 }
 358
 359 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
 360 {
 361         uint32_t bif_doorbell_intr_cntl;
 362
 363         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
 364         if (REG_GET_FIELD(bif_doorbell_intr_cntl,
 365                 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
 366                 /* driver has to clear the interrupt status when bif ring is disabled */
 367                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
 368                                                 BIF_DOORBELL_INT_CNTL,
 369                                                 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
 370                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
 371
 372                 amdgpu_ras_global_ras_isr(adev);
 373         }
 374 }
 375
 376
 377 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
 378                                                   struct amdgpu_irq_src *src,
 379                                                   unsigned type,
 380                                                   enum amdgpu_interrupt_state state)
 381 {
 382         /* The ras_controller_irq enablement should be done in psp bl when it
 383          * tries to enable ras feature. Driver only need to set the correct interrupt
 384          * vector for bare-metal and sriov use case respectively
 385          */
 386         uint32_t bif_intr_cntl;
 387
 388         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 389         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 390                 /* set interrupt vector select bit to 0 to select
 391                  * vetcor 1 for bare metal case */
 392                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 393                                               BIF_INTR_CNTL,
 394                                               RAS_INTR_VEC_SEL, 0);
 395                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
 402                                                 struct amdgpu_irq_src *source,
 403                                                 struct amdgpu_iv_entry *entry)
 404 {
 405         /* By design, the ih cookie for ras_controller_irq should be written
 406          * to BIFring instead of general iv ring. However, due to known bif ring
 407          * hw bug, it has to be disabled. There is no chance the process function
 408          * will be involked. Just left it as a dummy one.
 409          */
 410         return 0;
 411 }
 412
 413 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
 414                                                        struct amdgpu_irq_src *src,
 415                                                        unsigned type,
 416                                                        enum amdgpu_interrupt_state state)
 417 {
 418         /* The ras_controller_irq enablement should be done in psp bl when it
 419          * tries to enable ras feature. Driver only need to set the correct interrupt
 420          * vector for bare-metal and sriov use case respectively
 421          */
 422         uint32_t bif_intr_cntl;
 423
 424         bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
 425         if (state == AMDGPU_IRQ_STATE_ENABLE) {
 426                 /* set interrupt vector select bit to 0 to select
 427                  * vetcor 1 for bare metal case */
 428                 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
 429                                               BIF_INTR_CNTL,
 430                                               RAS_INTR_VEC_SEL, 0);
 431                 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
 438                                                  struct amdgpu_irq_src *source,
 439                                                  struct amdgpu_iv_entry *entry)
 440 {
 441         /* By design, the ih cookie for err_event_athub_irq should be written
 442          * to BIFring instead of general iv ring. However, due to known bif ring
 443          * hw bug, it has to be disabled. There is no chance the process function
 444          * will be involked. Just left it as a dummy one.
 445          */
 446         return 0;
 447 }
 448
 449 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
 450         .set = nbio_v7_4_set_ras_controller_irq_state,
 451         .process = nbio_v7_4_process_ras_controller_irq,
 452 };
 453
 454 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
 455         .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
 456         .process = nbio_v7_4_process_err_event_athub_irq,
 457 };
 458
 459 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
 460 {
 461         int r;
 462
 463         /* init the irq funcs */
 464         adev->nbio.ras_controller_irq.funcs =
 465                 &nbio_v7_4_ras_controller_irq_funcs;
 466         adev->nbio.ras_controller_irq.num_types = 1;
 467
 468         /* register ras controller interrupt */
 469         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 470                               NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
 471                               &adev->nbio.ras_controller_irq);
 472
 473         return r;
 474 }
 475
 476 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
 477 {
 478
 479         int r;
 480
 481         /* init the irq funcs */
 482         adev->nbio.ras_err_event_athub_irq.funcs =
 483                 &nbio_v7_4_ras_err_event_athub_irq_funcs;
 484         adev->nbio.ras_err_event_athub_irq.num_types = 1;
 485
 486         /* register ras err event athub interrupt */
 487         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
 488                               NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
 489                               &adev->nbio.ras_err_event_athub_irq);
 490
 491         return r;
 492 }
 493
 494 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2      0x13a20030
 495
 496 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
 497                                         void *ras_error_status)
 498 {
 499         uint32_t global_sts, central_sts, int_eoi, parity_sts;
 500         uint32_t corr, fatal, non_fatal;
 501         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 502
 503         global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
 504         corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
 505         fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
 506         non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
 507                                 ParityErrNonFatal);
 508         parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
 509
 510         if (corr)
 511                 err_data->ce_count++;
 512         if (fatal)
 513                 err_data->ue_count++;
 514
 515         if (corr || fatal || non_fatal) {
 516                 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
 517                 /* clear error status register */
 518                 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
 519
 520                 if (fatal)
 521                         /* clear parity fatal error indication field */
 522                         WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
 523                                     parity_sts);
 524
 525                 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
 526                                 BIFL_RasContller_Intr_Recv)) {
 527                         /* clear interrupt status register */
 528                         WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
 529                         int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
 530                         int_eoi = REG_SET_FIELD(int_eoi,
 531                                         IOHC_INTERRUPT_EOI, SMI_EOI, 1);
 532                         WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
 533                 }
 534         }
 535 }
 536
 537 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
 538                                                 bool enable)
 539 {
 540         WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
 541                        DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
 542 }
 543
 544 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
 545         .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
 546         .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
 547         .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
 548         .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
 549         .get_rev_id = nbio_v7_4_get_rev_id,
 550         .mc_access_enable = nbio_v7_4_mc_access_enable,
 551         .hdp_flush = nbio_v7_4_hdp_flush,
 552         .get_memsize = nbio_v7_4_get_memsize,
 553         .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
 554         .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
 555         .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
 556         .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
 557         .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
 558         .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
 559         .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
 560         .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
 561         .get_clockgating_state = nbio_v7_4_get_clockgating_state,
 562         .ih_control = nbio_v7_4_ih_control,
 563         .init_registers = nbio_v7_4_init_registers,
 564         .detect_hw_virt = nbio_v7_4_detect_hw_virt,
 565         .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
 566         .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
 567         .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
 568         .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
 569         .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
 570         .query_ras_error_count = nbio_v7_4_query_ras_error_count,
 571         .ras_late_init = amdgpu_nbio_ras_late_init,
 572 };