drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v2_3.h"
  26
  27 #include "nbio/nbio_2_3_default.h"
  28 #include "nbio/nbio_2_3_offset.h"
  29 #include "nbio/nbio_2_3_sh_mask.h"
  30
  31 #define smnPCIE_CONFIG_CNTL     0x11180044
  32 #define smnCPM_CONTROL          0x11180460
  33 #define smnPCIE_CNTL2           0x11180070
  34
  35 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
  36 {
  37         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  38
  39         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  40         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  41
  42         return tmp;
  43 }
  44
  45 static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable)
  46 {
  47         if (enable)
  48                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  49                              BIF_FB_EN__FB_READ_EN_MASK |
  50                              BIF_FB_EN__FB_WRITE_EN_MASK);
  51         else
  52                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  53 }
  54
  55 static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev,
  56                                 struct amdgpu_ring *ring)
  57 {
  58         if (!ring || !ring->funcs->emit_wreg)
  59                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  60         else
  61                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  62                         NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  63 }
  64
  65 static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev)
  66 {
  67         return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
  68 }
  69
  70 static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  71                                           bool use_doorbell, int doorbell_index,
  72                                           int doorbell_size)
  73 {
  74         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  75                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  76
  77         u32 doorbell_range = RREG32(reg);
  78
  79         if (use_doorbell) {
  80                 doorbell_range = REG_SET_FIELD(doorbell_range,
  81                                                BIF_SDMA0_DOORBELL_RANGE, OFFSET,
  82                                                doorbell_index);
  83                 doorbell_range = REG_SET_FIELD(doorbell_range,
  84                                                BIF_SDMA0_DOORBELL_RANGE, SIZE,
  85                                                doorbell_size);
  86         } else
  87                 doorbell_range = REG_SET_FIELD(doorbell_range,
  88                                                BIF_SDMA0_DOORBELL_RANGE, SIZE,
  89                                                0);
  90
  91         WREG32(reg, doorbell_range);
  92 }
  93
  94 static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
  95                                          int doorbell_index)
  96 {
  97         u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
  98
  99         u32 doorbell_range = RREG32(reg);
 100
 101         if (use_doorbell) {
 102                 doorbell_range = REG_SET_FIELD(doorbell_range,
 103                                                BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
 104                                                doorbell_index);
 105                 doorbell_range = REG_SET_FIELD(doorbell_range,
 106                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
 107         } else
 108                 doorbell_range = REG_SET_FIELD(doorbell_range,
 109                                                BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
 110
 111         WREG32(reg, doorbell_range);
 112 }
 113
 114 static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev,
 115                                                bool enable)
 116 {
 117         WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN,
 118                        enable ? 1 : 0);
 119 }
 120
 121 static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 122                                                         bool enable)
 123 {
 124         u32 tmp = 0;
 125
 126         if (enable) {
 127                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
 128                                     DOORBELL_SELFRING_GPA_APER_EN, 1) |
 129                       REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
 130                                     DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 131                       REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
 132                                     DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 133
 134                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 135                              lower_32_bits(adev->doorbell.base));
 136                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 137                              upper_32_bits(adev->doorbell.base));
 138         }
 139
 140         WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,
 141                      tmp);
 142 }
 143
 144
 145 static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev,
 146                                         bool use_doorbell, int doorbell_index)
 147 {
 148         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
 149
 150         if (use_doorbell) {
 151                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 152                                                   BIF_IH_DOORBELL_RANGE, OFFSET,
 153                                                   doorbell_index);
 154                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 155                                                   BIF_IH_DOORBELL_RANGE, SIZE,
 156                                                   2);
 157         } else
 158                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 159                                                   BIF_IH_DOORBELL_RANGE, SIZE,
 160                                                   0);
 161
 162         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 163 }
 164
 165 static void nbio_v2_3_ih_control(struct amdgpu_device *adev)
 166 {
 167         u32 interrupt_cntl;
 168
 169         /* setup interrupt control */
 170         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 171
 172         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 173         /*
 174          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 175          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 176          */
 177         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
 178                                        IH_DUMMY_RD_OVERRIDE, 0);
 179
 180         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 181         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,
 182                                        IH_REQ_NONSNOOP_EN, 0);
 183
 184         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 185 }
 186
 187 static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 188                                                        bool enable)
 189 {
 190         uint32_t def, data;
 191
 192         def = data = RREG32_PCIE(smnCPM_CONTROL);
 193         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
 194                 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 195                          CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 196                          CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 197                          CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 198                          CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 199                          CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 200         } else {
 201                 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 202                           CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 203                           CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 204                           CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 205                           CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 206                           CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 207         }
 208
 209         if (def != data)
 210                 WREG32_PCIE(smnCPM_CONTROL, data);
 211 }
 212
 213 static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 214                                                       bool enable)
 215 {
 216         uint32_t def, data;
 217
 218         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 219         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 220                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 221                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 222                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 223         } else {
 224                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 225                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 226                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 227         }
 228
 229         if (def != data)
 230                 WREG32_PCIE(smnPCIE_CNTL2, data);
 231 }
 232
 233 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev,
 234                                             u32 *flags)
 235 {
 236         int data;
 237
 238         /* AMD_CG_SUPPORT_BIF_MGCG */
 239         data = RREG32_PCIE(smnCPM_CONTROL);
 240         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 241                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 242
 243         /* AMD_CG_SUPPORT_BIF_LS */
 244         data = RREG32_PCIE(smnPCIE_CNTL2);
 245         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 246                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 247 }
 248
 249 static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 250 {
 251         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
 252 }
 253
 254 static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 255 {
 256         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
 257 }
 258
 259 static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev)
 260 {
 261         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 262 }
 263
 264 static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev)
 265 {
 266         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 267 }
 268
 269 const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = {
 270         .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK,
 271         .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK,
 272         .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK,
 273         .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK,
 274         .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK,
 275         .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK,
 276         .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK,
 277         .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK,
 278         .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK,
 279         .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK,
 280         .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 281         .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 282 };
 283
 284 static void nbio_v2_3_detect_hw_virt(struct amdgpu_device *adev)
 285 {
 286         uint32_t reg;
 287
 288         reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER);
 289         if (reg & 1)
 290                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 291
 292         if (reg & 0x80000000)
 293                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 294
 295         if (!reg) {
 296                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 297                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 298         }
 299 }
 300
 301 static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
 302 {
 303         uint32_t def, data;
 304
 305         def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
 306         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 307         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 308
 309         if (def != data)
 310                 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 311 }
 312
 313 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
 314         .hdp_flush_reg = &nbio_v2_3_hdp_flush_reg,
 315         .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
 316         .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
 317         .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset,
 318         .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset,
 319         .get_rev_id = nbio_v2_3_get_rev_id,
 320         .mc_access_enable = nbio_v2_3_mc_access_enable,
 321         .hdp_flush = nbio_v2_3_hdp_flush,
 322         .get_memsize = nbio_v2_3_get_memsize,
 323         .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range,
 324         .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range,
 325         .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture,
 326         .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture,
 327         .ih_doorbell_range = nbio_v2_3_ih_doorbell_range,
 328         .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating,
 329         .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep,
 330         .get_clockgating_state = nbio_v2_3_get_clockgating_state,
 331         .ih_control = nbio_v2_3_ih_control,
 332         .init_registers = nbio_v2_3_init_registers,
 333         .detect_hw_virt = nbio_v2_3_detect_hw_virt,
 334 };