drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "gmc_v8_0.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_amdkfd.h"
  33 #include "amdgpu_gem.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "oss/oss_3_0_d.h"
  42 #include "oss/oss_3_0_sh_mask.h"
  43
  44 #include "dce/dce_10_0_d.h"
  45 #include "dce/dce_10_0_sh_mask.h"
  46
  47 #include "vid.h"
  48 #include "vi.h"
  49
  50 #include "amdgpu_atombios.h"
  51
  52 #include "ivsrcid/ivsrcid_vislands30.h"
  53
  54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  56 static int gmc_v8_0_wait_for_idle(void *handle);
  57
  58 /*(DEBLOBBED)*/
  59
  60 static const u32 golden_settings_tonga_a11[] =
  61 {
  62         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  63         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  64         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  65         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  67         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  68         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69 };
  70
  71 static const u32 tonga_mgcg_cgcg_init[] =
  72 {
  73         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  74 };
  75
  76 static const u32 golden_settings_fiji_a10[] =
  77 {
  78         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  79         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  80         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  81         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82 };
  83
  84 static const u32 fiji_mgcg_cgcg_init[] =
  85 {
  86         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  87 };
  88
  89 static const u32 golden_settings_polaris11_a11[] =
  90 {
  91         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  93         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  94         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  95 };
  96
  97 static const u32 golden_settings_polaris10_a11[] =
  98 {
  99         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
 100         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 101         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 102         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 103         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 104 };
 105
 106 static const u32 cz_mgcg_cgcg_init[] =
 107 {
 108         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 109 };
 110
 111 static const u32 stoney_mgcg_cgcg_init[] =
 112 {
 113         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 114         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 115 };
 116
 117 static const u32 golden_settings_stoney_common[] =
 118 {
 119         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 120         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 121 };
 122
 123 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 124 {
 125         switch (adev->asic_type) {
 126         case CHIP_FIJI:
 127                 amdgpu_device_program_register_sequence(adev,
 128                                                         fiji_mgcg_cgcg_init,
 129                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 130                 amdgpu_device_program_register_sequence(adev,
 131                                                         golden_settings_fiji_a10,
 132                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 133                 break;
 134         case CHIP_TONGA:
 135                 amdgpu_device_program_register_sequence(adev,
 136                                                         tonga_mgcg_cgcg_init,
 137                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 138                 amdgpu_device_program_register_sequence(adev,
 139                                                         golden_settings_tonga_a11,
 140                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 141                 break;
 142         case CHIP_POLARIS11:
 143         case CHIP_POLARIS12:
 144         case CHIP_VEGAM:
 145                 amdgpu_device_program_register_sequence(adev,
 146                                                         golden_settings_polaris11_a11,
 147                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 148                 break;
 149         case CHIP_POLARIS10:
 150                 amdgpu_device_program_register_sequence(adev,
 151                                                         golden_settings_polaris10_a11,
 152                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 153                 break;
 154         case CHIP_CARRIZO:
 155                 amdgpu_device_program_register_sequence(adev,
 156                                                         cz_mgcg_cgcg_init,
 157                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 158                 break;
 159         case CHIP_STONEY:
 160                 amdgpu_device_program_register_sequence(adev,
 161                                                         stoney_mgcg_cgcg_init,
 162                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 163                 amdgpu_device_program_register_sequence(adev,
 164                                                         golden_settings_stoney_common,
 165                                                         ARRAY_SIZE(golden_settings_stoney_common));
 166                 break;
 167         default:
 168                 break;
 169         }
 170 }
 171
 172 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 173 {
 174         u32 blackout;
 175
 176         gmc_v8_0_wait_for_idle(adev);
 177
 178         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 179         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 180                 /* Block CPU access */
 181                 WREG32(mmBIF_FB_EN, 0);
 182                 /* blackout the MC */
 183                 blackout = REG_SET_FIELD(blackout,
 184                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 185                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 186         }
 187         /* wait for the MC to settle */
 188         udelay(100);
 189 }
 190
 191 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 192 {
 193         u32 tmp;
 194
 195         /* unblackout the MC */
 196         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 197         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 198         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 199         /* allow CPU access */
 200         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 201         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 202         WREG32(mmBIF_FB_EN, tmp);
 203 }
 204
 205 /**
 206  * gmc_v8_0_init_microcode - load ucode images from disk
 207  *
 208  * @adev: amdgpu_device pointer
 209  *
 210  * Use the firmware interface to load the ucode images into
 211  * the driver (not loaded into hw).
 212  * Returns 0 on success, error on failure.
 213  */
 214 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 215 {
 216         const char *chip_name;
 217         char fw_name[30];
 218         int err;
 219
 220         DRM_DEBUG("\n");
 221
 222         switch (adev->asic_type) {
 223         case CHIP_TONGA:
 224                 chip_name = "tonga";
 225                 break;
 226         case CHIP_POLARIS11:
 227                 if (((adev->pdev->device == 0x67ef) &&
 228                      ((adev->pdev->revision == 0xe0) ||
 229                       (adev->pdev->revision == 0xe5))) ||
 230                     ((adev->pdev->device == 0x67ff) &&
 231                      ((adev->pdev->revision == 0xcf) ||
 232                       (adev->pdev->revision == 0xef) ||
 233                       (adev->pdev->revision == 0xff))))
 234                         chip_name = "polaris11_k";
 235                 else if ((adev->pdev->device == 0x67ef) &&
 236                          (adev->pdev->revision == 0xe2))
 237                         chip_name = "polaris11_k";
 238                 else
 239                         chip_name = "polaris11";
 240                 break;
 241         case CHIP_POLARIS10:
 242                 if ((adev->pdev->device == 0x67df) &&
 243                     ((adev->pdev->revision == 0xe1) ||
 244                      (adev->pdev->revision == 0xf7)))
 245                         chip_name = "polaris10_k";
 246                 else
 247                         chip_name = "polaris10";
 248                 break;
 249         case CHIP_POLARIS12:
 250                 if (((adev->pdev->device == 0x6987) &&
 251                      ((adev->pdev->revision == 0xc0) ||
 252                       (adev->pdev->revision == 0xc3))) ||
 253                     ((adev->pdev->device == 0x6981) &&
 254                      ((adev->pdev->revision == 0x00) ||
 255                       (adev->pdev->revision == 0x01) ||
 256                       (adev->pdev->revision == 0x10))))
 257                         chip_name = "polaris12_k";
 258                 else
 259                         chip_name = "polaris12";
 260                 break;
 261         case CHIP_FIJI:
 262         case CHIP_CARRIZO:
 263         case CHIP_STONEY:
 264         case CHIP_VEGAM:
 265                 return 0;
 266         default: BUG();
 267         }
 268
 269         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 270         err = reject_firmware(&adev->gmc.fw, fw_name, adev->dev);
 271         if (err)
 272                 goto out;
 273         err = amdgpu_ucode_validate(adev->gmc.fw);
 274
 275 out:
 276         if (err) {
 277                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 278                 release_firmware(adev->gmc.fw);
 279                 adev->gmc.fw = NULL;
 280         }
 281         return err;
 282 }
 283
 284 /**
 285  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 286  *
 287  * @adev: amdgpu_device pointer
 288  *
 289  * Load the GDDR MC ucode into the hw (VI).
 290  * Returns 0 on success, error on failure.
 291  */
 292 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 293 {
 294         const struct mc_firmware_header_v1_0 *hdr;
 295         const __le32 *fw_data = NULL;
 296         const __le32 *io_mc_regs = NULL;
 297         u32 running;
 298         int i, ucode_size, regs_size;
 299
 300         /* Skip MC ucode loading on SR-IOV capable boards.
 301          * vbios does this for us in asic_init in that case.
 302          * Skip MC ucode loading on VF, because hypervisor will do that
 303          * for this adaptor.
 304          */
 305         if (amdgpu_sriov_bios(adev))
 306                 return 0;
 307
 308         if (!adev->gmc.fw)
 309                 return -EINVAL;
 310
 311         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 312         amdgpu_ucode_print_mc_hdr(&hdr->header);
 313
 314         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 315         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 316         io_mc_regs = (const __le32 *)
 317                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 318         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 319         fw_data = (const __le32 *)
 320                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 321
 322         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 323
 324         if (running == 0) {
 325                 /* reset the engine and set to writable */
 326                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 327                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 328
 329                 /* load mc io regs */
 330                 for (i = 0; i < regs_size; i++) {
 331                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 332                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 333                 }
 334                 /* load the MC ucode */
 335                 for (i = 0; i < ucode_size; i++)
 336                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 337
 338                 /* put the engine back into the active state */
 339                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 340                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 341                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 342
 343                 /* wait for training to complete */
 344                 for (i = 0; i < adev->usec_timeout; i++) {
 345                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 346                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 347                                 break;
 348                         udelay(1);
 349                 }
 350                 for (i = 0; i < adev->usec_timeout; i++) {
 351                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 352                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 353                                 break;
 354                         udelay(1);
 355                 }
 356         }
 357
 358         return 0;
 359 }
 360
 361 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 362 {
 363         const struct mc_firmware_header_v1_0 *hdr;
 364         const __le32 *fw_data = NULL;
 365         const __le32 *io_mc_regs = NULL;
 366         u32 data;
 367         int i, ucode_size, regs_size;
 368
 369         /* Skip MC ucode loading on SR-IOV capable boards.
 370          * vbios does this for us in asic_init in that case.
 371          * Skip MC ucode loading on VF, because hypervisor will do that
 372          * for this adaptor.
 373          */
 374         if (amdgpu_sriov_bios(adev))
 375                 return 0;
 376
 377         if (!adev->gmc.fw)
 378                 return -EINVAL;
 379
 380         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 381         amdgpu_ucode_print_mc_hdr(&hdr->header);
 382
 383         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 384         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 385         io_mc_regs = (const __le32 *)
 386                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 387         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 388         fw_data = (const __le32 *)
 389                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 390
 391         data = RREG32(mmMC_SEQ_MISC0);
 392         data &= ~(0x40);
 393         WREG32(mmMC_SEQ_MISC0, data);
 394
 395         /* load mc io regs */
 396         for (i = 0; i < regs_size; i++) {
 397                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 398                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 399         }
 400
 401         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 402         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 403
 404         /* load the MC ucode */
 405         for (i = 0; i < ucode_size; i++)
 406                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 407
 408         /* put the engine back into the active state */
 409         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 410         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 411         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 412
 413         /* wait for training to complete */
 414         for (i = 0; i < adev->usec_timeout; i++) {
 415                 data = RREG32(mmMC_SEQ_MISC0);
 416                 if (data & 0x80)
 417                         break;
 418                 udelay(1);
 419         }
 420
 421         return 0;
 422 }
 423
 424 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 425                                        struct amdgpu_gmc *mc)
 426 {
 427         u64 base = 0;
 428
 429         if (!amdgpu_sriov_vf(adev))
 430                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 431         base <<= 24;
 432
 433         amdgpu_gmc_vram_location(adev, mc, base);
 434         amdgpu_gmc_gart_location(adev, mc);
 435 }
 436
 437 /**
 438  * gmc_v8_0_mc_program - program the GPU memory controller
 439  *
 440  * @adev: amdgpu_device pointer
 441  *
 442  * Set the location of vram, gart, and AGP in the GPU's
 443  * physical address space (VI).
 444  */
 445 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 446 {
 447         u32 tmp;
 448         int i, j;
 449
 450         /* Initialize HDP */
 451         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 452                 WREG32((0xb05 + j), 0x00000000);
 453                 WREG32((0xb06 + j), 0x00000000);
 454                 WREG32((0xb07 + j), 0x00000000);
 455                 WREG32((0xb08 + j), 0x00000000);
 456                 WREG32((0xb09 + j), 0x00000000);
 457         }
 458         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 459
 460         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 461                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 462         }
 463         if (adev->mode_info.num_crtc) {
 464                 /* Lockout access through VGA aperture*/
 465                 tmp = RREG32(mmVGA_HDP_CONTROL);
 466                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 467                 WREG32(mmVGA_HDP_CONTROL, tmp);
 468
 469                 /* disable VGA render */
 470                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 471                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 472                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 473         }
 474         /* Update configuration */
 475         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 476                adev->gmc.vram_start >> 12);
 477         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 478                adev->gmc.vram_end >> 12);
 479         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 480                adev->vram_scratch.gpu_addr >> 12);
 481
 482         if (amdgpu_sriov_vf(adev)) {
 483                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 484                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 485                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 486                 /* XXX double check these! */
 487                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 488                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 489                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 490         }
 491
 492         WREG32(mmMC_VM_AGP_BASE, 0);
 493         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 494         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 495         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 496                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 497         }
 498
 499         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 500
 501         tmp = RREG32(mmHDP_MISC_CNTL);
 502         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 503         WREG32(mmHDP_MISC_CNTL, tmp);
 504
 505         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 506         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 507 }
 508
 509 /**
 510  * gmc_v8_0_mc_init - initialize the memory controller driver params
 511  *
 512  * @adev: amdgpu_device pointer
 513  *
 514  * Look up the amount of vram, vram width, and decide how to place
 515  * vram and gart within the GPU's physical address space (VI).
 516  * Returns 0 for success.
 517  */
 518 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 519 {
 520         int r;
 521
 522         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 523         if (!adev->gmc.vram_width) {
 524                 u32 tmp;
 525                 int chansize, numchan;
 526
 527                 /* Get VRAM informations */
 528                 tmp = RREG32(mmMC_ARB_RAMCFG);
 529                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 530                         chansize = 64;
 531                 } else {
 532                         chansize = 32;
 533                 }
 534                 tmp = RREG32(mmMC_SHARED_CHMAP);
 535                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 536                 case 0:
 537                 default:
 538                         numchan = 1;
 539                         break;
 540                 case 1:
 541                         numchan = 2;
 542                         break;
 543                 case 2:
 544                         numchan = 4;
 545                         break;
 546                 case 3:
 547                         numchan = 8;
 548                         break;
 549                 case 4:
 550                         numchan = 3;
 551                         break;
 552                 case 5:
 553                         numchan = 6;
 554                         break;
 555                 case 6:
 556                         numchan = 10;
 557                         break;
 558                 case 7:
 559                         numchan = 12;
 560                         break;
 561                 case 8:
 562                         numchan = 16;
 563                         break;
 564                 }
 565                 adev->gmc.vram_width = numchan * chansize;
 566         }
 567         /* size in MB on si */
 568         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 569         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 570
 571         if (!(adev->flags & AMD_IS_APU)) {
 572                 r = amdgpu_device_resize_fb_bar(adev);
 573                 if (r)
 574                         return r;
 575         }
 576         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 577         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 578
 579 #ifdef CONFIG_X86_64
 580         if (adev->flags & AMD_IS_APU) {
 581                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 582                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 583         }
 584 #endif
 585
 586         /* In case the PCI BAR is larger than the actual amount of vram */
 587         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 588         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 589                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 590
 591         /* set the gart size */
 592         if (amdgpu_gart_size == -1) {
 593                 switch (adev->asic_type) {
 594                 case CHIP_POLARIS10: /* all engines support GPUVM */
 595                 case CHIP_POLARIS11: /* all engines support GPUVM */
 596                 case CHIP_POLARIS12: /* all engines support GPUVM */
 597                 case CHIP_VEGAM:     /* all engines support GPUVM */
 598                 default:
 599                         adev->gmc.gart_size = 256ULL << 20;
 600                         break;
 601                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 602                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 603                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 604                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 605                         adev->gmc.gart_size = 1024ULL << 20;
 606                         break;
 607                 }
 608         } else {
 609                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 610         }
 611
 612         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * GART
 619  * VMID 0 is the physical GPU addresses as used by the kernel.
 620  * VMIDs 1-15 are used for userspace clients and are handled
 621  * by the amdgpu vm/hsa code.
 622  */
 623
 624 /**
 625  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 626  *
 627  * @adev: amdgpu_device pointer
 628  * @vmid: vm instance to flush
 629  *
 630  * Flush the TLB for the requested page table (VI).
 631  */
 632 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 633                                 uint32_t vmid, uint32_t flush_type)
 634 {
 635         /* bits 0-15 are the VM contexts0-15 */
 636         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 637 }
 638
 639 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 640                                             unsigned vmid, uint64_t pd_addr)
 641 {
 642         uint32_t reg;
 643
 644         if (vmid < 8)
 645                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 646         else
 647                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 648         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 649
 650         /* bits 0-15 are the VM contexts0-15 */
 651         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 652
 653         return pd_addr;
 654 }
 655
 656 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 657                                         unsigned pasid)
 658 {
 659         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 660 }
 661
 662 /*
 663  * PTE format on VI:
 664  * 63:40 reserved
 665  * 39:12 4k physical page base address
 666  * 11:7 fragment
 667  * 6 write
 668  * 5 read
 669  * 4 exe
 670  * 3 reserved
 671  * 2 snooped
 672  * 1 system
 673  * 0 valid
 674  *
 675  * PDE format on VI:
 676  * 63:59 block fragment size
 677  * 58:40 reserved
 678  * 39:1 physical base address of PTE
 679  * bits 5:1 must be 0.
 680  * 0 valid
 681  */
 682
 683 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 684                                           uint32_t flags)
 685 {
 686         uint64_t pte_flag = 0;
 687
 688         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 689                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 690         if (flags & AMDGPU_VM_PAGE_READABLE)
 691                 pte_flag |= AMDGPU_PTE_READABLE;
 692         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 693                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 694         if (flags & AMDGPU_VM_PAGE_PRT)
 695                 pte_flag |= AMDGPU_PTE_PRT;
 696
 697         return pte_flag;
 698 }
 699
 700 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 701                                 uint64_t *addr, uint64_t *flags)
 702 {
 703         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 704 }
 705
 706 /**
 707  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 708  *
 709  * @adev: amdgpu_device pointer
 710  * @value: true redirects VM faults to the default page
 711  */
 712 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 713                                               bool value)
 714 {
 715         u32 tmp;
 716
 717         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 718         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 719                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 720         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 721                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 722         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 723                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 724         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 725                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 726         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 727                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 728         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 729                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 730         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 731                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 732         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 733 }
 734
 735 /**
 736  * gmc_v8_0_set_prt - set PRT VM fault
 737  *
 738  * @adev: amdgpu_device pointer
 739  * @enable: enable/disable VM fault handling for PRT
 740 */
 741 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 742 {
 743         u32 tmp;
 744
 745         if (enable && !adev->gmc.prt_warning) {
 746                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 747                 adev->gmc.prt_warning = true;
 748         }
 749
 750         tmp = RREG32(mmVM_PRT_CNTL);
 751         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 752                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 753         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 754                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 755         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 756                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 757         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 758                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 759         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 760                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 761         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 762                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 763         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 764                             MASK_PDE0_FAULT, enable);
 765         WREG32(mmVM_PRT_CNTL, tmp);
 766
 767         if (enable) {
 768                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 769                 uint32_t high = adev->vm_manager.max_pfn -
 770                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 771
 772                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 773                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 774                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 775                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 776                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 777                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 778                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 779                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 780         } else {
 781                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 782                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 783                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 784                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 785                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 786                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 787                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 788                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 789         }
 790 }
 791
 792 /**
 793  * gmc_v8_0_gart_enable - gart enable
 794  *
 795  * @adev: amdgpu_device pointer
 796  *
 797  * This sets up the TLBs, programs the page tables for VMID0,
 798  * sets up the hw for VMIDs 1-15 which are allocated on
 799  * demand, and sets up the global locations for the LDS, GDS,
 800  * and GPUVM for FSA64 clients (VI).
 801  * Returns 0 for success, errors for failure.
 802  */
 803 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 804 {
 805         uint64_t table_addr;
 806         int r, i;
 807         u32 tmp, field;
 808
 809         if (adev->gart.bo == NULL) {
 810                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 811                 return -EINVAL;
 812         }
 813         r = amdgpu_gart_table_vram_pin(adev);
 814         if (r)
 815                 return r;
 816
 817         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 818
 819         /* Setup TLB control */
 820         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 821         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 822         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 823         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 824         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 825         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 826         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 827         /* Setup L2 cache */
 828         tmp = RREG32(mmVM_L2_CNTL);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 834         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 835         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 836         WREG32(mmVM_L2_CNTL, tmp);
 837         tmp = RREG32(mmVM_L2_CNTL2);
 838         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 839         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 840         WREG32(mmVM_L2_CNTL2, tmp);
 841
 842         field = adev->vm_manager.fragment_size;
 843         tmp = RREG32(mmVM_L2_CNTL3);
 844         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 845         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 846         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 847         WREG32(mmVM_L2_CNTL3, tmp);
 848         /* XXX: set to enable PTE/PDE in system memory */
 849         tmp = RREG32(mmVM_L2_CNTL4);
 850         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 851         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 860         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 861         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 862         WREG32(mmVM_L2_CNTL4, tmp);
 863         /* setup context0 */
 864         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 865         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 866         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 867         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 868                         (u32)(adev->dummy_page_addr >> 12));
 869         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 870         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 871         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 872         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 873         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 874         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 875
 876         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 877         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 878         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 879
 880         /* empty context1-15 */
 881         /* FIXME start with 4G, once using 2 level pt switch to full
 882          * vm size space
 883          */
 884         /* set vm size, must be a multiple of 4 */
 885         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 886         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 887         for (i = 1; i < 16; i++) {
 888                 if (i < 8)
 889                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 890                                table_addr >> 12);
 891                 else
 892                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 893                                table_addr >> 12);
 894         }
 895
 896         /* enable context1-15 */
 897         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 898                (u32)(adev->dummy_page_addr >> 12));
 899         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 900         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 901         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 902         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 903         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 904         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 905         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 906         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 907         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 908         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 909         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 910         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 911                             adev->vm_manager.block_size - 9);
 912         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 913         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 914                 gmc_v8_0_set_fault_enable_default(adev, false);
 915         else
 916                 gmc_v8_0_set_fault_enable_default(adev, true);
 917
 918         gmc_v8_0_flush_gpu_tlb(adev, 0, 0);
 919         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 920                  (unsigned)(adev->gmc.gart_size >> 20),
 921                  (unsigned long long)table_addr);
 922         adev->gart.ready = true;
 923         return 0;
 924 }
 925
 926 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 927 {
 928         int r;
 929
 930         if (adev->gart.bo) {
 931                 WARN(1, "R600 PCIE GART already initialized\n");
 932                 return 0;
 933         }
 934         /* Initialize common gart structure */
 935         r = amdgpu_gart_init(adev);
 936         if (r)
 937                 return r;
 938         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 939         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 940         return amdgpu_gart_table_vram_alloc(adev);
 941 }
 942
 943 /**
 944  * gmc_v8_0_gart_disable - gart disable
 945  *
 946  * @adev: amdgpu_device pointer
 947  *
 948  * This disables all VM page table (VI).
 949  */
 950 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 951 {
 952         u32 tmp;
 953
 954         /* Disable all tables */
 955         WREG32(mmVM_CONTEXT0_CNTL, 0);
 956         WREG32(mmVM_CONTEXT1_CNTL, 0);
 957         /* Setup TLB control */
 958         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 959         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 960         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 961         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 962         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 963         /* Setup L2 cache */
 964         tmp = RREG32(mmVM_L2_CNTL);
 965         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 966         WREG32(mmVM_L2_CNTL, tmp);
 967         WREG32(mmVM_L2_CNTL2, 0);
 968         amdgpu_gart_table_vram_unpin(adev);
 969 }
 970
 971 /**
 972  * gmc_v8_0_vm_decode_fault - print human readable fault info
 973  *
 974  * @adev: amdgpu_device pointer
 975  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 976  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 977  *
 978  * Print human readable fault information (VI).
 979  */
 980 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 981                                      u32 addr, u32 mc_client, unsigned pasid)
 982 {
 983         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 984         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 985                                         PROTECTIONS);
 986         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 987                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 988         u32 mc_id;
 989
 990         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 991                               MEMORY_CLIENT_ID);
 992
 993         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 994                protections, vmid, pasid, addr,
 995                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 996                              MEMORY_CLIENT_RW) ?
 997                "write" : "read", block, mc_client, mc_id);
 998 }
 999
1000 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1001 {
1002         switch (mc_seq_vram_type) {
1003         case MC_SEQ_MISC0__MT__GDDR1:
1004                 return AMDGPU_VRAM_TYPE_GDDR1;
1005         case MC_SEQ_MISC0__MT__DDR2:
1006                 return AMDGPU_VRAM_TYPE_DDR2;
1007         case MC_SEQ_MISC0__MT__GDDR3:
1008                 return AMDGPU_VRAM_TYPE_GDDR3;
1009         case MC_SEQ_MISC0__MT__GDDR4:
1010                 return AMDGPU_VRAM_TYPE_GDDR4;
1011         case MC_SEQ_MISC0__MT__GDDR5:
1012                 return AMDGPU_VRAM_TYPE_GDDR5;
1013         case MC_SEQ_MISC0__MT__HBM:
1014                 return AMDGPU_VRAM_TYPE_HBM;
1015         case MC_SEQ_MISC0__MT__DDR3:
1016                 return AMDGPU_VRAM_TYPE_DDR3;
1017         default:
1018                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1019         }
1020 }
1021
1022 static int gmc_v8_0_early_init(void *handle)
1023 {
1024         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
1026         gmc_v8_0_set_gmc_funcs(adev);
1027         gmc_v8_0_set_irq_funcs(adev);
1028
1029         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1030         adev->gmc.shared_aperture_end =
1031                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1032         adev->gmc.private_aperture_start =
1033                 adev->gmc.shared_aperture_end + 1;
1034         adev->gmc.private_aperture_end =
1035                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1036
1037         return 0;
1038 }
1039
1040 static int gmc_v8_0_late_init(void *handle)
1041 {
1042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043
1044         amdgpu_bo_late_init(adev);
1045
1046         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1047                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1048         else
1049                 return 0;
1050 }
1051
1052 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1053 {
1054         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1055         unsigned size;
1056
1057         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1058                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1059         } else {
1060                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1061                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1062                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1063                         4);
1064         }
1065         /* return 0 if the pre-OS buffer uses up most of vram */
1066         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1067                 return 0;
1068         return size;
1069 }
1070
1071 #define mmMC_SEQ_MISC0_FIJI 0xA71
1072
1073 static int gmc_v8_0_sw_init(void *handle)
1074 {
1075         int r;
1076         int dma_bits;
1077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078
1079         if (adev->flags & AMD_IS_APU) {
1080                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1081         } else {
1082                 u32 tmp;
1083
1084                 if ((adev->asic_type == CHIP_FIJI) ||
1085                     (adev->asic_type == CHIP_VEGAM))
1086                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1087                 else
1088                         tmp = RREG32(mmMC_SEQ_MISC0);
1089                 tmp &= MC_SEQ_MISC0__MT__MASK;
1090                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1091         }
1092
1093         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1094         if (r)
1095                 return r;
1096
1097         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1098         if (r)
1099                 return r;
1100
1101         /* Adjust VM size here.
1102          * Currently set to 4GB ((1 << 20) 4k pages).
1103          * Max GPUVM size for cayman and SI is 40 bits.
1104          */
1105         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1106
1107         /* Set the internal MC address mask
1108          * This is the max address of the GPU's
1109          * internal address space.
1110          */
1111         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1112
1113         /* set DMA mask + need_dma32 flags.
1114          * PCIE - can handle 40-bits.
1115          * IGP - can handle 40-bits
1116          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1117          */
1118         adev->need_dma32 = false;
1119         dma_bits = adev->need_dma32 ? 32 : 40;
1120         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1121         if (r) {
1122                 adev->need_dma32 = true;
1123                 dma_bits = 32;
1124                 pr_warn("amdgpu: No suitable DMA available\n");
1125         }
1126         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1127         if (r) {
1128                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1129                 pr_warn("amdgpu: No coherent DMA available\n");
1130         }
1131         adev->need_swiotlb = drm_need_swiotlb(dma_bits);
1132
1133         r = gmc_v8_0_init_microcode(adev);
1134         if (r) {
1135                 DRM_ERROR("Failed to load mc firmware!\n");
1136                 return r;
1137         }
1138
1139         r = gmc_v8_0_mc_init(adev);
1140         if (r)
1141                 return r;
1142
1143         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1144
1145         /* Memory manager */
1146         r = amdgpu_bo_init(adev);
1147         if (r)
1148                 return r;
1149
1150         r = gmc_v8_0_gart_init(adev);
1151         if (r)
1152                 return r;
1153
1154         /*
1155          * number of VMs
1156          * VMID 0 is reserved for System
1157          * amdgpu graphics/compute will use VMIDs 1-7
1158          * amdkfd will use VMIDs 8-15
1159          */
1160         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1161         amdgpu_vm_manager_init(adev);
1162
1163         /* base offset of vram pages */
1164         if (adev->flags & AMD_IS_APU) {
1165                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1166
1167                 tmp <<= 22;
1168                 adev->vm_manager.vram_base_offset = tmp;
1169         } else {
1170                 adev->vm_manager.vram_base_offset = 0;
1171         }
1172
1173         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1174                                         GFP_KERNEL);
1175         if (!adev->gmc.vm_fault_info)
1176                 return -ENOMEM;
1177         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1178
1179         return 0;
1180 }
1181
1182 static int gmc_v8_0_sw_fini(void *handle)
1183 {
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         amdgpu_gem_force_release(adev);
1187         amdgpu_vm_manager_fini(adev);
1188         kfree(adev->gmc.vm_fault_info);
1189         amdgpu_gart_table_vram_free(adev);
1190         amdgpu_bo_fini(adev);
1191         amdgpu_gart_fini(adev);
1192         release_firmware(adev->gmc.fw);
1193         adev->gmc.fw = NULL;
1194
1195         return 0;
1196 }
1197
1198 static int gmc_v8_0_hw_init(void *handle)
1199 {
1200         int r;
1201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1202
1203         gmc_v8_0_init_golden_registers(adev);
1204
1205         gmc_v8_0_mc_program(adev);
1206
1207         if (adev->asic_type == CHIP_TONGA) {
1208                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1209                 if (r) {
1210                         DRM_ERROR("Failed to load MC firmware!\n");
1211                         return r;
1212                 }
1213         } else if (adev->asic_type == CHIP_POLARIS11 ||
1214                         adev->asic_type == CHIP_POLARIS10 ||
1215                         adev->asic_type == CHIP_POLARIS12) {
1216                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1217                 if (r) {
1218                         DRM_ERROR("Failed to load MC firmware!\n");
1219                         return r;
1220                 }
1221         }
1222
1223         r = gmc_v8_0_gart_enable(adev);
1224         if (r)
1225                 return r;
1226
1227         return r;
1228 }
1229
1230 static int gmc_v8_0_hw_fini(void *handle)
1231 {
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233
1234         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1235         gmc_v8_0_gart_disable(adev);
1236
1237         return 0;
1238 }
1239
1240 static int gmc_v8_0_suspend(void *handle)
1241 {
1242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243
1244         gmc_v8_0_hw_fini(adev);
1245
1246         return 0;
1247 }
1248
1249 static int gmc_v8_0_resume(void *handle)
1250 {
1251         int r;
1252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1253
1254         r = gmc_v8_0_hw_init(adev);
1255         if (r)
1256                 return r;
1257
1258         amdgpu_vmid_reset_all(adev);
1259
1260         return 0;
1261 }
1262
1263 static bool gmc_v8_0_is_idle(void *handle)
1264 {
1265         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266         u32 tmp = RREG32(mmSRBM_STATUS);
1267
1268         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1269                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1270                 return false;
1271
1272         return true;
1273 }
1274
1275 static int gmc_v8_0_wait_for_idle(void *handle)
1276 {
1277         unsigned i;
1278         u32 tmp;
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281         for (i = 0; i < adev->usec_timeout; i++) {
1282                 /* read MC_STATUS */
1283                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1284                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1285                                                SRBM_STATUS__MCC_BUSY_MASK |
1286                                                SRBM_STATUS__MCD_BUSY_MASK |
1287                                                SRBM_STATUS__VMC_BUSY_MASK |
1288                                                SRBM_STATUS__VMC1_BUSY_MASK);
1289                 if (!tmp)
1290                         return 0;
1291                 udelay(1);
1292         }
1293         return -ETIMEDOUT;
1294
1295 }
1296
1297 static bool gmc_v8_0_check_soft_reset(void *handle)
1298 {
1299         u32 srbm_soft_reset = 0;
1300         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301         u32 tmp = RREG32(mmSRBM_STATUS);
1302
1303         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1304                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1305                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1306
1307         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1308                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1309                 if (!(adev->flags & AMD_IS_APU))
1310                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1311                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1312         }
1313         if (srbm_soft_reset) {
1314                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1315                 return true;
1316         } else {
1317                 adev->gmc.srbm_soft_reset = 0;
1318                 return false;
1319         }
1320 }
1321
1322 static int gmc_v8_0_pre_soft_reset(void *handle)
1323 {
1324         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326         if (!adev->gmc.srbm_soft_reset)
1327                 return 0;
1328
1329         gmc_v8_0_mc_stop(adev);
1330         if (gmc_v8_0_wait_for_idle(adev)) {
1331                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1332         }
1333
1334         return 0;
1335 }
1336
1337 static int gmc_v8_0_soft_reset(void *handle)
1338 {
1339         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340         u32 srbm_soft_reset;
1341
1342         if (!adev->gmc.srbm_soft_reset)
1343                 return 0;
1344         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1345
1346         if (srbm_soft_reset) {
1347                 u32 tmp;
1348
1349                 tmp = RREG32(mmSRBM_SOFT_RESET);
1350                 tmp |= srbm_soft_reset;
1351                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1352                 WREG32(mmSRBM_SOFT_RESET, tmp);
1353                 tmp = RREG32(mmSRBM_SOFT_RESET);
1354
1355                 udelay(50);
1356
1357                 tmp &= ~srbm_soft_reset;
1358                 WREG32(mmSRBM_SOFT_RESET, tmp);
1359                 tmp = RREG32(mmSRBM_SOFT_RESET);
1360
1361                 /* Wait a little for things to settle down */
1362                 udelay(50);
1363         }
1364
1365         return 0;
1366 }
1367
1368 static int gmc_v8_0_post_soft_reset(void *handle)
1369 {
1370         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371
1372         if (!adev->gmc.srbm_soft_reset)
1373                 return 0;
1374
1375         gmc_v8_0_mc_resume(adev);
1376         return 0;
1377 }
1378
1379 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1380                                              struct amdgpu_irq_src *src,
1381                                              unsigned type,
1382                                              enum amdgpu_interrupt_state state)
1383 {
1384         u32 tmp;
1385         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1386                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1387                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1388                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1389                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1390                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1391                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1392
1393         switch (state) {
1394         case AMDGPU_IRQ_STATE_DISABLE:
1395                 /* system context */
1396                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1397                 tmp &= ~bits;
1398                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1399                 /* VMs */
1400                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1401                 tmp &= ~bits;
1402                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1403                 break;
1404         case AMDGPU_IRQ_STATE_ENABLE:
1405                 /* system context */
1406                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1407                 tmp |= bits;
1408                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1409                 /* VMs */
1410                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1411                 tmp |= bits;
1412                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1413                 break;
1414         default:
1415                 break;
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1422                                       struct amdgpu_irq_src *source,
1423                                       struct amdgpu_iv_entry *entry)
1424 {
1425         u32 addr, status, mc_client, vmid;
1426
1427         if (amdgpu_sriov_vf(adev)) {
1428                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1429                         entry->src_id, entry->src_data[0]);
1430                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1431                 return 0;
1432         }
1433
1434         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1435         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1436         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1437         /* reset addr and status */
1438         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1439
1440         if (!addr && !status)
1441                 return 0;
1442
1443         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1444                 gmc_v8_0_set_fault_enable_default(adev, false);
1445
1446         if (printk_ratelimit()) {
1447                 struct amdgpu_task_info task_info;
1448
1449                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1450                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1451
1452                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1453                         entry->src_id, entry->src_data[0], task_info.process_name,
1454                         task_info.tgid, task_info.task_name, task_info.pid);
1455                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1456                         addr);
1457                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1458                         status);
1459                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1460                                          entry->pasid);
1461         }
1462
1463         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1464                              VMID);
1465         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1466                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1467                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1468                 u32 protections = REG_GET_FIELD(status,
1469                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1470                                         PROTECTIONS);
1471
1472                 info->vmid = vmid;
1473                 info->mc_id = REG_GET_FIELD(status,
1474                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1475                                             MEMORY_CLIENT_ID);
1476                 info->status = status;
1477                 info->page_addr = addr;
1478                 info->prot_valid = protections & 0x7 ? true : false;
1479                 info->prot_read = protections & 0x8 ? true : false;
1480                 info->prot_write = protections & 0x10 ? true : false;
1481                 info->prot_exec = protections & 0x20 ? true : false;
1482                 mb();
1483                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1484         }
1485
1486         return 0;
1487 }
1488
1489 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1490                                                      bool enable)
1491 {
1492         uint32_t data;
1493
1494         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1495                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1496                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1497                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1498
1499                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1500                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1501                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1502
1503                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1504                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1505                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1506
1507                 data = RREG32(mmMC_XPB_CLK_GAT);
1508                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1509                 WREG32(mmMC_XPB_CLK_GAT, data);
1510
1511                 data = RREG32(mmATC_MISC_CG);
1512                 data |= ATC_MISC_CG__ENABLE_MASK;
1513                 WREG32(mmATC_MISC_CG, data);
1514
1515                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1516                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1517                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1518
1519                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1520                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1521                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1522
1523                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1524                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1525                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1526
1527                 data = RREG32(mmVM_L2_CG);
1528                 data |= VM_L2_CG__ENABLE_MASK;
1529                 WREG32(mmVM_L2_CG, data);
1530         } else {
1531                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1532                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1533                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1534
1535                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1536                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1537                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1538
1539                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1540                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1541                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1542
1543                 data = RREG32(mmMC_XPB_CLK_GAT);
1544                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1545                 WREG32(mmMC_XPB_CLK_GAT, data);
1546
1547                 data = RREG32(mmATC_MISC_CG);
1548                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1549                 WREG32(mmATC_MISC_CG, data);
1550
1551                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1552                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1553                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1554
1555                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1556                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1557                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1558
1559                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1560                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1561                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1562
1563                 data = RREG32(mmVM_L2_CG);
1564                 data &= ~VM_L2_CG__ENABLE_MASK;
1565                 WREG32(mmVM_L2_CG, data);
1566         }
1567 }
1568
1569 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1570                                        bool enable)
1571 {
1572         uint32_t data;
1573
1574         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1575                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1576                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1577                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1578
1579                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1580                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1581                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1582
1583                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1584                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1585                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1586
1587                 data = RREG32(mmMC_XPB_CLK_GAT);
1588                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1589                 WREG32(mmMC_XPB_CLK_GAT, data);
1590
1591                 data = RREG32(mmATC_MISC_CG);
1592                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1593                 WREG32(mmATC_MISC_CG, data);
1594
1595                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1596                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1597                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1598
1599                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1600                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1601                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1602
1603                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1604                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1605                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1606
1607                 data = RREG32(mmVM_L2_CG);
1608                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1609                 WREG32(mmVM_L2_CG, data);
1610         } else {
1611                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1612                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1613                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1614
1615                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1616                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1617                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1618
1619                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1620                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1621                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1622
1623                 data = RREG32(mmMC_XPB_CLK_GAT);
1624                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1625                 WREG32(mmMC_XPB_CLK_GAT, data);
1626
1627                 data = RREG32(mmATC_MISC_CG);
1628                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1629                 WREG32(mmATC_MISC_CG, data);
1630
1631                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1632                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1633                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1634
1635                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1636                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1637                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1638
1639                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1640                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1641                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1642
1643                 data = RREG32(mmVM_L2_CG);
1644                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1645                 WREG32(mmVM_L2_CG, data);
1646         }
1647 }
1648
1649 static int gmc_v8_0_set_clockgating_state(void *handle,
1650                                           enum amd_clockgating_state state)
1651 {
1652         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1653
1654         if (amdgpu_sriov_vf(adev))
1655                 return 0;
1656
1657         switch (adev->asic_type) {
1658         case CHIP_FIJI:
1659                 fiji_update_mc_medium_grain_clock_gating(adev,
1660                                 state == AMD_CG_STATE_GATE);
1661                 fiji_update_mc_light_sleep(adev,
1662                                 state == AMD_CG_STATE_GATE);
1663                 break;
1664         default:
1665                 break;
1666         }
1667         return 0;
1668 }
1669
1670 static int gmc_v8_0_set_powergating_state(void *handle,
1671                                           enum amd_powergating_state state)
1672 {
1673         return 0;
1674 }
1675
1676 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1677 {
1678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1679         int data;
1680
1681         if (amdgpu_sriov_vf(adev))
1682                 *flags = 0;
1683
1684         /* AMD_CG_SUPPORT_MC_MGCG */
1685         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1686         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1687                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1688
1689         /* AMD_CG_SUPPORT_MC_LS */
1690         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1691                 *flags |= AMD_CG_SUPPORT_MC_LS;
1692 }
1693
1694 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1695         .name = "gmc_v8_0",
1696         .early_init = gmc_v8_0_early_init,
1697         .late_init = gmc_v8_0_late_init,
1698         .sw_init = gmc_v8_0_sw_init,
1699         .sw_fini = gmc_v8_0_sw_fini,
1700         .hw_init = gmc_v8_0_hw_init,
1701         .hw_fini = gmc_v8_0_hw_fini,
1702         .suspend = gmc_v8_0_suspend,
1703         .resume = gmc_v8_0_resume,
1704         .is_idle = gmc_v8_0_is_idle,
1705         .wait_for_idle = gmc_v8_0_wait_for_idle,
1706         .check_soft_reset = gmc_v8_0_check_soft_reset,
1707         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1708         .soft_reset = gmc_v8_0_soft_reset,
1709         .post_soft_reset = gmc_v8_0_post_soft_reset,
1710         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1711         .set_powergating_state = gmc_v8_0_set_powergating_state,
1712         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1713 };
1714
1715 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1716         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1717         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1718         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1719         .set_prt = gmc_v8_0_set_prt,
1720         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1721         .get_vm_pde = gmc_v8_0_get_vm_pde
1722 };
1723
1724 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1725         .set = gmc_v8_0_vm_fault_interrupt_state,
1726         .process = gmc_v8_0_process_interrupt,
1727 };
1728
1729 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1730 {
1731         adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1732 }
1733
1734 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1735 {
1736         adev->gmc.vm_fault.num_types = 1;
1737         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1738 }
1739
1740 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1741 {
1742         .type = AMD_IP_BLOCK_TYPE_GMC,
1743         .major = 8,
1744         .minor = 0,
1745         .rev = 0,
1746         .funcs = &gmc_v8_0_ip_funcs,
1747 };
1748
1749 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1750 {
1751         .type = AMD_IP_BLOCK_TYPE_GMC,
1752         .major = 8,
1753         .minor = 1,
1754         .rev = 0,
1755         .funcs = &gmc_v8_0_ip_funcs,
1756 };
1757
1758 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1759 {
1760         .type = AMD_IP_BLOCK_TYPE_GMC,
1761         .major = 8,
1762         .minor = 5,
1763         .rev = 0,
1764         .funcs = &gmc_v8_0_ip_funcs,
1765 };