drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "gmc_v6_0.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "bif/bif_3_0_d.h"
  35 #include "bif/bif_3_0_sh_mask.h"
  36 #include "oss/oss_1_0_d.h"
  37 #include "oss/oss_1_0_sh_mask.h"
  38 #include "gmc/gmc_6_0_d.h"
  39 #include "gmc/gmc_6_0_sh_mask.h"
  40 #include "dce/dce_6_0_d.h"
  41 #include "dce/dce_6_0_sh_mask.h"
  42 #include "si_enums.h"
  43
  44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
  45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  46 static int gmc_v6_0_wait_for_idle(void *handle);
  47
  48 /*(DEBLOBBED)*/
  49
  50 #define MC_SEQ_MISC0__MT__MASK   0xf0000000
  51 #define MC_SEQ_MISC0__MT__GDDR1  0x10000000
  52 #define MC_SEQ_MISC0__MT__DDR2   0x20000000
  53 #define MC_SEQ_MISC0__MT__GDDR3  0x30000000
  54 #define MC_SEQ_MISC0__MT__GDDR4  0x40000000
  55 #define MC_SEQ_MISC0__MT__GDDR5  0x50000000
  56 #define MC_SEQ_MISC0__MT__HBM    0x60000000
  57 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
  58
  59
  60 static const u32 crtc_offsets[6] =
  61 {
  62         SI_CRTC0_REGISTER_OFFSET,
  63         SI_CRTC1_REGISTER_OFFSET,
  64         SI_CRTC2_REGISTER_OFFSET,
  65         SI_CRTC3_REGISTER_OFFSET,
  66         SI_CRTC4_REGISTER_OFFSET,
  67         SI_CRTC5_REGISTER_OFFSET
  68 };
  69
  70 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
  71 {
  72         u32 blackout;
  73
  74         gmc_v6_0_wait_for_idle((void *)adev);
  75
  76         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  77         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  78                 /* Block CPU access */
  79                 WREG32(mmBIF_FB_EN, 0);
  80                 /* blackout the MC */
  81                 blackout = REG_SET_FIELD(blackout,
  82                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  83                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
  84         }
  85         /* wait for the MC to settle */
  86         udelay(100);
  87
  88 }
  89
  90 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
  91 {
  92         u32 tmp;
  93
  94         /* unblackout the MC */
  95         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  96         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
  97         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
  98         /* allow CPU access */
  99         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 100         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 101         WREG32(mmBIF_FB_EN, tmp);
 102 }
 103
 104 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
 105 {
 106         const char *chip_name;
 107         char fw_name[30];
 108         int err;
 109         bool is_58_fw = false;
 110
 111         DRM_DEBUG("\n");
 112
 113         switch (adev->asic_type) {
 114         case CHIP_TAHITI:
 115                 chip_name = "tahiti";
 116                 break;
 117         case CHIP_PITCAIRN:
 118                 chip_name = "pitcairn";
 119                 break;
 120         case CHIP_VERDE:
 121                 chip_name = "verde";
 122                 break;
 123         case CHIP_OLAND:
 124                 chip_name = "oland";
 125                 break;
 126         case CHIP_HAINAN:
 127                 chip_name = "hainan";
 128                 break;
 129         default: BUG();
 130         }
 131
 132         /* this memory configuration requires special firmware */
 133         if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
 134                 is_58_fw = true;
 135
 136         if (is_58_fw)
 137                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/");
 138         else
 139                 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 140         err = reject_firmware(&adev->gmc.fw, fw_name, adev->dev);
 141         if (err)
 142                 goto out;
 143
 144         err = amdgpu_ucode_validate(adev->gmc.fw);
 145
 146 out:
 147         if (err) {
 148                 dev_err(adev->dev,
 149                        "si_mc: Failed to load firmware \"%s\"\n",
 150                        fw_name);
 151                 release_firmware(adev->gmc.fw);
 152                 adev->gmc.fw = NULL;
 153         }
 154         return err;
 155 }
 156
 157 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
 158 {
 159         const __le32 *new_fw_data = NULL;
 160         u32 running;
 161         const __le32 *new_io_mc_regs = NULL;
 162         int i, regs_size, ucode_size;
 163         const struct mc_firmware_header_v1_0 *hdr;
 164
 165         if (!adev->gmc.fw)
 166                 return -EINVAL;
 167
 168         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 169
 170         amdgpu_ucode_print_mc_hdr(&hdr->header);
 171
 172         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 173         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 174         new_io_mc_regs = (const __le32 *)
 175                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 176         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 177         new_fw_data = (const __le32 *)
 178                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 179
 180         running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
 181
 182         if (running == 0) {
 183
 184                 /* reset the engine and set to writable */
 185                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 186                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 187
 188                 /* load mc io regs */
 189                 for (i = 0; i < regs_size; i++) {
 190                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
 191                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
 192                 }
 193                 /* load the MC ucode */
 194                 for (i = 0; i < ucode_size; i++) {
 195                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
 196                 }
 197
 198                 /* put the engine back into the active state */
 199                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 200                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 201                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 202
 203                 /* wait for training to complete */
 204                 for (i = 0; i < adev->usec_timeout; i++) {
 205                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
 206                                 break;
 207                         udelay(1);
 208                 }
 209                 for (i = 0; i < adev->usec_timeout; i++) {
 210                         if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
 211                                 break;
 212                         udelay(1);
 213                 }
 214
 215         }
 216
 217         return 0;
 218 }
 219
 220 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
 221                                        struct amdgpu_gmc *mc)
 222 {
 223         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 224         base <<= 24;
 225
 226         amdgpu_gmc_vram_location(adev, mc, base);
 227         amdgpu_gmc_gart_location(adev, mc);
 228 }
 229
 230 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
 231 {
 232         int i, j;
 233
 234         /* Initialize HDP */
 235         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 236                 WREG32((0xb05 + j), 0x00000000);
 237                 WREG32((0xb06 + j), 0x00000000);
 238                 WREG32((0xb07 + j), 0x00000000);
 239                 WREG32((0xb08 + j), 0x00000000);
 240                 WREG32((0xb09 + j), 0x00000000);
 241         }
 242         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 243
 244         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 245                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 246         }
 247
 248         if (adev->mode_info.num_crtc) {
 249                 u32 tmp;
 250
 251                 /* Lockout access through VGA aperture*/
 252                 tmp = RREG32(mmVGA_HDP_CONTROL);
 253                 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
 254                 WREG32(mmVGA_HDP_CONTROL, tmp);
 255
 256                 /* disable VGA render */
 257                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 258                 tmp &= ~VGA_VSTATUS_CNTL;
 259                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 260         }
 261         /* Update configuration */
 262         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 263                adev->gmc.vram_start >> 12);
 264         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 265                adev->gmc.vram_end >> 12);
 266         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 267                adev->vram_scratch.gpu_addr >> 12);
 268         WREG32(mmMC_VM_AGP_BASE, 0);
 269         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 270         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 271
 272         if (gmc_v6_0_wait_for_idle((void *)adev)) {
 273                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 274         }
 275 }
 276
 277 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 278 {
 279
 280         u32 tmp;
 281         int chansize, numchan;
 282         int r;
 283
 284         tmp = RREG32(mmMC_ARB_RAMCFG);
 285         if (tmp & (1 << 11)) {
 286                 chansize = 16;
 287         } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
 288                 chansize = 64;
 289         } else {
 290                 chansize = 32;
 291         }
 292         tmp = RREG32(mmMC_SHARED_CHMAP);
 293         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 294         case 0:
 295         default:
 296                 numchan = 1;
 297                 break;
 298         case 1:
 299                 numchan = 2;
 300                 break;
 301         case 2:
 302                 numchan = 4;
 303                 break;
 304         case 3:
 305                 numchan = 8;
 306                 break;
 307         case 4:
 308                 numchan = 3;
 309                 break;
 310         case 5:
 311                 numchan = 6;
 312                 break;
 313         case 6:
 314                 numchan = 10;
 315                 break;
 316         case 7:
 317                 numchan = 12;
 318                 break;
 319         case 8:
 320                 numchan = 16;
 321                 break;
 322         }
 323         adev->gmc.vram_width = numchan * chansize;
 324         /* size in MB on si */
 325         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 326         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 327
 328         if (!(adev->flags & AMD_IS_APU)) {
 329                 r = amdgpu_device_resize_fb_bar(adev);
 330                 if (r)
 331                         return r;
 332         }
 333         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 334         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 335         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 336
 337         /* set the gart size */
 338         if (amdgpu_gart_size == -1) {
 339                 switch (adev->asic_type) {
 340                 case CHIP_HAINAN:    /* no MM engines */
 341                 default:
 342                         adev->gmc.gart_size = 256ULL << 20;
 343                         break;
 344                 case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
 345                 case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
 346                 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
 347                 case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
 348                         adev->gmc.gart_size = 1024ULL << 20;
 349                         break;
 350                 }
 351         } else {
 352                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 353         }
 354
 355         gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
 356
 357         return 0;
 358 }
 359
 360 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev,
 361                                 uint32_t vmid, uint32_t flush_type)
 362 {
 363         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 364 }
 365
 366 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 367                                             unsigned vmid, uint64_t pd_addr)
 368 {
 369         uint32_t reg;
 370
 371         /* write new base address */
 372         if (vmid < 8)
 373                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 374         else
 375                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
 376         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 377
 378         /* bits 0-15 are the VM contexts0-15 */
 379         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 380
 381         return pd_addr;
 382 }
 383
 384 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
 385                                           uint32_t flags)
 386 {
 387         uint64_t pte_flag = 0;
 388
 389         if (flags & AMDGPU_VM_PAGE_READABLE)
 390                 pte_flag |= AMDGPU_PTE_READABLE;
 391         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 392                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 393         if (flags & AMDGPU_VM_PAGE_PRT)
 394                 pte_flag |= AMDGPU_PTE_PRT;
 395
 396         return pte_flag;
 397 }
 398
 399 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
 400                                 uint64_t *addr, uint64_t *flags)
 401 {
 402         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 403 }
 404
 405 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
 406                                               bool value)
 407 {
 408         u32 tmp;
 409
 410         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 411         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 412                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 413         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 414                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 415         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 416                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 417         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 418                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 419         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 420                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 421         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 422                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 423         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 424 }
 425
 426  /**
 427    + * gmc_v8_0_set_prt - set PRT VM fault
 428    + *
 429    + * @adev: amdgpu_device pointer
 430    + * @enable: enable/disable VM fault handling for PRT
 431    +*/
 432 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 433 {
 434         u32 tmp;
 435
 436         if (enable && !adev->gmc.prt_warning) {
 437                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 438                 adev->gmc.prt_warning = true;
 439         }
 440
 441         tmp = RREG32(mmVM_PRT_CNTL);
 442         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 443                             CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 444                             enable);
 445         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 446                             TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
 447                             enable);
 448         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 449                             L2_CACHE_STORE_INVALID_ENTRIES,
 450                             enable);
 451         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 452                             L1_TLB_STORE_INVALID_ENTRIES,
 453                             enable);
 454         WREG32(mmVM_PRT_CNTL, tmp);
 455
 456         if (enable) {
 457                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 458                 uint32_t high = adev->vm_manager.max_pfn -
 459                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 460
 461                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 462                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 463                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 464                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 465                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 466                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 467                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 468                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 469         } else {
 470                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 471                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 472                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 473                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 474                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 475                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 476                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 477                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 478         }
 479 }
 480
 481 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 482 {
 483         uint64_t table_addr;
 484         int r, i;
 485         u32 field;
 486
 487         if (adev->gart.bo == NULL) {
 488                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 489                 return -EINVAL;
 490         }
 491         r = amdgpu_gart_table_vram_pin(adev);
 492         if (r)
 493                 return r;
 494
 495         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 496
 497         /* Setup TLB control */
 498         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 499                (0xA << 7) |
 500                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
 501                MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
 502                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 503                MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
 504                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 505         /* Setup L2 cache */
 506         WREG32(mmVM_L2_CNTL,
 507                VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
 508                VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
 509                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 510                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 511                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 512                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 513         WREG32(mmVM_L2_CNTL2,
 514                VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
 515                VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
 516
 517         field = adev->vm_manager.fragment_size;
 518         WREG32(mmVM_L2_CNTL3,
 519                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 520                (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
 521                (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 522         /* setup context0 */
 523         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 524         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 525         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 526         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 527                         (u32)(adev->dummy_page_addr >> 12));
 528         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 529         WREG32(mmVM_CONTEXT0_CNTL,
 530                VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
 531                (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 532                VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
 533
 534         WREG32(0x575, 0);
 535         WREG32(0x576, 0);
 536         WREG32(0x577, 0);
 537
 538         /* empty context1-15 */
 539         /* set vm size, must be a multiple of 4 */
 540         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 541         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 542         /* Assign the pt base to something valid for now; the pts used for
 543          * the VMs are determined by the application and setup and assigned
 544          * on the fly in the vm part of radeon_gart.c
 545          */
 546         for (i = 1; i < 16; i++) {
 547                 if (i < 8)
 548                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 549                                table_addr >> 12);
 550                 else
 551                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 552                                table_addr >> 12);
 553         }
 554
 555         /* enable context1-15 */
 556         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 557                (u32)(adev->dummy_page_addr >> 12));
 558         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 559         WREG32(mmVM_CONTEXT1_CNTL,
 560                VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
 561                (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
 562                ((adev->vm_manager.block_size - 9)
 563                << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
 564         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 565                 gmc_v6_0_set_fault_enable_default(adev, false);
 566         else
 567                 gmc_v6_0_set_fault_enable_default(adev, true);
 568
 569         gmc_v6_0_flush_gpu_tlb(adev, 0, 0);
 570         dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 571                  (unsigned)(adev->gmc.gart_size >> 20),
 572                  (unsigned long long)table_addr);
 573         adev->gart.ready = true;
 574         return 0;
 575 }
 576
 577 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 578 {
 579         int r;
 580
 581         if (adev->gart.bo) {
 582                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 583                 return 0;
 584         }
 585         r = amdgpu_gart_init(adev);
 586         if (r)
 587                 return r;
 588         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 589         adev->gart.gart_pte_flags = 0;
 590         return amdgpu_gart_table_vram_alloc(adev);
 591 }
 592
 593 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
 594 {
 595         /*unsigned i;
 596
 597         for (i = 1; i < 16; ++i) {
 598                 uint32_t reg;
 599                 if (i < 8)
 600                         reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
 601                 else
 602                         reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
 603                 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
 604         }*/
 605
 606         /* Disable all tables */
 607         WREG32(mmVM_CONTEXT0_CNTL, 0);
 608         WREG32(mmVM_CONTEXT1_CNTL, 0);
 609         /* Setup TLB control */
 610         WREG32(mmMC_VM_MX_L1_TLB_CNTL,
 611                MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
 612                (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
 613         /* Setup L2 cache */
 614         WREG32(mmVM_L2_CNTL,
 615                VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 616                VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
 617                (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
 618                (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
 619         WREG32(mmVM_L2_CNTL2, 0);
 620         WREG32(mmVM_L2_CNTL3,
 621                VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
 622                (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
 623         amdgpu_gart_table_vram_unpin(adev);
 624 }
 625
 626 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
 627                                      u32 status, u32 addr, u32 mc_client)
 628 {
 629         u32 mc_id;
 630         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 631         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 632                                         PROTECTIONS);
 633         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 634                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 635
 636         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 637                               MEMORY_CLIENT_ID);
 638
 639         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 640                protections, vmid, addr,
 641                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 642                              MEMORY_CLIENT_RW) ?
 643                "write" : "read", block, mc_client, mc_id);
 644 }
 645
 646 /*
 647 static const u32 mc_cg_registers[] = {
 648         MC_HUB_MISC_HUB_CG,
 649         MC_HUB_MISC_SIP_CG,
 650         MC_HUB_MISC_VM_CG,
 651         MC_XPB_CLK_GAT,
 652         ATC_MISC_CG,
 653         MC_CITF_MISC_WR_CG,
 654         MC_CITF_MISC_RD_CG,
 655         MC_CITF_MISC_VM_CG,
 656         VM_L2_CG,
 657 };
 658
 659 static const u32 mc_cg_ls_en[] = {
 660         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 661         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 662         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 663         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 664         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 665         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 666         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 667         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 668         VM_L2_CG__MEM_LS_ENABLE_MASK,
 669 };
 670
 671 static const u32 mc_cg_en[] = {
 672         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 673         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 674         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 675         MC_XPB_CLK_GAT__ENABLE_MASK,
 676         ATC_MISC_CG__ENABLE_MASK,
 677         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 678         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 679         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 680         VM_L2_CG__ENABLE_MASK,
 681 };
 682
 683 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
 684                                   bool enable)
 685 {
 686         int i;
 687         u32 orig, data;
 688
 689         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 690                 orig = data = RREG32(mc_cg_registers[i]);
 691                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
 692                         data |= mc_cg_ls_en[i];
 693                 else
 694                         data &= ~mc_cg_ls_en[i];
 695                 if (data != orig)
 696                         WREG32(mc_cg_registers[i], data);
 697         }
 698 }
 699
 700 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
 701                                     bool enable)
 702 {
 703         int i;
 704         u32 orig, data;
 705
 706         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 707                 orig = data = RREG32(mc_cg_registers[i]);
 708                 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
 709                         data |= mc_cg_en[i];
 710                 else
 711                         data &= ~mc_cg_en[i];
 712                 if (data != orig)
 713                         WREG32(mc_cg_registers[i], data);
 714         }
 715 }
 716
 717 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
 718                                      bool enable)
 719 {
 720         u32 orig, data;
 721
 722         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 723
 724         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
 725                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 726                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 727                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 728                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 729         } else {
 730                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 731                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 732                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 733                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 734         }
 735
 736         if (orig != data)
 737                 WREG32_PCIE(ixPCIE_CNTL2, data);
 738 }
 739
 740 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 741                                      bool enable)
 742 {
 743         u32 orig, data;
 744
 745         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 746
 747         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
 748                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 749         else
 750                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 751
 752         if (orig != data)
 753                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 754 }
 755
 756 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
 757                                    bool enable)
 758 {
 759         u32 orig, data;
 760
 761         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 762
 763         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
 764                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 765         else
 766                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 767
 768         if (orig != data)
 769                 WREG32(mmHDP_MEM_POWER_LS, data);
 770 }
 771 */
 772
 773 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
 774 {
 775         switch (mc_seq_vram_type) {
 776         case MC_SEQ_MISC0__MT__GDDR1:
 777                 return AMDGPU_VRAM_TYPE_GDDR1;
 778         case MC_SEQ_MISC0__MT__DDR2:
 779                 return AMDGPU_VRAM_TYPE_DDR2;
 780         case MC_SEQ_MISC0__MT__GDDR3:
 781                 return AMDGPU_VRAM_TYPE_GDDR3;
 782         case MC_SEQ_MISC0__MT__GDDR4:
 783                 return AMDGPU_VRAM_TYPE_GDDR4;
 784         case MC_SEQ_MISC0__MT__GDDR5:
 785                 return AMDGPU_VRAM_TYPE_GDDR5;
 786         case MC_SEQ_MISC0__MT__DDR3:
 787                 return AMDGPU_VRAM_TYPE_DDR3;
 788         default:
 789                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 790         }
 791 }
 792
 793 static int gmc_v6_0_early_init(void *handle)
 794 {
 795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 796
 797         gmc_v6_0_set_gmc_funcs(adev);
 798         gmc_v6_0_set_irq_funcs(adev);
 799
 800         return 0;
 801 }
 802
 803 static int gmc_v6_0_late_init(void *handle)
 804 {
 805         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 806
 807         amdgpu_bo_late_init(adev);
 808
 809         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 810                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 811         else
 812                 return 0;
 813 }
 814
 815 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
 816 {
 817         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 818         unsigned size;
 819
 820         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 821                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 822         } else {
 823                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 824                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 825                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 826                         4);
 827         }
 828         /* return 0 if the pre-OS buffer uses up most of vram */
 829         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
 830                 return 0;
 831         return size;
 832 }
 833
 834 static int gmc_v6_0_sw_init(void *handle)
 835 {
 836         int r;
 837         int dma_bits;
 838         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 839
 840         if (adev->flags & AMD_IS_APU) {
 841                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 842         } else {
 843                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 844                 tmp &= MC_SEQ_MISC0__MT__MASK;
 845                 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
 846         }
 847
 848         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
 849         if (r)
 850                 return r;
 851
 852         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
 853         if (r)
 854                 return r;
 855
 856         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 857
 858         adev->gmc.mc_mask = 0xffffffffffULL;
 859
 860         adev->need_dma32 = false;
 861         dma_bits = adev->need_dma32 ? 32 : 40;
 862         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 863         if (r) {
 864                 adev->need_dma32 = true;
 865                 dma_bits = 32;
 866                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
 867         }
 868         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 869         if (r) {
 870                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 871                 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
 872         }
 873         adev->need_swiotlb = drm_need_swiotlb(dma_bits);
 874
 875         r = gmc_v6_0_init_microcode(adev);
 876         if (r) {
 877                 dev_err(adev->dev, "Failed to load mc firmware!\n");
 878                 return r;
 879         }
 880
 881         r = gmc_v6_0_mc_init(adev);
 882         if (r)
 883                 return r;
 884
 885         adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
 886
 887         r = amdgpu_bo_init(adev);
 888         if (r)
 889                 return r;
 890
 891         r = gmc_v6_0_gart_init(adev);
 892         if (r)
 893                 return r;
 894
 895         /*
 896          * number of VMs
 897          * VMID 0 is reserved for System
 898          * amdgpu graphics/compute will use VMIDs 1-7
 899          * amdkfd will use VMIDs 8-15
 900          */
 901         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
 902         amdgpu_vm_manager_init(adev);
 903
 904         /* base offset of vram pages */
 905         if (adev->flags & AMD_IS_APU) {
 906                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 907
 908                 tmp <<= 22;
 909                 adev->vm_manager.vram_base_offset = tmp;
 910         } else {
 911                 adev->vm_manager.vram_base_offset = 0;
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int gmc_v6_0_sw_fini(void *handle)
 918 {
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         amdgpu_gem_force_release(adev);
 922         amdgpu_vm_manager_fini(adev);
 923         amdgpu_gart_table_vram_free(adev);
 924         amdgpu_bo_fini(adev);
 925         amdgpu_gart_fini(adev);
 926         release_firmware(adev->gmc.fw);
 927         adev->gmc.fw = NULL;
 928
 929         return 0;
 930 }
 931
 932 static int gmc_v6_0_hw_init(void *handle)
 933 {
 934         int r;
 935         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 936
 937         gmc_v6_0_mc_program(adev);
 938
 939         if (!(adev->flags & AMD_IS_APU)) {
 940                 r = gmc_v6_0_mc_load_microcode(adev);
 941                 if (r) {
 942                         dev_err(adev->dev, "Failed to load MC firmware!\n");
 943                         return r;
 944                 }
 945         }
 946
 947         r = gmc_v6_0_gart_enable(adev);
 948         if (r)
 949                 return r;
 950
 951         return r;
 952 }
 953
 954 static int gmc_v6_0_hw_fini(void *handle)
 955 {
 956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 957
 958         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 959         gmc_v6_0_gart_disable(adev);
 960
 961         return 0;
 962 }
 963
 964 static int gmc_v6_0_suspend(void *handle)
 965 {
 966         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 967
 968         gmc_v6_0_hw_fini(adev);
 969
 970         return 0;
 971 }
 972
 973 static int gmc_v6_0_resume(void *handle)
 974 {
 975         int r;
 976         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 977
 978         r = gmc_v6_0_hw_init(adev);
 979         if (r)
 980                 return r;
 981
 982         amdgpu_vmid_reset_all(adev);
 983
 984         return 0;
 985 }
 986
 987 static bool gmc_v6_0_is_idle(void *handle)
 988 {
 989         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 990         u32 tmp = RREG32(mmSRBM_STATUS);
 991
 992         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 993                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
 994                 return false;
 995
 996         return true;
 997 }
 998
 999 static int gmc_v6_0_wait_for_idle(void *handle)
1000 {
1001         unsigned i;
1002         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003
1004         for (i = 0; i < adev->usec_timeout; i++) {
1005                 if (gmc_v6_0_is_idle(handle))
1006                         return 0;
1007                 udelay(1);
1008         }
1009         return -ETIMEDOUT;
1010
1011 }
1012
1013 static int gmc_v6_0_soft_reset(void *handle)
1014 {
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016         u32 srbm_soft_reset = 0;
1017         u32 tmp = RREG32(mmSRBM_STATUS);
1018
1019         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1020                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1021                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1022
1023         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1024                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1025                 if (!(adev->flags & AMD_IS_APU))
1026                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1027                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1028         }
1029
1030         if (srbm_soft_reset) {
1031                 gmc_v6_0_mc_stop(adev);
1032                 if (gmc_v6_0_wait_for_idle(adev)) {
1033                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1034                 }
1035
1036
1037                 tmp = RREG32(mmSRBM_SOFT_RESET);
1038                 tmp |= srbm_soft_reset;
1039                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1040                 WREG32(mmSRBM_SOFT_RESET, tmp);
1041                 tmp = RREG32(mmSRBM_SOFT_RESET);
1042
1043                 udelay(50);
1044
1045                 tmp &= ~srbm_soft_reset;
1046                 WREG32(mmSRBM_SOFT_RESET, tmp);
1047                 tmp = RREG32(mmSRBM_SOFT_RESET);
1048
1049                 udelay(50);
1050
1051                 gmc_v6_0_mc_resume(adev);
1052                 udelay(50);
1053         }
1054
1055         return 0;
1056 }
1057
1058 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1059                                              struct amdgpu_irq_src *src,
1060                                              unsigned type,
1061                                              enum amdgpu_interrupt_state state)
1062 {
1063         u32 tmp;
1064         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1065                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1066                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1067                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1068                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1069                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1070
1071         switch (state) {
1072         case AMDGPU_IRQ_STATE_DISABLE:
1073                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1074                 tmp &= ~bits;
1075                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1076                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1077                 tmp &= ~bits;
1078                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1079                 break;
1080         case AMDGPU_IRQ_STATE_ENABLE:
1081                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1082                 tmp |= bits;
1083                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1084                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1085                 tmp |= bits;
1086                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1087                 break;
1088         default:
1089                 break;
1090         }
1091
1092         return 0;
1093 }
1094
1095 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1096                                       struct amdgpu_irq_src *source,
1097                                       struct amdgpu_iv_entry *entry)
1098 {
1099         u32 addr, status;
1100
1101         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1102         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1103         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1104
1105         if (!addr && !status)
1106                 return 0;
1107
1108         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1109                 gmc_v6_0_set_fault_enable_default(adev, false);
1110
1111         if (printk_ratelimit()) {
1112                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1113                         entry->src_id, entry->src_data[0]);
1114                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1115                         addr);
1116                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1117                         status);
1118                 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1119         }
1120
1121         return 0;
1122 }
1123
1124 static int gmc_v6_0_set_clockgating_state(void *handle,
1125                                           enum amd_clockgating_state state)
1126 {
1127         return 0;
1128 }
1129
1130 static int gmc_v6_0_set_powergating_state(void *handle,
1131                                           enum amd_powergating_state state)
1132 {
1133         return 0;
1134 }
1135
1136 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1137         .name = "gmc_v6_0",
1138         .early_init = gmc_v6_0_early_init,
1139         .late_init = gmc_v6_0_late_init,
1140         .sw_init = gmc_v6_0_sw_init,
1141         .sw_fini = gmc_v6_0_sw_fini,
1142         .hw_init = gmc_v6_0_hw_init,
1143         .hw_fini = gmc_v6_0_hw_fini,
1144         .suspend = gmc_v6_0_suspend,
1145         .resume = gmc_v6_0_resume,
1146         .is_idle = gmc_v6_0_is_idle,
1147         .wait_for_idle = gmc_v6_0_wait_for_idle,
1148         .soft_reset = gmc_v6_0_soft_reset,
1149         .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1150         .set_powergating_state = gmc_v6_0_set_powergating_state,
1151 };
1152
1153 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1154         .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1155         .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1156         .set_prt = gmc_v6_0_set_prt,
1157         .get_vm_pde = gmc_v6_0_get_vm_pde,
1158         .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1159 };
1160
1161 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1162         .set = gmc_v6_0_vm_fault_interrupt_state,
1163         .process = gmc_v6_0_process_interrupt,
1164 };
1165
1166 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1167 {
1168         adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1169 }
1170
1171 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1172 {
1173         adev->gmc.vm_fault.num_types = 1;
1174         adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1175 }
1176
1177 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1178 {
1179         .type = AMD_IP_BLOCK_TYPE_GMC,
1180         .major = 6,
1181         .minor = 0,
1182         .rev = 0,
1183         .funcs = &gmc_v6_0_ip_funcs,
1184 };