2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
27 #include "amdgpu_ih.h"
28 #include "amdgpu_gfx.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_si.h"
31 #include "bif/bif_3_0_d.h"
32 #include "bif/bif_3_0_sh_mask.h"
33 #include "oss/oss_1_0_d.h"
34 #include "oss/oss_1_0_sh_mask.h"
35 #include "gca/gfx_6_0_d.h"
36 #include "gca/gfx_6_0_sh_mask.h"
37 #include "gmc/gmc_6_0_d.h"
38 #include "gmc/gmc_6_0_sh_mask.h"
39 #include "dce/dce_6_0_d.h"
40 #include "dce/dce_6_0_sh_mask.h"
41 #include "gca/gfx_7_2_enum.h"
45 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
46 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
47 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
51 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
52 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
53 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
54 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
56 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
57 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
58 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
59 #define MICRO_TILE_MODE(x) ((x) << 0)
60 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
61 #define BANK_WIDTH(x) ((x) << 14)
62 #define BANK_HEIGHT(x) ((x) << 16)
63 #define MACRO_TILE_ASPECT(x) ((x) << 18)
64 #define NUM_BANKS(x) ((x) << 20)
66 static const u32 verde_rlc_save_restore_register_list[] =
68 (0x8000 << 16) | (0x98f4 >> 2),
70 (0x8040 << 16) | (0x98f4 >> 2),
72 (0x8000 << 16) | (0xe80 >> 2),
74 (0x8040 << 16) | (0xe80 >> 2),
76 (0x8000 << 16) | (0x89bc >> 2),
78 (0x8040 << 16) | (0x89bc >> 2),
80 (0x8000 << 16) | (0x8c1c >> 2),
82 (0x8040 << 16) | (0x8c1c >> 2),
84 (0x9c00 << 16) | (0x98f0 >> 2),
86 (0x9c00 << 16) | (0xe7c >> 2),
88 (0x8000 << 16) | (0x9148 >> 2),
90 (0x8040 << 16) | (0x9148 >> 2),
92 (0x9c00 << 16) | (0x9150 >> 2),
94 (0x9c00 << 16) | (0x897c >> 2),
96 (0x9c00 << 16) | (0x8d8c >> 2),
98 (0x9c00 << 16) | (0xac54 >> 2),
101 (0x9c00 << 16) | (0x98f8 >> 2),
103 (0x9c00 << 16) | (0x9910 >> 2),
105 (0x9c00 << 16) | (0x9914 >> 2),
107 (0x9c00 << 16) | (0x9918 >> 2),
109 (0x9c00 << 16) | (0x991c >> 2),
111 (0x9c00 << 16) | (0x9920 >> 2),
113 (0x9c00 << 16) | (0x9924 >> 2),
115 (0x9c00 << 16) | (0x9928 >> 2),
117 (0x9c00 << 16) | (0x992c >> 2),
119 (0x9c00 << 16) | (0x9930 >> 2),
121 (0x9c00 << 16) | (0x9934 >> 2),
123 (0x9c00 << 16) | (0x9938 >> 2),
125 (0x9c00 << 16) | (0x993c >> 2),
127 (0x9c00 << 16) | (0x9940 >> 2),
129 (0x9c00 << 16) | (0x9944 >> 2),
131 (0x9c00 << 16) | (0x9948 >> 2),
133 (0x9c00 << 16) | (0x994c >> 2),
135 (0x9c00 << 16) | (0x9950 >> 2),
137 (0x9c00 << 16) | (0x9954 >> 2),
139 (0x9c00 << 16) | (0x9958 >> 2),
141 (0x9c00 << 16) | (0x995c >> 2),
143 (0x9c00 << 16) | (0x9960 >> 2),
145 (0x9c00 << 16) | (0x9964 >> 2),
147 (0x9c00 << 16) | (0x9968 >> 2),
149 (0x9c00 << 16) | (0x996c >> 2),
151 (0x9c00 << 16) | (0x9970 >> 2),
153 (0x9c00 << 16) | (0x9974 >> 2),
155 (0x9c00 << 16) | (0x9978 >> 2),
157 (0x9c00 << 16) | (0x997c >> 2),
159 (0x9c00 << 16) | (0x9980 >> 2),
161 (0x9c00 << 16) | (0x9984 >> 2),
163 (0x9c00 << 16) | (0x9988 >> 2),
165 (0x9c00 << 16) | (0x998c >> 2),
167 (0x9c00 << 16) | (0x8c00 >> 2),
169 (0x9c00 << 16) | (0x8c14 >> 2),
171 (0x9c00 << 16) | (0x8c04 >> 2),
173 (0x9c00 << 16) | (0x8c08 >> 2),
175 (0x8000 << 16) | (0x9b7c >> 2),
177 (0x8040 << 16) | (0x9b7c >> 2),
179 (0x8000 << 16) | (0xe84 >> 2),
181 (0x8040 << 16) | (0xe84 >> 2),
183 (0x8000 << 16) | (0x89c0 >> 2),
185 (0x8040 << 16) | (0x89c0 >> 2),
187 (0x8000 << 16) | (0x914c >> 2),
189 (0x8040 << 16) | (0x914c >> 2),
191 (0x8000 << 16) | (0x8c20 >> 2),
193 (0x8040 << 16) | (0x8c20 >> 2),
195 (0x8000 << 16) | (0x9354 >> 2),
197 (0x8040 << 16) | (0x9354 >> 2),
199 (0x9c00 << 16) | (0x9060 >> 2),
201 (0x9c00 << 16) | (0x9364 >> 2),
203 (0x9c00 << 16) | (0x9100 >> 2),
205 (0x9c00 << 16) | (0x913c >> 2),
207 (0x8000 << 16) | (0x90e0 >> 2),
209 (0x8000 << 16) | (0x90e4 >> 2),
211 (0x8000 << 16) | (0x90e8 >> 2),
213 (0x8040 << 16) | (0x90e0 >> 2),
215 (0x8040 << 16) | (0x90e4 >> 2),
217 (0x8040 << 16) | (0x90e8 >> 2),
219 (0x9c00 << 16) | (0x8bcc >> 2),
221 (0x9c00 << 16) | (0x8b24 >> 2),
223 (0x9c00 << 16) | (0x88c4 >> 2),
225 (0x9c00 << 16) | (0x8e50 >> 2),
227 (0x9c00 << 16) | (0x8c0c >> 2),
229 (0x9c00 << 16) | (0x8e58 >> 2),
231 (0x9c00 << 16) | (0x8e5c >> 2),
233 (0x9c00 << 16) | (0x9508 >> 2),
235 (0x9c00 << 16) | (0x950c >> 2),
237 (0x9c00 << 16) | (0x9494 >> 2),
239 (0x9c00 << 16) | (0xac0c >> 2),
241 (0x9c00 << 16) | (0xac10 >> 2),
243 (0x9c00 << 16) | (0xac14 >> 2),
245 (0x9c00 << 16) | (0xae00 >> 2),
247 (0x9c00 << 16) | (0xac08 >> 2),
249 (0x9c00 << 16) | (0x88d4 >> 2),
251 (0x9c00 << 16) | (0x88c8 >> 2),
253 (0x9c00 << 16) | (0x88cc >> 2),
255 (0x9c00 << 16) | (0x89b0 >> 2),
257 (0x9c00 << 16) | (0x8b10 >> 2),
259 (0x9c00 << 16) | (0x8a14 >> 2),
261 (0x9c00 << 16) | (0x9830 >> 2),
263 (0x9c00 << 16) | (0x9834 >> 2),
265 (0x9c00 << 16) | (0x9838 >> 2),
267 (0x9c00 << 16) | (0x9a10 >> 2),
269 (0x8000 << 16) | (0x9870 >> 2),
271 (0x8000 << 16) | (0x9874 >> 2),
273 (0x8001 << 16) | (0x9870 >> 2),
275 (0x8001 << 16) | (0x9874 >> 2),
277 (0x8040 << 16) | (0x9870 >> 2),
279 (0x8040 << 16) | (0x9874 >> 2),
281 (0x8041 << 16) | (0x9870 >> 2),
283 (0x8041 << 16) | (0x9874 >> 2),
288 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
290 const char *chip_name;
293 const struct gfx_firmware_header_v1_0 *cp_hdr;
294 const struct rlc_firmware_header_v1_0 *rlc_hdr;
298 switch (adev->asic_type) {
300 chip_name = "tahiti";
303 chip_name = "pitcairn";
312 chip_name = "hainan";
317 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
318 err = reject_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
321 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
324 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
325 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
326 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
328 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
329 err = reject_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
332 err = amdgpu_ucode_validate(adev->gfx.me_fw);
335 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
336 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
337 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
339 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
340 err = reject_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
343 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
346 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
347 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
348 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
350 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
351 err = reject_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
354 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
355 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
356 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
357 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
361 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
362 release_firmware(adev->gfx.pfp_fw);
363 adev->gfx.pfp_fw = NULL;
364 release_firmware(adev->gfx.me_fw);
365 adev->gfx.me_fw = NULL;
366 release_firmware(adev->gfx.ce_fw);
367 adev->gfx.ce_fw = NULL;
368 release_firmware(adev->gfx.rlc_fw);
369 adev->gfx.rlc_fw = NULL;
374 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
376 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
377 u32 reg_offset, split_equal_to_row_size, *tilemode;
379 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
380 tilemode = adev->gfx.config.tile_mode_array;
382 switch (adev->gfx.config.mem_row_size_in_kb) {
384 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
388 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
391 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
395 if (adev->asic_type == CHIP_VERDE) {
396 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
397 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
398 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
399 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
400 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
401 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
402 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
403 NUM_BANKS(ADDR_SURF_16_BANK);
404 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
405 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
406 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
408 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
411 NUM_BANKS(ADDR_SURF_16_BANK);
412 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
413 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
414 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
419 NUM_BANKS(ADDR_SURF_16_BANK);
420 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
421 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
422 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
423 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
426 NUM_BANKS(ADDR_SURF_8_BANK) |
427 TILE_SPLIT(split_equal_to_row_size);
428 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
429 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16);
431 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
432 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
433 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
434 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
435 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
438 NUM_BANKS(ADDR_SURF_4_BANK);
439 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
441 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
446 NUM_BANKS(ADDR_SURF_4_BANK);
447 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
449 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
450 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_2_BANK);
455 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
456 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
457 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
458 PIPE_CONFIG(ADDR_SURF_P4_8x16);
459 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
461 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
466 NUM_BANKS(ADDR_SURF_16_BANK);
467 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
474 NUM_BANKS(ADDR_SURF_16_BANK);
475 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
477 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
481 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
482 NUM_BANKS(ADDR_SURF_16_BANK);
483 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
484 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
485 PIPE_CONFIG(ADDR_SURF_P4_8x16);
486 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
487 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
488 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
489 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
490 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
493 NUM_BANKS(ADDR_SURF_16_BANK);
494 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
496 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
501 NUM_BANKS(ADDR_SURF_16_BANK);
502 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
504 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
509 NUM_BANKS(ADDR_SURF_16_BANK);
510 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
511 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
512 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
516 NUM_BANKS(ADDR_SURF_16_BANK) |
517 TILE_SPLIT(split_equal_to_row_size);
518 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
519 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16);
521 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
522 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
523 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
524 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
527 NUM_BANKS(ADDR_SURF_16_BANK) |
528 TILE_SPLIT(split_equal_to_row_size);
529 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
530 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
531 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
535 NUM_BANKS(ADDR_SURF_16_BANK) |
536 TILE_SPLIT(split_equal_to_row_size);
537 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
538 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
539 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
540 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
544 NUM_BANKS(ADDR_SURF_8_BANK);
545 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
546 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
547 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
548 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
549 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
552 NUM_BANKS(ADDR_SURF_8_BANK);
553 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
554 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
555 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
557 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
560 NUM_BANKS(ADDR_SURF_4_BANK);
561 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
562 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
563 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
564 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
568 NUM_BANKS(ADDR_SURF_4_BANK);
569 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
571 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
572 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
576 NUM_BANKS(ADDR_SURF_2_BANK);
577 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
578 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
580 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
581 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
582 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
583 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
584 NUM_BANKS(ADDR_SURF_2_BANK);
585 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
586 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
587 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
588 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
589 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
592 NUM_BANKS(ADDR_SURF_2_BANK);
593 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
594 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
595 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
596 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
598 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
599 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
600 NUM_BANKS(ADDR_SURF_2_BANK);
601 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_2_BANK);
609 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
611 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
616 NUM_BANKS(ADDR_SURF_2_BANK);
617 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
618 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
619 } else if (adev->asic_type == CHIP_OLAND) {
620 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
621 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
622 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
624 NUM_BANKS(ADDR_SURF_16_BANK) |
625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
628 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
630 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
632 NUM_BANKS(ADDR_SURF_16_BANK) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
636 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
638 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
640 NUM_BANKS(ADDR_SURF_16_BANK) |
641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
642 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
644 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
645 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
646 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
648 NUM_BANKS(ADDR_SURF_16_BANK) |
649 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
650 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
651 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
652 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
653 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
654 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
655 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
656 NUM_BANKS(ADDR_SURF_16_BANK) |
657 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
658 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
659 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
660 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
661 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
662 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
663 TILE_SPLIT(split_equal_to_row_size) |
664 NUM_BANKS(ADDR_SURF_16_BANK) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
668 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
669 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
670 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
671 TILE_SPLIT(split_equal_to_row_size) |
672 NUM_BANKS(ADDR_SURF_16_BANK) |
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
676 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
677 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
678 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
679 TILE_SPLIT(split_equal_to_row_size) |
680 NUM_BANKS(ADDR_SURF_16_BANK) |
681 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
682 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
683 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
684 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
685 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
686 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
687 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
688 NUM_BANKS(ADDR_SURF_16_BANK) |
689 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
690 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
691 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
692 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
693 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
694 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
696 NUM_BANKS(ADDR_SURF_16_BANK) |
697 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
698 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
699 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
700 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
701 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
702 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
704 NUM_BANKS(ADDR_SURF_16_BANK) |
705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
708 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
709 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
710 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
712 NUM_BANKS(ADDR_SURF_16_BANK) |
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
716 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
717 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
718 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
720 NUM_BANKS(ADDR_SURF_16_BANK) |
721 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
722 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
723 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
724 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
725 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
726 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
727 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
728 NUM_BANKS(ADDR_SURF_16_BANK) |
729 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
730 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
731 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
732 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
733 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
734 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
736 NUM_BANKS(ADDR_SURF_16_BANK) |
737 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
738 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
739 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
740 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
741 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
742 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
744 NUM_BANKS(ADDR_SURF_16_BANK) |
745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
748 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
749 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
750 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
752 NUM_BANKS(ADDR_SURF_16_BANK) |
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
756 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
758 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
759 TILE_SPLIT(split_equal_to_row_size) |
760 NUM_BANKS(ADDR_SURF_16_BANK) |
761 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
762 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
763 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
764 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
765 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
766 PIPE_CONFIG(ADDR_SURF_P4_8x16);
767 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
768 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
769 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
773 NUM_BANKS(ADDR_SURF_16_BANK) |
774 TILE_SPLIT(split_equal_to_row_size);
775 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
776 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
777 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
779 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
780 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 TILE_SPLIT(split_equal_to_row_size);
783 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
784 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
785 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
786 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
787 NUM_BANKS(ADDR_SURF_16_BANK) |
788 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
789 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
790 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
791 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
792 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
793 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
794 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
795 NUM_BANKS(ADDR_SURF_16_BANK) |
796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
799 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
800 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
801 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
802 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
803 NUM_BANKS(ADDR_SURF_16_BANK) |
804 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
805 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
806 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
807 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
808 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
809 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
810 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
811 NUM_BANKS(ADDR_SURF_16_BANK) |
812 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
815 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
816 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
817 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
819 NUM_BANKS(ADDR_SURF_8_BANK) |
820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
823 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
824 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
825 } else if (adev->asic_type == CHIP_HAINAN) {
826 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
827 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
828 PIPE_CONFIG(ADDR_SURF_P2) |
829 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
830 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
831 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
832 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
833 NUM_BANKS(ADDR_SURF_16_BANK);
834 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
836 PIPE_CONFIG(ADDR_SURF_P2) |
837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
838 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
841 NUM_BANKS(ADDR_SURF_16_BANK);
842 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
844 PIPE_CONFIG(ADDR_SURF_P2) |
845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
846 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
847 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
848 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
849 NUM_BANKS(ADDR_SURF_16_BANK);
850 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
851 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
852 PIPE_CONFIG(ADDR_SURF_P2) |
853 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
856 NUM_BANKS(ADDR_SURF_8_BANK) |
857 TILE_SPLIT(split_equal_to_row_size);
858 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
859 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
860 PIPE_CONFIG(ADDR_SURF_P2);
861 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
862 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
863 PIPE_CONFIG(ADDR_SURF_P2) |
864 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
865 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
868 NUM_BANKS(ADDR_SURF_8_BANK);
869 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
871 PIPE_CONFIG(ADDR_SURF_P2) |
872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
876 NUM_BANKS(ADDR_SURF_8_BANK);
877 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
879 PIPE_CONFIG(ADDR_SURF_P2) |
880 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
884 NUM_BANKS(ADDR_SURF_4_BANK);
885 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
886 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
887 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
888 PIPE_CONFIG(ADDR_SURF_P2);
889 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
890 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
891 PIPE_CONFIG(ADDR_SURF_P2) |
892 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
893 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
895 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
896 NUM_BANKS(ADDR_SURF_16_BANK);
897 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
898 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
899 PIPE_CONFIG(ADDR_SURF_P2) |
900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
904 NUM_BANKS(ADDR_SURF_16_BANK);
905 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
906 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
907 PIPE_CONFIG(ADDR_SURF_P2) |
908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
909 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
910 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
911 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
912 NUM_BANKS(ADDR_SURF_16_BANK);
913 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
914 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
915 PIPE_CONFIG(ADDR_SURF_P2);
916 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
917 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
918 PIPE_CONFIG(ADDR_SURF_P2) |
919 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
921 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
922 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
923 NUM_BANKS(ADDR_SURF_16_BANK);
924 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 PIPE_CONFIG(ADDR_SURF_P2) |
927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
931 NUM_BANKS(ADDR_SURF_16_BANK);
932 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
934 PIPE_CONFIG(ADDR_SURF_P2) |
935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
939 NUM_BANKS(ADDR_SURF_16_BANK);
940 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
941 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
942 PIPE_CONFIG(ADDR_SURF_P2) |
943 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
944 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
945 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
946 NUM_BANKS(ADDR_SURF_16_BANK) |
947 TILE_SPLIT(split_equal_to_row_size);
948 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
949 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
950 PIPE_CONFIG(ADDR_SURF_P2);
951 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
952 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
953 PIPE_CONFIG(ADDR_SURF_P2) |
954 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
955 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
956 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
957 NUM_BANKS(ADDR_SURF_16_BANK) |
958 TILE_SPLIT(split_equal_to_row_size);
959 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
960 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
961 PIPE_CONFIG(ADDR_SURF_P2) |
962 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
963 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
964 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
965 NUM_BANKS(ADDR_SURF_16_BANK) |
966 TILE_SPLIT(split_equal_to_row_size);
967 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
968 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
969 PIPE_CONFIG(ADDR_SURF_P2) |
970 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
971 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
974 NUM_BANKS(ADDR_SURF_8_BANK);
975 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
976 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
977 PIPE_CONFIG(ADDR_SURF_P2) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
979 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
982 NUM_BANKS(ADDR_SURF_8_BANK);
983 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
984 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
985 PIPE_CONFIG(ADDR_SURF_P2) |
986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
987 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
988 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
989 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
990 NUM_BANKS(ADDR_SURF_8_BANK);
991 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
992 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
993 PIPE_CONFIG(ADDR_SURF_P2) |
994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
995 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
996 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
997 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
998 NUM_BANKS(ADDR_SURF_8_BANK);
999 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1000 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1001 PIPE_CONFIG(ADDR_SURF_P2) |
1002 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1003 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1004 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1005 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1006 NUM_BANKS(ADDR_SURF_4_BANK);
1007 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1008 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1009 PIPE_CONFIG(ADDR_SURF_P2) |
1010 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1011 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1012 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1013 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1014 NUM_BANKS(ADDR_SURF_4_BANK);
1015 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1016 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1017 PIPE_CONFIG(ADDR_SURF_P2) |
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1019 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1022 NUM_BANKS(ADDR_SURF_4_BANK);
1023 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1025 PIPE_CONFIG(ADDR_SURF_P2) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1030 NUM_BANKS(ADDR_SURF_4_BANK);
1031 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1032 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1033 PIPE_CONFIG(ADDR_SURF_P2) |
1034 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1035 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1038 NUM_BANKS(ADDR_SURF_4_BANK);
1039 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1040 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1041 PIPE_CONFIG(ADDR_SURF_P2) |
1042 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1043 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1044 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1045 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1046 NUM_BANKS(ADDR_SURF_4_BANK);
1047 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1048 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1049 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1050 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1051 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1052 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1054 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1057 NUM_BANKS(ADDR_SURF_16_BANK);
1058 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1065 NUM_BANKS(ADDR_SURF_16_BANK);
1066 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1073 NUM_BANKS(ADDR_SURF_16_BANK);
1074 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1075 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1077 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1078 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1079 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1080 NUM_BANKS(ADDR_SURF_4_BANK) |
1081 TILE_SPLIT(split_equal_to_row_size);
1082 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1083 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1085 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1086 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1088 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1092 NUM_BANKS(ADDR_SURF_2_BANK);
1093 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1100 NUM_BANKS(ADDR_SURF_2_BANK);
1101 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1108 NUM_BANKS(ADDR_SURF_2_BANK);
1109 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1110 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1111 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1112 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1113 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1114 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1115 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1117 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1120 NUM_BANKS(ADDR_SURF_16_BANK);
1121 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1128 NUM_BANKS(ADDR_SURF_16_BANK);
1129 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1130 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1136 NUM_BANKS(ADDR_SURF_16_BANK);
1137 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1138 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1140 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1141 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1142 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1143 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1144 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1147 NUM_BANKS(ADDR_SURF_16_BANK);
1148 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1155 NUM_BANKS(ADDR_SURF_16_BANK);
1156 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1163 NUM_BANKS(ADDR_SURF_16_BANK);
1164 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1165 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1170 NUM_BANKS(ADDR_SURF_16_BANK) |
1171 TILE_SPLIT(split_equal_to_row_size);
1172 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1173 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1174 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1175 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1176 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1177 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1178 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1181 NUM_BANKS(ADDR_SURF_16_BANK) |
1182 TILE_SPLIT(split_equal_to_row_size);
1183 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1184 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1189 NUM_BANKS(ADDR_SURF_16_BANK) |
1190 TILE_SPLIT(split_equal_to_row_size);
1191 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1192 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1195 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1198 NUM_BANKS(ADDR_SURF_4_BANK);
1199 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1200 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1203 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1206 NUM_BANKS(ADDR_SURF_4_BANK);
1207 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1208 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1211 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1214 NUM_BANKS(ADDR_SURF_2_BANK);
1215 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1216 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1222 NUM_BANKS(ADDR_SURF_2_BANK);
1223 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1224 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1230 NUM_BANKS(ADDR_SURF_2_BANK);
1231 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1232 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1235 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1238 NUM_BANKS(ADDR_SURF_2_BANK);
1239 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1240 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1242 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1243 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1246 NUM_BANKS(ADDR_SURF_2_BANK);
1247 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1248 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1251 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1254 NUM_BANKS(ADDR_SURF_2_BANK);
1255 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1256 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1258 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1262 NUM_BANKS(ADDR_SURF_2_BANK);
1263 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1270 NUM_BANKS(ADDR_SURF_2_BANK);
1271 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1272 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1274 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1278 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1279 u32 sh_num, u32 instance)
1283 if (instance == 0xffffffff)
1284 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1288 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1289 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1290 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1291 else if (se_num == 0xffffffff)
1292 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1293 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1294 else if (sh_num == 0xffffffff)
1295 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1296 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1298 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1299 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1300 WREG32(mmGRBM_GFX_INDEX, data);
1303 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1307 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1308 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1310 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1312 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1313 adev->gfx.config.max_sh_per_se);
1315 return ~data & mask;
1318 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1320 switch (adev->asic_type) {
1324 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1325 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1326 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1327 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1328 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1329 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1334 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1335 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1336 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1339 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1345 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1350 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1351 u32 raster_config, unsigned rb_mask,
1354 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1355 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1356 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1357 unsigned rb_per_se = num_rb / num_se;
1358 unsigned se_mask[4];
1361 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1362 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1363 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1364 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1366 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1367 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1368 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1370 for (se = 0; se < num_se; se++) {
1371 unsigned raster_config_se = raster_config;
1372 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1373 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1374 int idx = (se / 2) * 2;
1376 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1377 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1380 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1382 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1385 pkr0_mask &= rb_mask;
1386 pkr1_mask &= rb_mask;
1387 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1388 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1391 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1396 if (rb_per_se >= 2) {
1397 unsigned rb0_mask = 1 << (se * rb_per_se);
1398 unsigned rb1_mask = rb0_mask << 1;
1400 rb0_mask &= rb_mask;
1401 rb1_mask &= rb_mask;
1402 if (!rb0_mask || !rb1_mask) {
1403 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1407 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1410 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1413 if (rb_per_se > 2) {
1414 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1415 rb1_mask = rb0_mask << 1;
1416 rb0_mask &= rb_mask;
1417 rb1_mask &= rb_mask;
1418 if (!rb0_mask || !rb1_mask) {
1419 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1423 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1426 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1431 /* GRBM_GFX_INDEX has a different offset on SI */
1432 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1433 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1436 /* GRBM_GFX_INDEX has a different offset on SI */
1437 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1440 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1444 u32 raster_config = 0;
1446 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1447 adev->gfx.config.max_sh_per_se;
1448 unsigned num_rb_pipes;
1450 mutex_lock(&adev->grbm_idx_mutex);
1451 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1452 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1453 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1454 data = gfx_v6_0_get_rb_active_bitmap(adev);
1455 active_rbs |= data <<
1456 ((i * adev->gfx.config.max_sh_per_se + j) *
1457 rb_bitmap_width_per_sh);
1460 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1462 adev->gfx.config.backend_enable_mask = active_rbs;
1463 adev->gfx.config.num_rbs = hweight32(active_rbs);
1465 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1466 adev->gfx.config.max_shader_engines, 16);
1468 gfx_v6_0_raster_config(adev, &raster_config);
1470 if (!adev->gfx.config.backend_enable_mask ||
1471 adev->gfx.config.num_rbs >= num_rb_pipes)
1472 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1474 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1475 adev->gfx.config.backend_enable_mask,
1478 /* cache the values for userspace */
1479 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1480 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1481 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1482 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1483 RREG32(mmCC_RB_BACKEND_DISABLE);
1484 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1485 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1486 adev->gfx.config.rb_config[i][j].raster_config =
1487 RREG32(mmPA_SC_RASTER_CONFIG);
1490 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1491 mutex_unlock(&adev->grbm_idx_mutex);
1494 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1502 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1503 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1505 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1508 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1512 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1513 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1515 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1516 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1520 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1526 mutex_lock(&adev->grbm_idx_mutex);
1527 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1528 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1529 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1530 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1531 active_cu = gfx_v6_0_get_cu_enabled(adev);
1534 for (k = 0; k < 16; k++) {
1536 if (active_cu & mask) {
1538 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1544 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1545 mutex_unlock(&adev->grbm_idx_mutex);
1548 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1550 adev->gfx.config.double_offchip_lds_buf = 0;
1553 static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1555 u32 gb_addr_config = 0;
1558 u32 hdp_host_path_cntl;
1561 switch (adev->asic_type) {
1563 adev->gfx.config.max_shader_engines = 2;
1564 adev->gfx.config.max_tile_pipes = 12;
1565 adev->gfx.config.max_cu_per_sh = 8;
1566 adev->gfx.config.max_sh_per_se = 2;
1567 adev->gfx.config.max_backends_per_se = 4;
1568 adev->gfx.config.max_texture_channel_caches = 12;
1569 adev->gfx.config.max_gprs = 256;
1570 adev->gfx.config.max_gs_threads = 32;
1571 adev->gfx.config.max_hw_contexts = 8;
1573 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1574 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1575 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1576 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1577 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1580 adev->gfx.config.max_shader_engines = 2;
1581 adev->gfx.config.max_tile_pipes = 8;
1582 adev->gfx.config.max_cu_per_sh = 5;
1583 adev->gfx.config.max_sh_per_se = 2;
1584 adev->gfx.config.max_backends_per_se = 4;
1585 adev->gfx.config.max_texture_channel_caches = 8;
1586 adev->gfx.config.max_gprs = 256;
1587 adev->gfx.config.max_gs_threads = 32;
1588 adev->gfx.config.max_hw_contexts = 8;
1590 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1591 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1592 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1593 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1594 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 adev->gfx.config.max_shader_engines = 1;
1598 adev->gfx.config.max_tile_pipes = 4;
1599 adev->gfx.config.max_cu_per_sh = 5;
1600 adev->gfx.config.max_sh_per_se = 2;
1601 adev->gfx.config.max_backends_per_se = 4;
1602 adev->gfx.config.max_texture_channel_caches = 4;
1603 adev->gfx.config.max_gprs = 256;
1604 adev->gfx.config.max_gs_threads = 32;
1605 adev->gfx.config.max_hw_contexts = 8;
1607 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1608 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1609 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1610 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1611 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1614 adev->gfx.config.max_shader_engines = 1;
1615 adev->gfx.config.max_tile_pipes = 4;
1616 adev->gfx.config.max_cu_per_sh = 6;
1617 adev->gfx.config.max_sh_per_se = 1;
1618 adev->gfx.config.max_backends_per_se = 2;
1619 adev->gfx.config.max_texture_channel_caches = 4;
1620 adev->gfx.config.max_gprs = 256;
1621 adev->gfx.config.max_gs_threads = 16;
1622 adev->gfx.config.max_hw_contexts = 8;
1624 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1625 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1626 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1627 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1628 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1631 adev->gfx.config.max_shader_engines = 1;
1632 adev->gfx.config.max_tile_pipes = 4;
1633 adev->gfx.config.max_cu_per_sh = 5;
1634 adev->gfx.config.max_sh_per_se = 1;
1635 adev->gfx.config.max_backends_per_se = 1;
1636 adev->gfx.config.max_texture_channel_caches = 2;
1637 adev->gfx.config.max_gprs = 256;
1638 adev->gfx.config.max_gs_threads = 16;
1639 adev->gfx.config.max_hw_contexts = 8;
1641 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1642 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1643 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1644 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1645 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1652 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1653 WREG32(mmSRBM_INT_CNTL, 1);
1654 WREG32(mmSRBM_INT_ACK, 1);
1656 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1658 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1659 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1661 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1662 adev->gfx.config.mem_max_burst_length_bytes = 256;
1663 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1664 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1665 if (adev->gfx.config.mem_row_size_in_kb > 4)
1666 adev->gfx.config.mem_row_size_in_kb = 4;
1667 adev->gfx.config.shader_engine_tile_size = 32;
1668 adev->gfx.config.num_gpus = 1;
1669 adev->gfx.config.multi_gpu_tile_size = 64;
1671 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1672 switch (adev->gfx.config.mem_row_size_in_kb) {
1675 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1678 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1681 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1684 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1685 if (adev->gfx.config.max_shader_engines == 2)
1686 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1687 adev->gfx.config.gb_addr_config = gb_addr_config;
1689 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1690 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1691 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1692 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1694 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1697 if (adev->has_uvd) {
1698 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1699 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1700 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1703 gfx_v6_0_tiling_mode_table_init(adev);
1705 gfx_v6_0_setup_rb(adev);
1707 gfx_v6_0_setup_spi(adev);
1709 gfx_v6_0_get_cu_info(adev);
1710 gfx_v6_0_config_init(adev);
1712 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1713 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1714 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1715 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1717 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1718 WREG32(mmSX_DEBUG_1, sx_debug_1);
1720 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1722 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1723 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1724 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1725 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1727 WREG32(mmVGT_NUM_INSTANCES, 1);
1728 WREG32(mmCP_PERFMON_CNTL, 0);
1729 WREG32(mmSQ_CONFIG, 0);
1730 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1731 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1733 WREG32(mmVGT_CACHE_INVALIDATION,
1734 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1735 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1737 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1738 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1740 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1741 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1742 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1743 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1744 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1745 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1746 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1747 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1749 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1750 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1752 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1753 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1759 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1761 adev->gfx.scratch.num_reg = 8;
1762 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1763 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1766 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1768 struct amdgpu_device *adev = ring->adev;
1774 r = amdgpu_gfx_scratch_get(adev, &scratch);
1778 WREG32(scratch, 0xCAFEDEAD);
1780 r = amdgpu_ring_alloc(ring, 3);
1782 goto error_free_scratch;
1784 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1785 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1786 amdgpu_ring_write(ring, 0xDEADBEEF);
1787 amdgpu_ring_commit(ring);
1789 for (i = 0; i < adev->usec_timeout; i++) {
1790 tmp = RREG32(scratch);
1791 if (tmp == 0xDEADBEEF)
1796 if (i >= adev->usec_timeout)
1800 amdgpu_gfx_scratch_free(adev, scratch);
1804 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1806 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1807 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1811 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1812 u64 seq, unsigned flags)
1814 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1815 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1816 /* flush read cache over gart */
1817 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1818 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1819 amdgpu_ring_write(ring, 0);
1820 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1821 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1822 PACKET3_TC_ACTION_ENA |
1823 PACKET3_SH_KCACHE_ACTION_ENA |
1824 PACKET3_SH_ICACHE_ACTION_ENA);
1825 amdgpu_ring_write(ring, 0xFFFFFFFF);
1826 amdgpu_ring_write(ring, 0);
1827 amdgpu_ring_write(ring, 10); /* poll interval */
1828 /* EVENT_WRITE_EOP - flush caches, send int */
1829 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1830 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1831 amdgpu_ring_write(ring, addr & 0xfffffffc);
1832 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1833 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1834 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1835 amdgpu_ring_write(ring, lower_32_bits(seq));
1836 amdgpu_ring_write(ring, upper_32_bits(seq));
1839 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1840 struct amdgpu_job *job,
1841 struct amdgpu_ib *ib,
1844 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1845 u32 header, control = 0;
1847 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1848 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1849 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1850 amdgpu_ring_write(ring, 0);
1853 if (ib->flags & AMDGPU_IB_FLAG_CE)
1854 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1856 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1858 control |= ib->length_dw | (vmid << 24);
1860 amdgpu_ring_write(ring, header);
1861 amdgpu_ring_write(ring,
1865 (ib->gpu_addr & 0xFFFFFFFC));
1866 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1867 amdgpu_ring_write(ring, control);
1871 * gfx_v6_0_ring_test_ib - basic ring IB test
1873 * @ring: amdgpu_ring structure holding ring information
1875 * Allocate an IB and execute it on the gfx ring (SI).
1876 * Provides a basic gfx ring test to verify that IBs are working.
1877 * Returns 0 on success, error on failure.
1879 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1881 struct amdgpu_device *adev = ring->adev;
1882 struct amdgpu_ib ib;
1883 struct dma_fence *f = NULL;
1888 r = amdgpu_gfx_scratch_get(adev, &scratch);
1892 WREG32(scratch, 0xCAFEDEAD);
1893 memset(&ib, 0, sizeof(ib));
1894 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1898 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1899 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1900 ib.ptr[2] = 0xDEADBEEF;
1903 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1907 r = dma_fence_wait_timeout(f, false, timeout);
1914 tmp = RREG32(scratch);
1915 if (tmp == 0xDEADBEEF)
1921 amdgpu_ib_free(adev, &ib, NULL);
1924 amdgpu_gfx_scratch_free(adev, scratch);
1928 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1932 WREG32(mmCP_ME_CNTL, 0);
1934 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1935 CP_ME_CNTL__PFP_HALT_MASK |
1936 CP_ME_CNTL__CE_HALT_MASK));
1937 WREG32(mmSCRATCH_UMSK, 0);
1938 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1939 adev->gfx.gfx_ring[i].sched.ready = false;
1940 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1941 adev->gfx.compute_ring[i].sched.ready = false;
1946 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1949 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1950 const struct gfx_firmware_header_v1_0 *ce_hdr;
1951 const struct gfx_firmware_header_v1_0 *me_hdr;
1952 const __le32 *fw_data;
1955 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1958 gfx_v6_0_cp_gfx_enable(adev, false);
1959 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1960 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1961 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1963 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1964 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1965 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1968 fw_data = (const __le32 *)
1969 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1970 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1971 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1972 for (i = 0; i < fw_size; i++)
1973 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1974 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1977 fw_data = (const __le32 *)
1978 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1979 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1980 WREG32(mmCP_CE_UCODE_ADDR, 0);
1981 for (i = 0; i < fw_size; i++)
1982 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1983 WREG32(mmCP_CE_UCODE_ADDR, 0);
1986 fw_data = (const __be32 *)
1987 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1988 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1989 WREG32(mmCP_ME_RAM_WADDR, 0);
1990 for (i = 0; i < fw_size; i++)
1991 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1992 WREG32(mmCP_ME_RAM_WADDR, 0);
1994 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1995 WREG32(mmCP_CE_UCODE_ADDR, 0);
1996 WREG32(mmCP_ME_RAM_WADDR, 0);
1997 WREG32(mmCP_ME_RAM_RADDR, 0);
2001 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2003 const struct cs_section_def *sect = NULL;
2004 const struct cs_extent_def *ext = NULL;
2005 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2008 r = amdgpu_ring_alloc(ring, 7 + 4);
2010 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2013 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2014 amdgpu_ring_write(ring, 0x1);
2015 amdgpu_ring_write(ring, 0x0);
2016 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2017 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2018 amdgpu_ring_write(ring, 0);
2019 amdgpu_ring_write(ring, 0);
2021 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2022 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2023 amdgpu_ring_write(ring, 0xc000);
2024 amdgpu_ring_write(ring, 0xe000);
2025 amdgpu_ring_commit(ring);
2027 gfx_v6_0_cp_gfx_enable(adev, true);
2029 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2031 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2036 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2038 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2039 for (ext = sect->section; ext->extent != NULL; ++ext) {
2040 if (sect->id == SECT_CONTEXT) {
2041 amdgpu_ring_write(ring,
2042 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2043 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2044 for (i = 0; i < ext->reg_count; i++)
2045 amdgpu_ring_write(ring, ext->extent[i]);
2050 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2051 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2053 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2054 amdgpu_ring_write(ring, 0);
2056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2057 amdgpu_ring_write(ring, 0x00000316);
2058 amdgpu_ring_write(ring, 0x0000000e);
2059 amdgpu_ring_write(ring, 0x00000010);
2061 amdgpu_ring_commit(ring);
2066 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2068 struct amdgpu_ring *ring;
2074 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2075 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2077 /* Set the write pointer delay */
2078 WREG32(mmCP_RB_WPTR_DELAY, 0);
2080 WREG32(mmCP_DEBUG, 0);
2081 WREG32(mmSCRATCH_ADDR, 0);
2083 /* ring 0 - compute and gfx */
2084 /* Set ring buffer size */
2085 ring = &adev->gfx.gfx_ring[0];
2086 rb_bufsz = order_base_2(ring->ring_size / 8);
2087 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2090 tmp |= BUF_SWAP_32BIT;
2092 WREG32(mmCP_RB0_CNTL, tmp);
2094 /* Initialize the ring buffer's read and write pointers */
2095 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2097 WREG32(mmCP_RB0_WPTR, ring->wptr);
2099 /* set the wb address whether it's enabled or not */
2100 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2101 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2102 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2104 WREG32(mmSCRATCH_UMSK, 0);
2107 WREG32(mmCP_RB0_CNTL, tmp);
2109 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2111 /* start the rings */
2112 gfx_v6_0_cp_gfx_start(adev);
2113 r = amdgpu_ring_test_helper(ring);
2120 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2122 return ring->adev->wb.wb[ring->rptr_offs];
2125 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2127 struct amdgpu_device *adev = ring->adev;
2129 if (ring == &adev->gfx.gfx_ring[0])
2130 return RREG32(mmCP_RB0_WPTR);
2131 else if (ring == &adev->gfx.compute_ring[0])
2132 return RREG32(mmCP_RB1_WPTR);
2133 else if (ring == &adev->gfx.compute_ring[1])
2134 return RREG32(mmCP_RB2_WPTR);
2139 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2141 struct amdgpu_device *adev = ring->adev;
2143 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2144 (void)RREG32(mmCP_RB0_WPTR);
2147 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2149 struct amdgpu_device *adev = ring->adev;
2151 if (ring == &adev->gfx.compute_ring[0]) {
2152 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2153 (void)RREG32(mmCP_RB1_WPTR);
2154 } else if (ring == &adev->gfx.compute_ring[1]) {
2155 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2156 (void)RREG32(mmCP_RB2_WPTR);
2163 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2165 struct amdgpu_ring *ring;
2171 /* ring1 - compute only */
2172 /* Set ring buffer size */
2174 ring = &adev->gfx.compute_ring[0];
2175 rb_bufsz = order_base_2(ring->ring_size / 8);
2176 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2178 tmp |= BUF_SWAP_32BIT;
2180 WREG32(mmCP_RB1_CNTL, tmp);
2182 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2184 WREG32(mmCP_RB1_WPTR, ring->wptr);
2186 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2187 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2188 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2191 WREG32(mmCP_RB1_CNTL, tmp);
2192 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2194 ring = &adev->gfx.compute_ring[1];
2195 rb_bufsz = order_base_2(ring->ring_size / 8);
2196 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2198 tmp |= BUF_SWAP_32BIT;
2200 WREG32(mmCP_RB2_CNTL, tmp);
2202 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2204 WREG32(mmCP_RB2_WPTR, ring->wptr);
2205 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2206 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2207 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2210 WREG32(mmCP_RB2_CNTL, tmp);
2211 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2214 for (i = 0; i < 2; i++) {
2215 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2223 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2225 gfx_v6_0_cp_gfx_enable(adev, enable);
2228 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2230 return gfx_v6_0_cp_gfx_load_microcode(adev);
2233 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2236 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2241 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2242 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2244 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2245 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2246 WREG32(mmCP_INT_CNTL_RING0, tmp);
2249 /* read a gfx register */
2250 tmp = RREG32(mmDB_DEPTH_INFO);
2252 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2253 for (i = 0; i < adev->usec_timeout; i++) {
2254 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2261 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2265 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2267 r = gfx_v6_0_cp_load_microcode(adev);
2271 r = gfx_v6_0_cp_gfx_resume(adev);
2274 r = gfx_v6_0_cp_compute_resume(adev);
2278 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2283 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2285 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2286 uint32_t seq = ring->fence_drv.sync_seq;
2287 uint64_t addr = ring->fence_drv.gpu_addr;
2289 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2290 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2291 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2292 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2293 amdgpu_ring_write(ring, addr & 0xfffffffc);
2294 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2295 amdgpu_ring_write(ring, seq);
2296 amdgpu_ring_write(ring, 0xffffffff);
2297 amdgpu_ring_write(ring, 4); /* poll interval */
2300 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2301 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2302 amdgpu_ring_write(ring, 0);
2303 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2304 amdgpu_ring_write(ring, 0);
2308 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2309 unsigned vmid, uint64_t pd_addr)
2311 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2313 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2315 /* wait for the invalidate to complete */
2316 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2317 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2318 WAIT_REG_MEM_ENGINE(0))); /* me */
2319 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2320 amdgpu_ring_write(ring, 0);
2321 amdgpu_ring_write(ring, 0); /* ref */
2322 amdgpu_ring_write(ring, 0); /* mask */
2323 amdgpu_ring_write(ring, 0x20); /* poll interval */
2326 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2327 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2328 amdgpu_ring_write(ring, 0x0);
2330 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2331 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2332 amdgpu_ring_write(ring, 0);
2333 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2334 amdgpu_ring_write(ring, 0);
2338 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2339 uint32_t reg, uint32_t val)
2341 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2343 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2344 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2345 WRITE_DATA_DST_SEL(0)));
2346 amdgpu_ring_write(ring, reg);
2347 amdgpu_ring_write(ring, 0);
2348 amdgpu_ring_write(ring, val);
2351 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2354 volatile u32 *dst_ptr;
2356 u64 reg_list_mc_addr;
2357 const struct cs_section_def *cs_data;
2360 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2361 adev->gfx.rlc.reg_list_size =
2362 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2364 adev->gfx.rlc.cs_data = si_cs_data;
2365 src_ptr = adev->gfx.rlc.reg_list;
2366 dws = adev->gfx.rlc.reg_list_size;
2367 cs_data = adev->gfx.rlc.cs_data;
2370 /* init save restore block */
2371 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2377 /* clear state block */
2378 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2379 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2381 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2382 AMDGPU_GEM_DOMAIN_VRAM,
2383 &adev->gfx.rlc.clear_state_obj,
2384 &adev->gfx.rlc.clear_state_gpu_addr,
2385 (void **)&adev->gfx.rlc.cs_ptr);
2387 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2388 amdgpu_gfx_rlc_fini(adev);
2392 /* set up the cs buffer */
2393 dst_ptr = adev->gfx.rlc.cs_ptr;
2394 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2395 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2396 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2397 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2398 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2399 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2400 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2406 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2408 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2411 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2412 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2416 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2420 for (i = 0; i < adev->usec_timeout; i++) {
2421 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2426 for (i = 0; i < adev->usec_timeout; i++) {
2427 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2433 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2437 tmp = RREG32(mmRLC_CNTL);
2439 WREG32(mmRLC_CNTL, rlc);
2442 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2446 orig = data = RREG32(mmRLC_CNTL);
2448 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2449 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2450 WREG32(mmRLC_CNTL, data);
2452 gfx_v6_0_wait_for_rlc_serdes(adev);
2458 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2460 WREG32(mmRLC_CNTL, 0);
2462 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2463 gfx_v6_0_wait_for_rlc_serdes(adev);
2466 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2468 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2470 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2475 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2477 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2479 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2483 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2487 /* Enable LBPW only for DDR3 */
2488 tmp = RREG32(mmMC_SEQ_MISC0);
2489 if ((tmp & 0xF0000000) == 0xB0000000)
2494 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2498 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2501 const struct rlc_firmware_header_v1_0 *hdr;
2502 const __le32 *fw_data;
2506 if (!adev->gfx.rlc_fw)
2509 adev->gfx.rlc.funcs->stop(adev);
2510 adev->gfx.rlc.funcs->reset(adev);
2511 gfx_v6_0_init_pg(adev);
2512 gfx_v6_0_init_cg(adev);
2514 WREG32(mmRLC_RL_BASE, 0);
2515 WREG32(mmRLC_RL_SIZE, 0);
2516 WREG32(mmRLC_LB_CNTL, 0);
2517 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2518 WREG32(mmRLC_LB_CNTR_INIT, 0);
2519 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2521 WREG32(mmRLC_MC_CNTL, 0);
2522 WREG32(mmRLC_UCODE_CNTL, 0);
2524 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2525 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2526 fw_data = (const __le32 *)
2527 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2529 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2531 for (i = 0; i < fw_size; i++) {
2532 WREG32(mmRLC_UCODE_ADDR, i);
2533 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2535 WREG32(mmRLC_UCODE_ADDR, 0);
2537 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2538 adev->gfx.rlc.funcs->start(adev);
2543 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2545 u32 data, orig, tmp;
2547 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2549 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2550 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2552 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2554 tmp = gfx_v6_0_halt_rlc(adev);
2556 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2557 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2558 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2560 gfx_v6_0_wait_for_rlc_serdes(adev);
2561 gfx_v6_0_update_rlc(adev, tmp);
2563 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2565 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2567 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2569 RREG32(mmCB_CGTT_SCLK_CTRL);
2570 RREG32(mmCB_CGTT_SCLK_CTRL);
2571 RREG32(mmCB_CGTT_SCLK_CTRL);
2572 RREG32(mmCB_CGTT_SCLK_CTRL);
2574 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2578 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2582 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2585 u32 data, orig, tmp = 0;
2587 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2588 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2591 WREG32(mmCGTS_SM_CTRL_REG, data);
2593 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2594 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2595 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2597 WREG32(mmCP_MEM_SLP_CNTL, data);
2600 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2603 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2605 tmp = gfx_v6_0_halt_rlc(adev);
2607 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2608 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2609 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2611 gfx_v6_0_update_rlc(adev, tmp);
2613 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2616 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2618 data = RREG32(mmCP_MEM_SLP_CNTL);
2619 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2620 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2621 WREG32(mmCP_MEM_SLP_CNTL, data);
2623 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2624 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2626 WREG32(mmCGTS_SM_CTRL_REG, data);
2628 tmp = gfx_v6_0_halt_rlc(adev);
2630 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2631 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2632 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2634 gfx_v6_0_update_rlc(adev, tmp);
2638 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2641 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2643 gfx_v6_0_enable_mgcg(adev, true);
2644 gfx_v6_0_enable_cgcg(adev, true);
2646 gfx_v6_0_enable_cgcg(adev, false);
2647 gfx_v6_0_enable_mgcg(adev, false);
2649 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2653 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2658 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2663 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2667 orig = data = RREG32(mmRLC_PG_CNTL);
2668 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2673 WREG32(mmRLC_PG_CNTL, data);
2676 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2680 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2682 const __le32 *fw_data;
2683 volatile u32 *dst_ptr;
2684 int me, i, max_me = 4;
2686 u32 table_offset, table_size;
2688 if (adev->asic_type == CHIP_KAVERI)
2691 if (adev->gfx.rlc.cp_table_ptr == NULL)
2694 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2695 for (me = 0; me < max_me; me++) {
2697 const struct gfx_firmware_header_v1_0 *hdr =
2698 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2699 fw_data = (const __le32 *)
2700 (adev->gfx.ce_fw->data +
2701 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2702 table_offset = le32_to_cpu(hdr->jt_offset);
2703 table_size = le32_to_cpu(hdr->jt_size);
2704 } else if (me == 1) {
2705 const struct gfx_firmware_header_v1_0 *hdr =
2706 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2707 fw_data = (const __le32 *)
2708 (adev->gfx.pfp_fw->data +
2709 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2710 table_offset = le32_to_cpu(hdr->jt_offset);
2711 table_size = le32_to_cpu(hdr->jt_size);
2712 } else if (me == 2) {
2713 const struct gfx_firmware_header_v1_0 *hdr =
2714 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2715 fw_data = (const __le32 *)
2716 (adev->gfx.me_fw->data +
2717 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2718 table_offset = le32_to_cpu(hdr->jt_offset);
2719 table_size = le32_to_cpu(hdr->jt_size);
2720 } else if (me == 3) {
2721 const struct gfx_firmware_header_v1_0 *hdr =
2722 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2723 fw_data = (const __le32 *)
2724 (adev->gfx.mec_fw->data +
2725 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2726 table_offset = le32_to_cpu(hdr->jt_offset);
2727 table_size = le32_to_cpu(hdr->jt_size);
2729 const struct gfx_firmware_header_v1_0 *hdr =
2730 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2731 fw_data = (const __le32 *)
2732 (adev->gfx.mec2_fw->data +
2733 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2734 table_offset = le32_to_cpu(hdr->jt_offset);
2735 table_size = le32_to_cpu(hdr->jt_size);
2738 for (i = 0; i < table_size; i ++) {
2739 dst_ptr[bo_offset + i] =
2740 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2743 bo_offset += table_size;
2747 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2750 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2751 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2752 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2753 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2755 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2756 (void)RREG32(mmDB_RENDER_CONTROL);
2760 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2764 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2766 tmp = RREG32(mmRLC_MAX_PG_CU);
2767 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2768 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2769 WREG32(mmRLC_MAX_PG_CU, tmp);
2772 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2777 orig = data = RREG32(mmRLC_PG_CNTL);
2778 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2779 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2781 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2783 WREG32(mmRLC_PG_CNTL, data);
2786 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2791 orig = data = RREG32(mmRLC_PG_CNTL);
2792 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2793 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2795 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2797 WREG32(mmRLC_PG_CNTL, data);
2800 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2804 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2805 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2806 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2808 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2809 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2810 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2811 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2812 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2815 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2817 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2818 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2819 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2822 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2825 const struct cs_section_def *sect = NULL;
2826 const struct cs_extent_def *ext = NULL;
2828 if (adev->gfx.rlc.cs_data == NULL)
2831 /* begin clear state */
2833 /* context control state */
2836 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2837 for (ext = sect->section; ext->extent != NULL; ++ext) {
2838 if (sect->id == SECT_CONTEXT)
2839 count += 2 + ext->reg_count;
2844 /* pa_sc_raster_config */
2846 /* end clear state */
2854 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2855 volatile u32 *buffer)
2858 const struct cs_section_def *sect = NULL;
2859 const struct cs_extent_def *ext = NULL;
2861 if (adev->gfx.rlc.cs_data == NULL)
2866 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2867 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2868 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2869 buffer[count++] = cpu_to_le32(0x80000000);
2870 buffer[count++] = cpu_to_le32(0x80000000);
2872 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2873 for (ext = sect->section; ext->extent != NULL; ++ext) {
2874 if (sect->id == SECT_CONTEXT) {
2876 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2877 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2878 for (i = 0; i < ext->reg_count; i++)
2879 buffer[count++] = cpu_to_le32(ext->extent[i]);
2886 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2887 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2888 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2890 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2891 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2893 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2894 buffer[count++] = cpu_to_le32(0);
2897 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2899 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2900 AMD_PG_SUPPORT_GFX_SMG |
2901 AMD_PG_SUPPORT_GFX_DMG |
2903 AMD_PG_SUPPORT_GDS |
2904 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2905 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2906 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2907 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2908 gfx_v6_0_init_gfx_cgpg(adev);
2909 gfx_v6_0_enable_cp_pg(adev, true);
2910 gfx_v6_0_enable_gds_pg(adev, true);
2912 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2913 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2916 gfx_v6_0_init_ao_cu_mask(adev);
2917 gfx_v6_0_update_gfx_pg(adev, true);
2920 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2921 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2925 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2927 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2928 AMD_PG_SUPPORT_GFX_SMG |
2929 AMD_PG_SUPPORT_GFX_DMG |
2931 AMD_PG_SUPPORT_GDS |
2932 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2933 gfx_v6_0_update_gfx_pg(adev, false);
2934 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2935 gfx_v6_0_enable_cp_pg(adev, false);
2936 gfx_v6_0_enable_gds_pg(adev, false);
2941 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2945 mutex_lock(&adev->gfx.gpu_clock_mutex);
2946 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2947 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2948 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2949 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2953 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2955 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2956 gfx_v6_0_ring_emit_vgt_flush(ring);
2957 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2958 amdgpu_ring_write(ring, 0x80000000);
2959 amdgpu_ring_write(ring, 0);
2963 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2965 WREG32(mmSQ_IND_INDEX,
2966 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2967 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2968 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2969 (SQ_IND_INDEX__FORCE_READ_MASK));
2970 return RREG32(mmSQ_IND_DATA);
2973 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2974 uint32_t wave, uint32_t thread,
2975 uint32_t regno, uint32_t num, uint32_t *out)
2977 WREG32(mmSQ_IND_INDEX,
2978 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2979 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2980 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2981 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2982 (SQ_IND_INDEX__FORCE_READ_MASK) |
2983 (SQ_IND_INDEX__AUTO_INCR_MASK));
2985 *(out++) = RREG32(mmSQ_IND_DATA);
2988 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2990 /* type 0 wave data */
2991 dst[(*no_fields)++] = 0;
2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2993 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2994 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2995 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2996 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2997 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2998 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2999 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3000 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3001 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3002 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3003 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3004 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3005 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3006 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3007 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3008 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3009 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3012 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3013 uint32_t wave, uint32_t start,
3014 uint32_t size, uint32_t *dst)
3017 adev, simd, wave, 0,
3018 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3021 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3022 u32 me, u32 pipe, u32 q, u32 vm)
3024 DRM_INFO("Not implemented\n");
3027 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3028 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3029 .select_se_sh = &gfx_v6_0_select_se_sh,
3030 .read_wave_data = &gfx_v6_0_read_wave_data,
3031 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3032 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3035 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3036 .init = gfx_v6_0_rlc_init,
3037 .resume = gfx_v6_0_rlc_resume,
3038 .stop = gfx_v6_0_rlc_stop,
3039 .reset = gfx_v6_0_rlc_reset,
3040 .start = gfx_v6_0_rlc_start
3043 static int gfx_v6_0_early_init(void *handle)
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3047 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3048 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3049 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3050 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3051 gfx_v6_0_set_ring_funcs(adev);
3052 gfx_v6_0_set_irq_funcs(adev);
3057 static int gfx_v6_0_sw_init(void *handle)
3059 struct amdgpu_ring *ring;
3060 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3067 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3071 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3075 gfx_v6_0_scratch_init(adev);
3077 r = gfx_v6_0_init_microcode(adev);
3079 DRM_ERROR("Failed to load gfx firmware!\n");
3083 r = adev->gfx.rlc.funcs->init(adev);
3085 DRM_ERROR("Failed to init rlc BOs!\n");
3089 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3090 ring = &adev->gfx.gfx_ring[i];
3091 ring->ring_obj = NULL;
3092 sprintf(ring->name, "gfx");
3093 r = amdgpu_ring_init(adev, ring, 1024,
3094 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
3099 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3102 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3103 DRM_ERROR("Too many (%d) compute rings!\n", i);
3106 ring = &adev->gfx.compute_ring[i];
3107 ring->ring_obj = NULL;
3108 ring->use_doorbell = false;
3109 ring->doorbell_index = 0;
3113 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3114 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3115 r = amdgpu_ring_init(adev, ring, 1024,
3116 &adev->gfx.eop_irq, irq_type);
3124 static int gfx_v6_0_sw_fini(void *handle)
3127 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3129 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3130 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3131 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3132 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3134 amdgpu_gfx_rlc_fini(adev);
3139 static int gfx_v6_0_hw_init(void *handle)
3142 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3144 gfx_v6_0_constants_init(adev);
3146 r = adev->gfx.rlc.funcs->resume(adev);
3150 r = gfx_v6_0_cp_resume(adev);
3154 adev->gfx.ce_ram_size = 0x8000;
3159 static int gfx_v6_0_hw_fini(void *handle)
3161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3163 gfx_v6_0_cp_enable(adev, false);
3164 adev->gfx.rlc.funcs->stop(adev);
3165 gfx_v6_0_fini_pg(adev);
3170 static int gfx_v6_0_suspend(void *handle)
3172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3174 return gfx_v6_0_hw_fini(adev);
3177 static int gfx_v6_0_resume(void *handle)
3179 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3181 return gfx_v6_0_hw_init(adev);
3184 static bool gfx_v6_0_is_idle(void *handle)
3186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3188 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3194 static int gfx_v6_0_wait_for_idle(void *handle)
3197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3199 for (i = 0; i < adev->usec_timeout; i++) {
3200 if (gfx_v6_0_is_idle(handle))
3207 static int gfx_v6_0_soft_reset(void *handle)
3212 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3213 enum amdgpu_interrupt_state state)
3218 case AMDGPU_IRQ_STATE_DISABLE:
3219 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3220 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3221 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3223 case AMDGPU_IRQ_STATE_ENABLE:
3224 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3225 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3226 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3233 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3235 enum amdgpu_interrupt_state state)
3239 case AMDGPU_IRQ_STATE_DISABLE:
3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3242 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3243 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3247 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3248 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3252 case AMDGPU_IRQ_STATE_ENABLE:
3254 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3255 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3256 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3259 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3260 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3261 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3273 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3274 struct amdgpu_irq_src *src,
3276 enum amdgpu_interrupt_state state)
3281 case AMDGPU_IRQ_STATE_DISABLE:
3282 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3283 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3284 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3286 case AMDGPU_IRQ_STATE_ENABLE:
3287 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3288 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3289 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3298 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3299 struct amdgpu_irq_src *src,
3301 enum amdgpu_interrupt_state state)
3306 case AMDGPU_IRQ_STATE_DISABLE:
3307 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3308 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3309 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3311 case AMDGPU_IRQ_STATE_ENABLE:
3312 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3313 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3314 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3323 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3324 struct amdgpu_irq_src *src,
3326 enum amdgpu_interrupt_state state)
3329 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3330 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3332 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3333 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3335 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3336 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3344 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3345 struct amdgpu_irq_src *source,
3346 struct amdgpu_iv_entry *entry)
3348 switch (entry->ring_id) {
3350 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3354 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3362 static void gfx_v6_0_fault(struct amdgpu_device *adev,
3363 struct amdgpu_iv_entry *entry)
3365 struct amdgpu_ring *ring;
3367 switch (entry->ring_id) {
3369 ring = &adev->gfx.gfx_ring[0];
3373 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3378 drm_sched_fault(&ring->sched);
3381 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3382 struct amdgpu_irq_src *source,
3383 struct amdgpu_iv_entry *entry)
3385 DRM_ERROR("Illegal register access in command stream\n");
3386 gfx_v6_0_fault(adev, entry);
3390 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3391 struct amdgpu_irq_src *source,
3392 struct amdgpu_iv_entry *entry)
3394 DRM_ERROR("Illegal instruction in command stream\n");
3395 gfx_v6_0_fault(adev, entry);
3399 static int gfx_v6_0_set_clockgating_state(void *handle,
3400 enum amd_clockgating_state state)
3403 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3405 if (state == AMD_CG_STATE_GATE)
3408 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3410 gfx_v6_0_enable_mgcg(adev, true);
3411 gfx_v6_0_enable_cgcg(adev, true);
3413 gfx_v6_0_enable_cgcg(adev, false);
3414 gfx_v6_0_enable_mgcg(adev, false);
3416 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3421 static int gfx_v6_0_set_powergating_state(void *handle,
3422 enum amd_powergating_state state)
3425 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3427 if (state == AMD_PG_STATE_GATE)
3430 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3431 AMD_PG_SUPPORT_GFX_SMG |
3432 AMD_PG_SUPPORT_GFX_DMG |
3434 AMD_PG_SUPPORT_GDS |
3435 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3436 gfx_v6_0_update_gfx_pg(adev, gate);
3437 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3438 gfx_v6_0_enable_cp_pg(adev, gate);
3439 gfx_v6_0_enable_gds_pg(adev, gate);
3446 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3448 .early_init = gfx_v6_0_early_init,
3450 .sw_init = gfx_v6_0_sw_init,
3451 .sw_fini = gfx_v6_0_sw_fini,
3452 .hw_init = gfx_v6_0_hw_init,
3453 .hw_fini = gfx_v6_0_hw_fini,
3454 .suspend = gfx_v6_0_suspend,
3455 .resume = gfx_v6_0_resume,
3456 .is_idle = gfx_v6_0_is_idle,
3457 .wait_for_idle = gfx_v6_0_wait_for_idle,
3458 .soft_reset = gfx_v6_0_soft_reset,
3459 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3460 .set_powergating_state = gfx_v6_0_set_powergating_state,
3463 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3464 .type = AMDGPU_RING_TYPE_GFX,
3467 .support_64bit_ptrs = false,
3468 .get_rptr = gfx_v6_0_ring_get_rptr,
3469 .get_wptr = gfx_v6_0_ring_get_wptr,
3470 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3472 5 + 5 + /* hdp flush / invalidate */
3473 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3474 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3475 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3476 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3477 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3478 .emit_ib = gfx_v6_0_ring_emit_ib,
3479 .emit_fence = gfx_v6_0_ring_emit_fence,
3480 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3481 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3482 .test_ring = gfx_v6_0_ring_test_ring,
3483 .test_ib = gfx_v6_0_ring_test_ib,
3484 .insert_nop = amdgpu_ring_insert_nop,
3485 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3486 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3489 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3490 .type = AMDGPU_RING_TYPE_COMPUTE,
3493 .get_rptr = gfx_v6_0_ring_get_rptr,
3494 .get_wptr = gfx_v6_0_ring_get_wptr,
3495 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3497 5 + 5 + /* hdp flush / invalidate */
3498 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3499 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3500 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3501 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3502 .emit_ib = gfx_v6_0_ring_emit_ib,
3503 .emit_fence = gfx_v6_0_ring_emit_fence,
3504 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3505 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3506 .test_ring = gfx_v6_0_ring_test_ring,
3507 .test_ib = gfx_v6_0_ring_test_ib,
3508 .insert_nop = amdgpu_ring_insert_nop,
3509 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3512 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3516 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3517 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3518 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3519 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3522 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3523 .set = gfx_v6_0_set_eop_interrupt_state,
3524 .process = gfx_v6_0_eop_irq,
3527 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3528 .set = gfx_v6_0_set_priv_reg_fault_state,
3529 .process = gfx_v6_0_priv_reg_irq,
3532 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3533 .set = gfx_v6_0_set_priv_inst_fault_state,
3534 .process = gfx_v6_0_priv_inst_irq,
3537 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3539 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3540 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3542 adev->gfx.priv_reg_irq.num_types = 1;
3543 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3545 adev->gfx.priv_inst_irq.num_types = 1;
3546 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3549 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3551 int i, j, k, counter, active_cu_number = 0;
3552 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3553 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3554 unsigned disable_masks[4 * 2];
3557 if (adev->flags & AMD_IS_APU)
3560 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3562 memset(cu_info, 0, sizeof(*cu_info));
3564 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3566 mutex_lock(&adev->grbm_idx_mutex);
3567 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3568 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3572 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3574 gfx_v6_0_set_user_cu_inactive_bitmap(
3575 adev, disable_masks[i * 2 + j]);
3576 bitmap = gfx_v6_0_get_cu_enabled(adev);
3577 cu_info->bitmap[i][j] = bitmap;
3579 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3580 if (bitmap & mask) {
3581 if (counter < ao_cu_num)
3587 active_cu_number += counter;
3589 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3590 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3594 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3595 mutex_unlock(&adev->grbm_idx_mutex);
3597 cu_info->number = active_cu_number;
3598 cu_info->ao_cu_mask = ao_cu_mask;
3601 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3603 .type = AMD_IP_BLOCK_TYPE_GFX,
3607 .funcs = &gfx_v6_0_ip_funcs,
projects / librecmc / linux-libre.git / blob