drivers/gpu/drm/amd/amdgpu/dce_virtual.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_vblank.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_pm.h"
  28 #include "amdgpu_i2c.h"
  29 #include "atom.h"
  30 #include "amdgpu_pll.h"
  31 #include "amdgpu_connectors.h"
  32 #ifdef CONFIG_DRM_AMDGPU_SI
  33 #include "dce_v6_0.h"
  34 #endif
  35 #ifdef CONFIG_DRM_AMDGPU_CIK
  36 #include "dce_v8_0.h"
  37 #endif
  38 #include "dce_v10_0.h"
  39 #include "dce_v11_0.h"
  40 #include "dce_virtual.h"
  41 #include "ivsrcid/ivsrcid_vislands30.h"
  42
  43 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  44
  45
  46 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  48 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  49                                               int index);
  50 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  51                                                         int crtc,
  52                                                         enum amdgpu_interrupt_state state);
  53
  54 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  55 {
  56         return 0;
  57 }
  58
  59 static void dce_virtual_page_flip(struct amdgpu_device *adev,
  60                               int crtc_id, u64 crtc_base, bool async)
  61 {
  62         return;
  63 }
  64
  65 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  66                                         u32 *vbl, u32 *position)
  67 {
  68         *vbl = 0;
  69         *position = 0;
  70
  71         return -EINVAL;
  72 }
  73
  74 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  75                                enum amdgpu_hpd_id hpd)
  76 {
  77         return true;
  78 }
  79
  80 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  81                                       enum amdgpu_hpd_id hpd)
  82 {
  83         return;
  84 }
  85
  86 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  87 {
  88         return 0;
  89 }
  90
  91 /**
  92  * dce_virtual_bandwidth_update - program display watermarks
  93  *
  94  * @adev: amdgpu_device pointer
  95  *
  96  * Calculate and program the display watermarks and line
  97  * buffer allocation (CIK).
  98  */
  99 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
 100 {
 101         return;
 102 }
 103
 104 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 105                                       u16 *green, u16 *blue, uint32_t size,
 106                                       struct drm_modeset_acquire_ctx *ctx)
 107 {
 108         return 0;
 109 }
 110
 111 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 112 {
 113         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 114
 115         drm_crtc_cleanup(crtc);
 116         kfree(amdgpu_crtc);
 117 }
 118
 119 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 120         .cursor_set2 = NULL,
 121         .cursor_move = NULL,
 122         .gamma_set = dce_virtual_crtc_gamma_set,
 123         .set_config = amdgpu_display_crtc_set_config,
 124         .destroy = dce_virtual_crtc_destroy,
 125         .page_flip_target = amdgpu_display_crtc_page_flip_target,
 126         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 127         .enable_vblank = amdgpu_enable_vblank_kms,
 128         .disable_vblank = amdgpu_disable_vblank_kms,
 129         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 130 };
 131
 132 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 133 {
 134         struct drm_device *dev = crtc->dev;
 135         struct amdgpu_device *adev = dev->dev_private;
 136         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 137         unsigned type;
 138
 139         if (amdgpu_sriov_vf(adev))
 140                 return;
 141
 142         switch (mode) {
 143         case DRM_MODE_DPMS_ON:
 144                 amdgpu_crtc->enabled = true;
 145                 /* Make sure VBLANK interrupts are still enabled */
 146                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
 147                                                 amdgpu_crtc->crtc_id);
 148                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
 149                 drm_crtc_vblank_on(crtc);
 150                 break;
 151         case DRM_MODE_DPMS_STANDBY:
 152         case DRM_MODE_DPMS_SUSPEND:
 153         case DRM_MODE_DPMS_OFF:
 154                 drm_crtc_vblank_off(crtc);
 155                 amdgpu_crtc->enabled = false;
 156                 break;
 157         }
 158 }
 159
 160
 161 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 162 {
 163         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 164 }
 165
 166 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 167 {
 168         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 169 }
 170
 171 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 172 {
 173         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 174
 175         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 176
 177         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 178         amdgpu_crtc->encoder = NULL;
 179         amdgpu_crtc->connector = NULL;
 180 }
 181
 182 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 183                                   struct drm_display_mode *mode,
 184                                   struct drm_display_mode *adjusted_mode,
 185                                   int x, int y, struct drm_framebuffer *old_fb)
 186 {
 187         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 188
 189         /* update the hw version fpr dpm */
 190         amdgpu_crtc->hw_mode = *adjusted_mode;
 191
 192         return 0;
 193 }
 194
 195 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 196                                      const struct drm_display_mode *mode,
 197                                      struct drm_display_mode *adjusted_mode)
 198 {
 199         return true;
 200 }
 201
 202
 203 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 204                                   struct drm_framebuffer *old_fb)
 205 {
 206         return 0;
 207 }
 208
 209 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 210                                          struct drm_framebuffer *fb,
 211                                          int x, int y, enum mode_set_atomic state)
 212 {
 213         return 0;
 214 }
 215
 216 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 217         .dpms = dce_virtual_crtc_dpms,
 218         .mode_fixup = dce_virtual_crtc_mode_fixup,
 219         .mode_set = dce_virtual_crtc_mode_set,
 220         .mode_set_base = dce_virtual_crtc_set_base,
 221         .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 222         .prepare = dce_virtual_crtc_prepare,
 223         .commit = dce_virtual_crtc_commit,
 224         .disable = dce_virtual_crtc_disable,
 225         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 226 };
 227
 228 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 229 {
 230         struct amdgpu_crtc *amdgpu_crtc;
 231
 232         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 233                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 234         if (amdgpu_crtc == NULL)
 235                 return -ENOMEM;
 236
 237         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 238
 239         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 240         amdgpu_crtc->crtc_id = index;
 241         adev->mode_info.crtcs[index] = amdgpu_crtc;
 242
 243         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 244         amdgpu_crtc->encoder = NULL;
 245         amdgpu_crtc->connector = NULL;
 246         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 247         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 248
 249         return 0;
 250 }
 251
 252 static int dce_virtual_early_init(void *handle)
 253 {
 254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 255
 256         dce_virtual_set_display_funcs(adev);
 257         dce_virtual_set_irq_funcs(adev);
 258
 259         adev->mode_info.num_hpd = 1;
 260         adev->mode_info.num_dig = 1;
 261         return 0;
 262 }
 263
 264 static struct drm_encoder *
 265 dce_virtual_encoder(struct drm_connector *connector)
 266 {
 267         struct drm_encoder *encoder;
 268
 269         drm_connector_for_each_possible_encoder(connector, encoder) {
 270                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 271                         return encoder;
 272         }
 273
 274         /* pick the first one */
 275         drm_connector_for_each_possible_encoder(connector, encoder)
 276                 return encoder;
 277
 278         return NULL;
 279 }
 280
 281 static int dce_virtual_get_modes(struct drm_connector *connector)
 282 {
 283         struct drm_device *dev = connector->dev;
 284         struct drm_display_mode *mode = NULL;
 285         unsigned i;
 286         static const struct mode_size {
 287                 int w;
 288                 int h;
 289         } common_modes[17] = {
 290                 { 640,  480},
 291                 { 720,  480},
 292                 { 800,  600},
 293                 { 848,  480},
 294                 {1024,  768},
 295                 {1152,  768},
 296                 {1280,  720},
 297                 {1280,  800},
 298                 {1280,  854},
 299                 {1280,  960},
 300                 {1280, 1024},
 301                 {1440,  900},
 302                 {1400, 1050},
 303                 {1680, 1050},
 304                 {1600, 1200},
 305                 {1920, 1080},
 306                 {1920, 1200}
 307         };
 308
 309         for (i = 0; i < 17; i++) {
 310                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 311                 drm_mode_probed_add(connector, mode);
 312         }
 313
 314         return 0;
 315 }
 316
 317 static enum drm_mode_status dce_virtual_mode_valid(struct drm_connector *connector,
 318                                   struct drm_display_mode *mode)
 319 {
 320         return MODE_OK;
 321 }
 322
 323 static int
 324 dce_virtual_dpms(struct drm_connector *connector, int mode)
 325 {
 326         return 0;
 327 }
 328
 329 static int
 330 dce_virtual_set_property(struct drm_connector *connector,
 331                          struct drm_property *property,
 332                          uint64_t val)
 333 {
 334         return 0;
 335 }
 336
 337 static void dce_virtual_destroy(struct drm_connector *connector)
 338 {
 339         drm_connector_unregister(connector);
 340         drm_connector_cleanup(connector);
 341         kfree(connector);
 342 }
 343
 344 static void dce_virtual_force(struct drm_connector *connector)
 345 {
 346         return;
 347 }
 348
 349 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 350         .get_modes = dce_virtual_get_modes,
 351         .mode_valid = dce_virtual_mode_valid,
 352         .best_encoder = dce_virtual_encoder,
 353 };
 354
 355 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 356         .dpms = dce_virtual_dpms,
 357         .fill_modes = drm_helper_probe_single_connector_modes,
 358         .set_property = dce_virtual_set_property,
 359         .destroy = dce_virtual_destroy,
 360         .force = dce_virtual_force,
 361 };
 362
 363 static int dce_virtual_sw_init(void *handle)
 364 {
 365         int r, i;
 366         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 367
 368         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
 369         if (r)
 370                 return r;
 371
 372         adev->ddev->max_vblank_count = 0;
 373
 374         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 375
 376         adev->ddev->mode_config.max_width = 16384;
 377         adev->ddev->mode_config.max_height = 16384;
 378
 379         adev->ddev->mode_config.preferred_depth = 24;
 380         adev->ddev->mode_config.prefer_shadow = 1;
 381
 382         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
 383
 384         r = amdgpu_display_modeset_create_props(adev);
 385         if (r)
 386                 return r;
 387
 388         adev->ddev->mode_config.max_width = 16384;
 389         adev->ddev->mode_config.max_height = 16384;
 390
 391         /* allocate crtcs, encoders, connectors */
 392         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 393                 r = dce_virtual_crtc_init(adev, i);
 394                 if (r)
 395                         return r;
 396                 r = dce_virtual_connector_encoder_init(adev, i);
 397                 if (r)
 398                         return r;
 399         }
 400
 401         drm_kms_helper_poll_init(adev->ddev);
 402
 403         adev->mode_info.mode_config_initialized = true;
 404         return 0;
 405 }
 406
 407 static int dce_virtual_sw_fini(void *handle)
 408 {
 409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 410
 411         kfree(adev->mode_info.bios_hardcoded_edid);
 412
 413         drm_kms_helper_poll_fini(adev->ddev);
 414
 415         drm_mode_config_cleanup(adev->ddev);
 416         /* clear crtcs pointer to avoid dce irq finish routine access freed data */
 417         memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
 418         adev->mode_info.mode_config_initialized = false;
 419         return 0;
 420 }
 421
 422 static int dce_virtual_hw_init(void *handle)
 423 {
 424         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 425
 426         switch (adev->asic_type) {
 427 #ifdef CONFIG_DRM_AMDGPU_SI
 428         case CHIP_TAHITI:
 429         case CHIP_PITCAIRN:
 430         case CHIP_VERDE:
 431         case CHIP_OLAND:
 432                 dce_v6_0_disable_dce(adev);
 433                 break;
 434 #endif
 435 #ifdef CONFIG_DRM_AMDGPU_CIK
 436         case CHIP_BONAIRE:
 437         case CHIP_HAWAII:
 438         case CHIP_KAVERI:
 439         case CHIP_KABINI:
 440         case CHIP_MULLINS:
 441                 dce_v8_0_disable_dce(adev);
 442                 break;
 443 #endif
 444         case CHIP_FIJI:
 445         case CHIP_TONGA:
 446                 dce_v10_0_disable_dce(adev);
 447                 break;
 448         case CHIP_CARRIZO:
 449         case CHIP_STONEY:
 450         case CHIP_POLARIS10:
 451         case CHIP_POLARIS11:
 452         case CHIP_VEGAM:
 453                 dce_v11_0_disable_dce(adev);
 454                 break;
 455         case CHIP_TOPAZ:
 456 #ifdef CONFIG_DRM_AMDGPU_SI
 457         case CHIP_HAINAN:
 458 #endif
 459                 /* no DCE */
 460                 break;
 461         default:
 462                 break;
 463         }
 464         return 0;
 465 }
 466
 467 static int dce_virtual_hw_fini(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470         int i = 0;
 471
 472         for (i = 0; i<adev->mode_info.num_crtc; i++)
 473                 if (adev->mode_info.crtcs[i])
 474                         dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
 475
 476         return 0;
 477 }
 478
 479 static int dce_virtual_suspend(void *handle)
 480 {
 481         return dce_virtual_hw_fini(handle);
 482 }
 483
 484 static int dce_virtual_resume(void *handle)
 485 {
 486         return dce_virtual_hw_init(handle);
 487 }
 488
 489 static bool dce_virtual_is_idle(void *handle)
 490 {
 491         return true;
 492 }
 493
 494 static int dce_virtual_wait_for_idle(void *handle)
 495 {
 496         return 0;
 497 }
 498
 499 static int dce_virtual_soft_reset(void *handle)
 500 {
 501         return 0;
 502 }
 503
 504 static int dce_virtual_set_clockgating_state(void *handle,
 505                                           enum amd_clockgating_state state)
 506 {
 507         return 0;
 508 }
 509
 510 static int dce_virtual_set_powergating_state(void *handle,
 511                                           enum amd_powergating_state state)
 512 {
 513         return 0;
 514 }
 515
 516 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 517         .name = "dce_virtual",
 518         .early_init = dce_virtual_early_init,
 519         .late_init = NULL,
 520         .sw_init = dce_virtual_sw_init,
 521         .sw_fini = dce_virtual_sw_fini,
 522         .hw_init = dce_virtual_hw_init,
 523         .hw_fini = dce_virtual_hw_fini,
 524         .suspend = dce_virtual_suspend,
 525         .resume = dce_virtual_resume,
 526         .is_idle = dce_virtual_is_idle,
 527         .wait_for_idle = dce_virtual_wait_for_idle,
 528         .soft_reset = dce_virtual_soft_reset,
 529         .set_clockgating_state = dce_virtual_set_clockgating_state,
 530         .set_powergating_state = dce_virtual_set_powergating_state,
 531 };
 532
 533 /* these are handled by the primary encoders */
 534 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 535 {
 536         return;
 537 }
 538
 539 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 540 {
 541         return;
 542 }
 543
 544 static void
 545 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 546                              struct drm_display_mode *mode,
 547                              struct drm_display_mode *adjusted_mode)
 548 {
 549         return;
 550 }
 551
 552 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 553 {
 554         return;
 555 }
 556
 557 static void
 558 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 559 {
 560         return;
 561 }
 562
 563 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 564                                     const struct drm_display_mode *mode,
 565                                     struct drm_display_mode *adjusted_mode)
 566 {
 567         return true;
 568 }
 569
 570 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 571         .dpms = dce_virtual_encoder_dpms,
 572         .mode_fixup = dce_virtual_encoder_mode_fixup,
 573         .prepare = dce_virtual_encoder_prepare,
 574         .mode_set = dce_virtual_encoder_mode_set,
 575         .commit = dce_virtual_encoder_commit,
 576         .disable = dce_virtual_encoder_disable,
 577 };
 578
 579 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 580 {
 581         drm_encoder_cleanup(encoder);
 582         kfree(encoder);
 583 }
 584
 585 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 586         .destroy = dce_virtual_encoder_destroy,
 587 };
 588
 589 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 590                                               int index)
 591 {
 592         struct drm_encoder *encoder;
 593         struct drm_connector *connector;
 594
 595         /* add a new encoder */
 596         encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 597         if (!encoder)
 598                 return -ENOMEM;
 599         encoder->possible_crtcs = 1 << index;
 600         drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
 601                          DRM_MODE_ENCODER_VIRTUAL, NULL);
 602         drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 603
 604         connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 605         if (!connector) {
 606                 kfree(encoder);
 607                 return -ENOMEM;
 608         }
 609
 610         /* add a new connector */
 611         drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
 612                            DRM_MODE_CONNECTOR_VIRTUAL);
 613         drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 614         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 615         connector->interlace_allowed = false;
 616         connector->doublescan_allowed = false;
 617
 618         /* link them */
 619         drm_connector_attach_encoder(connector, encoder);
 620
 621         return 0;
 622 }
 623
 624 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 625         .bandwidth_update = &dce_virtual_bandwidth_update,
 626         .vblank_get_counter = &dce_virtual_vblank_get_counter,
 627         .backlight_set_level = NULL,
 628         .backlight_get_level = NULL,
 629         .hpd_sense = &dce_virtual_hpd_sense,
 630         .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 631         .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 632         .page_flip = &dce_virtual_page_flip,
 633         .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 634         .add_encoder = NULL,
 635         .add_connector = NULL,
 636 };
 637
 638 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 639 {
 640         adev->mode_info.funcs = &dce_virtual_display_funcs;
 641 }
 642
 643 static int dce_virtual_pageflip(struct amdgpu_device *adev,
 644                                 unsigned crtc_id)
 645 {
 646         unsigned long flags;
 647         struct amdgpu_crtc *amdgpu_crtc;
 648         struct amdgpu_flip_work *works;
 649
 650         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 651
 652         if (crtc_id >= adev->mode_info.num_crtc) {
 653                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 654                 return -EINVAL;
 655         }
 656
 657         /* IRQ could occur when in initial stage */
 658         if (amdgpu_crtc == NULL)
 659                 return 0;
 660
 661         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 662         works = amdgpu_crtc->pflip_works;
 663         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 664                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 665                         "AMDGPU_FLIP_SUBMITTED(%d)\n",
 666                         amdgpu_crtc->pflip_status,
 667                         AMDGPU_FLIP_SUBMITTED);
 668                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 669                 return 0;
 670         }
 671
 672         /* page flip completed. clean up */
 673         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 674         amdgpu_crtc->pflip_works = NULL;
 675
 676         /* wakeup usersapce */
 677         if (works->event)
 678                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 679
 680         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 681
 682         drm_crtc_vblank_put(&amdgpu_crtc->base);
 683         amdgpu_bo_unref(&works->old_abo);
 684         kfree(works->shared);
 685         kfree(works);
 686
 687         return 0;
 688 }
 689
 690 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 691 {
 692         struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 693                                                        struct amdgpu_crtc, vblank_timer);
 694         struct drm_device *ddev = amdgpu_crtc->base.dev;
 695         struct amdgpu_device *adev = ddev->dev_private;
 696
 697         drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 698         dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 699         hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
 700                       HRTIMER_MODE_REL);
 701
 702         return HRTIMER_NORESTART;
 703 }
 704
 705 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 706                                                         int crtc,
 707                                                         enum amdgpu_interrupt_state state)
 708 {
 709         if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
 710                 DRM_DEBUG("invalid crtc %d\n", crtc);
 711                 return;
 712         }
 713
 714         if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 715                 DRM_DEBUG("Enable software vsync timer\n");
 716                 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
 717                              CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 718                 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
 719                                     DCE_VIRTUAL_VBLANK_PERIOD);
 720                 adev->mode_info.crtcs[crtc]->vblank_timer.function =
 721                         dce_virtual_vblank_timer_handle;
 722                 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
 723                               DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
 724         } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 725                 DRM_DEBUG("Disable software vsync timer\n");
 726                 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
 727         }
 728
 729         adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 730         DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 731 }
 732
 733
 734 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 735                                           struct amdgpu_irq_src *source,
 736                                           unsigned type,
 737                                           enum amdgpu_interrupt_state state)
 738 {
 739         if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 740                 return -EINVAL;
 741
 742         dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 743
 744         return 0;
 745 }
 746
 747 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 748         .set = dce_virtual_set_crtc_irq_state,
 749         .process = NULL,
 750 };
 751
 752 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 753 {
 754         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
 755         adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 756 }
 757
 758 const struct amdgpu_ip_block_version dce_virtual_ip_block =
 759 {
 760         .type = AMD_IP_BLOCK_TYPE_DCE,
 761         .major = 1,
 762         .minor = 0,
 763         .rev = 0,
 764         .funcs = &dce_virtual_ip_funcs,
 765 };