drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26
  27 #include <linux/firmware.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_pm.h"
  33 #include "amdgpu_vcn.h"
  34 #include "soc15d.h"
  35
  36 /* Firmware Names */
  37 #define FIRMWARE_RAVEN          "/*(DEBLOBBED)*/"
  38 #define FIRMWARE_PICASSO        "/*(DEBLOBBED)*/"
  39 #define FIRMWARE_RAVEN2         "/*(DEBLOBBED)*/"
  40 #define FIRMWARE_ARCTURUS       "/*(DEBLOBBED)*/"
  41 #define FIRMWARE_RENOIR         "/*(DEBLOBBED)*/"
  42 #define FIRMWARE_NAVI10         "/*(DEBLOBBED)*/"
  43 #define FIRMWARE_NAVI14         "/*(DEBLOBBED)*/"
  44 #define FIRMWARE_NAVI12         "/*(DEBLOBBED)*/"
  45
  46 /*(DEBLOBBED)*/
  47
  48 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
  49
  50 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
  51 {
  52         unsigned long bo_size;
  53         const char *fw_name;
  54         const struct common_firmware_header *hdr;
  55         unsigned char fw_check;
  56         int i, r;
  57
  58         INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
  59
  60         switch (adev->asic_type) {
  61         case CHIP_RAVEN:
  62                 if (adev->rev_id >= 8)
  63                         fw_name = FIRMWARE_RAVEN2;
  64                 else if (adev->pdev->device == 0x15d8)
  65                         fw_name = FIRMWARE_PICASSO;
  66                 else
  67                         fw_name = FIRMWARE_RAVEN;
  68                 break;
  69         case CHIP_ARCTURUS:
  70                 fw_name = FIRMWARE_ARCTURUS;
  71                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
  72                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
  73                         adev->vcn.indirect_sram = true;
  74                 break;
  75         case CHIP_RENOIR:
  76                 fw_name = FIRMWARE_RENOIR;
  77                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
  78                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
  79                         adev->vcn.indirect_sram = true;
  80                 break;
  81         case CHIP_NAVI10:
  82                 fw_name = FIRMWARE_NAVI10;
  83                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
  84                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
  85                         adev->vcn.indirect_sram = true;
  86                 break;
  87         case CHIP_NAVI14:
  88                 fw_name = FIRMWARE_NAVI14;
  89                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
  90                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
  91                         adev->vcn.indirect_sram = true;
  92                 break;
  93         case CHIP_NAVI12:
  94                 fw_name = FIRMWARE_NAVI12;
  95                 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
  96                     (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
  97                         adev->vcn.indirect_sram = true;
  98                 break;
  99         default:
 100                 return -EINVAL;
 101         }
 102
 103         r = reject_firmware(&adev->vcn.fw, fw_name, adev->dev);
 104         if (r) {
 105                 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
 106                         fw_name);
 107                 return r;
 108         }
 109
 110         r = amdgpu_ucode_validate(adev->vcn.fw);
 111         if (r) {
 112                 dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
 113                         fw_name);
 114                 release_firmware(adev->vcn.fw);
 115                 adev->vcn.fw = NULL;
 116                 return r;
 117         }
 118
 119         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 120         adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
 121
 122         /* Bit 20-23, it is encode major and non-zero for new naming convention.
 123          * This field is part of version minor and DRM_DISABLED_FLAG in old naming
 124          * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
 125          * is zero in old naming convention, this field is always zero so far.
 126          * These four bits are used to tell which naming convention is present.
 127          */
 128         fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
 129         if (fw_check) {
 130                 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
 131
 132                 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
 133                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
 134                 enc_major = fw_check;
 135                 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
 136                 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
 137                 DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
 138                         enc_major, enc_minor, dec_ver, vep, fw_rev);
 139         } else {
 140                 unsigned int version_major, version_minor, family_id;
 141
 142                 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 143                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 144                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 145                 DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
 146                         version_major, version_minor, family_id);
 147         }
 148
 149         bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
 150         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 151                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 152
 153         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 154                 if (adev->vcn.harvest_config & (1 << i))
 155                         continue;
 156
 157                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 158                                                 AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
 159                                                 &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
 160                 if (r) {
 161                         dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
 162                         return r;
 163                 }
 164
 165                 if (adev->vcn.indirect_sram) {
 166                         r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
 167                                         AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
 168                                         &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
 169                         if (r) {
 170                                 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
 171                                 return r;
 172                         }
 173                 }
 174         }
 175
 176         return 0;
 177 }
 178
 179 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 180 {
 181         int i, j;
 182
 183         cancel_delayed_work_sync(&adev->vcn.idle_work);
 184
 185         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 186                 if (adev->vcn.harvest_config & (1 << j))
 187                         continue;
 188                 if (adev->vcn.indirect_sram) {
 189                         amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
 190                                                   &adev->vcn.inst[j].dpg_sram_gpu_addr,
 191                                                   (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
 192                 }
 193                 kvfree(adev->vcn.inst[j].saved_bo);
 194
 195                 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
 196                                           &adev->vcn.inst[j].gpu_addr,
 197                                           (void **)&adev->vcn.inst[j].cpu_addr);
 198
 199                 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
 200
 201                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
 202                         amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
 203         }
 204
 205         release_firmware(adev->vcn.fw);
 206
 207         return 0;
 208 }
 209
 210 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 211 {
 212         unsigned size;
 213         void *ptr;
 214         int i;
 215
 216         cancel_delayed_work_sync(&adev->vcn.idle_work);
 217
 218         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 219                 if (adev->vcn.harvest_config & (1 << i))
 220                         continue;
 221                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 222                         return 0;
 223
 224                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 225                 ptr = adev->vcn.inst[i].cpu_addr;
 226
 227                 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
 228                 if (!adev->vcn.inst[i].saved_bo)
 229                         return -ENOMEM;
 230
 231                 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
 232         }
 233         return 0;
 234 }
 235
 236 int amdgpu_vcn_resume(struct amdgpu_device *adev)
 237 {
 238         unsigned size;
 239         void *ptr;
 240         int i;
 241
 242         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 243                 if (adev->vcn.harvest_config & (1 << i))
 244                         continue;
 245                 if (adev->vcn.inst[i].vcpu_bo == NULL)
 246                         return -EINVAL;
 247
 248                 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
 249                 ptr = adev->vcn.inst[i].cpu_addr;
 250
 251                 if (adev->vcn.inst[i].saved_bo != NULL) {
 252                         memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
 253                         kvfree(adev->vcn.inst[i].saved_bo);
 254                         adev->vcn.inst[i].saved_bo = NULL;
 255                 } else {
 256                         const struct common_firmware_header *hdr;
 257                         unsigned offset;
 258
 259                         hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 260                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 261                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 262                                 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
 263                                             le32_to_cpu(hdr->ucode_size_bytes));
 264                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 265                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 266                         }
 267                         memset_io(ptr, 0, size);
 268                 }
 269         }
 270         return 0;
 271 }
 272
 273 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 274 {
 275         struct amdgpu_device *adev =
 276                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
 277         unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 278         unsigned int i, j;
 279
 280         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 281                 if (adev->vcn.harvest_config & (1 << j))
 282                         continue;
 283
 284                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 285                         fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
 286                 }
 287
 288                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 289                         struct dpg_pause_state new_state;
 290
 291                         if (fence[j])
 292                                 new_state.fw_based = VCN_DPG_STATE__PAUSE;
 293                         else
 294                                 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 295
 296                         adev->vcn.pause_dpg_mode(adev, j, &new_state);
 297                 }
 298
 299                 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
 300                 fences += fence[j];
 301         }
 302
 303         if (fences == 0) {
 304                 amdgpu_gfx_off_ctrl(adev, true);
 305                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 306                        AMD_PG_STATE_GATE);
 307         } else {
 308                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 309         }
 310 }
 311
 312 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 313 {
 314         struct amdgpu_device *adev = ring->adev;
 315         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 316
 317         if (set_clocks) {
 318                 amdgpu_gfx_off_ctrl(adev, false);
 319                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 320                        AMD_PG_STATE_UNGATE);
 321         }
 322
 323         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)    {
 324                 struct dpg_pause_state new_state;
 325                 unsigned int fences = 0;
 326                 unsigned int i;
 327
 328                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 329                         fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
 330                 }
 331                 if (fences)
 332                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 333                 else
 334                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 335
 336                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
 337                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
 338
 339                 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
 340         }
 341 }
 342
 343 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
 344 {
 345         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 346 }
 347
 348 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
 349 {
 350         struct amdgpu_device *adev = ring->adev;
 351         uint32_t tmp = 0;
 352         unsigned i;
 353         int r;
 354
 355         WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
 356         r = amdgpu_ring_alloc(ring, 3);
 357         if (r)
 358                 return r;
 359         amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
 360         amdgpu_ring_write(ring, 0xDEADBEEF);
 361         amdgpu_ring_commit(ring);
 362         for (i = 0; i < adev->usec_timeout; i++) {
 363                 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
 364                 if (tmp == 0xDEADBEEF)
 365                         break;
 366                 udelay(1);
 367         }
 368
 369         if (i >= adev->usec_timeout)
 370                 r = -ETIMEDOUT;
 371
 372         return r;
 373 }
 374
 375 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
 376                                    struct amdgpu_bo *bo,
 377                                    struct dma_fence **fence)
 378 {
 379         struct amdgpu_device *adev = ring->adev;
 380         struct dma_fence *f = NULL;
 381         struct amdgpu_job *job;
 382         struct amdgpu_ib *ib;
 383         uint64_t addr;
 384         int i, r;
 385
 386         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 387         if (r)
 388                 goto err;
 389
 390         ib = &job->ibs[0];
 391         addr = amdgpu_bo_gpu_offset(bo);
 392         ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
 393         ib->ptr[1] = addr;
 394         ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
 395         ib->ptr[3] = addr >> 32;
 396         ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
 397         ib->ptr[5] = 0;
 398         for (i = 6; i < 16; i += 2) {
 399                 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
 400                 ib->ptr[i+1] = 0;
 401         }
 402         ib->length_dw = 16;
 403
 404         r = amdgpu_job_submit_direct(job, ring, &f);
 405         if (r)
 406                 goto err_free;
 407
 408         amdgpu_bo_fence(bo, f, false);
 409         amdgpu_bo_unreserve(bo);
 410         amdgpu_bo_unref(&bo);
 411
 412         if (fence)
 413                 *fence = dma_fence_get(f);
 414         dma_fence_put(f);
 415
 416         return 0;
 417
 418 err_free:
 419         amdgpu_job_free(job);
 420
 421 err:
 422         amdgpu_bo_unreserve(bo);
 423         amdgpu_bo_unref(&bo);
 424         return r;
 425 }
 426
 427 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 428                               struct dma_fence **fence)
 429 {
 430         struct amdgpu_device *adev = ring->adev;
 431         struct amdgpu_bo *bo = NULL;
 432         uint32_t *msg;
 433         int r, i;
 434
 435         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 436                                       AMDGPU_GEM_DOMAIN_VRAM,
 437                                       &bo, NULL, (void **)&msg);
 438         if (r)
 439                 return r;
 440
 441         msg[0] = cpu_to_le32(0x00000028);
 442         msg[1] = cpu_to_le32(0x00000038);
 443         msg[2] = cpu_to_le32(0x00000001);
 444         msg[3] = cpu_to_le32(0x00000000);
 445         msg[4] = cpu_to_le32(handle);
 446         msg[5] = cpu_to_le32(0x00000000);
 447         msg[6] = cpu_to_le32(0x00000001);
 448         msg[7] = cpu_to_le32(0x00000028);
 449         msg[8] = cpu_to_le32(0x00000010);
 450         msg[9] = cpu_to_le32(0x00000000);
 451         msg[10] = cpu_to_le32(0x00000007);
 452         msg[11] = cpu_to_le32(0x00000000);
 453         msg[12] = cpu_to_le32(0x00000780);
 454         msg[13] = cpu_to_le32(0x00000440);
 455         for (i = 14; i < 1024; ++i)
 456                 msg[i] = cpu_to_le32(0x0);
 457
 458         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 459 }
 460
 461 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 462                                struct dma_fence **fence)
 463 {
 464         struct amdgpu_device *adev = ring->adev;
 465         struct amdgpu_bo *bo = NULL;
 466         uint32_t *msg;
 467         int r, i;
 468
 469         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
 470                                       AMDGPU_GEM_DOMAIN_VRAM,
 471                                       &bo, NULL, (void **)&msg);
 472         if (r)
 473                 return r;
 474
 475         msg[0] = cpu_to_le32(0x00000028);
 476         msg[1] = cpu_to_le32(0x00000018);
 477         msg[2] = cpu_to_le32(0x00000000);
 478         msg[3] = cpu_to_le32(0x00000002);
 479         msg[4] = cpu_to_le32(handle);
 480         msg[5] = cpu_to_le32(0x00000000);
 481         for (i = 6; i < 1024; ++i)
 482                 msg[i] = cpu_to_le32(0x0);
 483
 484         return amdgpu_vcn_dec_send_msg(ring, bo, fence);
 485 }
 486
 487 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 488 {
 489         struct dma_fence *fence;
 490         long r;
 491
 492         r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
 493         if (r)
 494                 goto error;
 495
 496         r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
 497         if (r)
 498                 goto error;
 499
 500         r = dma_fence_wait_timeout(fence, false, timeout);
 501         if (r == 0)
 502                 r = -ETIMEDOUT;
 503         else if (r > 0)
 504                 r = 0;
 505
 506         dma_fence_put(fence);
 507 error:
 508         return r;
 509 }
 510
 511 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
 512 {
 513         struct amdgpu_device *adev = ring->adev;
 514         uint32_t rptr;
 515         unsigned i;
 516         int r;
 517
 518         if (amdgpu_sriov_vf(adev))
 519                 return 0;
 520
 521         r = amdgpu_ring_alloc(ring, 16);
 522         if (r)
 523                 return r;
 524
 525         rptr = amdgpu_ring_get_rptr(ring);
 526
 527         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
 528         amdgpu_ring_commit(ring);
 529
 530         for (i = 0; i < adev->usec_timeout; i++) {
 531                 if (amdgpu_ring_get_rptr(ring) != rptr)
 532                         break;
 533                 udelay(1);
 534         }
 535
 536         if (i >= adev->usec_timeout)
 537                 r = -ETIMEDOUT;
 538
 539         return r;
 540 }
 541
 542 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 543                                          struct amdgpu_bo *bo,
 544                                          struct dma_fence **fence)
 545 {
 546         const unsigned ib_size_dw = 16;
 547         struct amdgpu_job *job;
 548         struct amdgpu_ib *ib;
 549         struct dma_fence *f = NULL;
 550         uint64_t addr;
 551         int i, r;
 552
 553         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 554         if (r)
 555                 return r;
 556
 557         ib = &job->ibs[0];
 558         addr = amdgpu_bo_gpu_offset(bo);
 559
 560         ib->length_dw = 0;
 561         ib->ptr[ib->length_dw++] = 0x00000018;
 562         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 563         ib->ptr[ib->length_dw++] = handle;
 564         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 565         ib->ptr[ib->length_dw++] = addr;
 566         ib->ptr[ib->length_dw++] = 0x0000000b;
 567
 568         ib->ptr[ib->length_dw++] = 0x00000014;
 569         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 570         ib->ptr[ib->length_dw++] = 0x0000001c;
 571         ib->ptr[ib->length_dw++] = 0x00000000;
 572         ib->ptr[ib->length_dw++] = 0x00000000;
 573
 574         ib->ptr[ib->length_dw++] = 0x00000008;
 575         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 576
 577         for (i = ib->length_dw; i < ib_size_dw; ++i)
 578                 ib->ptr[i] = 0x0;
 579
 580         r = amdgpu_job_submit_direct(job, ring, &f);
 581         if (r)
 582                 goto err;
 583
 584         if (fence)
 585                 *fence = dma_fence_get(f);
 586         dma_fence_put(f);
 587
 588         return 0;
 589
 590 err:
 591         amdgpu_job_free(job);
 592         return r;
 593 }
 594
 595 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 596                                           struct amdgpu_bo *bo,
 597                                           struct dma_fence **fence)
 598 {
 599         const unsigned ib_size_dw = 16;
 600         struct amdgpu_job *job;
 601         struct amdgpu_ib *ib;
 602         struct dma_fence *f = NULL;
 603         uint64_t addr;
 604         int i, r;
 605
 606         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 607         if (r)
 608                 return r;
 609
 610         ib = &job->ibs[0];
 611         addr = amdgpu_bo_gpu_offset(bo);
 612
 613         ib->length_dw = 0;
 614         ib->ptr[ib->length_dw++] = 0x00000018;
 615         ib->ptr[ib->length_dw++] = 0x00000001;
 616         ib->ptr[ib->length_dw++] = handle;
 617         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 618         ib->ptr[ib->length_dw++] = addr;
 619         ib->ptr[ib->length_dw++] = 0x0000000b;
 620
 621         ib->ptr[ib->length_dw++] = 0x00000014;
 622         ib->ptr[ib->length_dw++] = 0x00000002;
 623         ib->ptr[ib->length_dw++] = 0x0000001c;
 624         ib->ptr[ib->length_dw++] = 0x00000000;
 625         ib->ptr[ib->length_dw++] = 0x00000000;
 626
 627         ib->ptr[ib->length_dw++] = 0x00000008;
 628         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 629
 630         for (i = ib->length_dw; i < ib_size_dw; ++i)
 631                 ib->ptr[i] = 0x0;
 632
 633         r = amdgpu_job_submit_direct(job, ring, &f);
 634         if (r)
 635                 goto err;
 636
 637         if (fence)
 638                 *fence = dma_fence_get(f);
 639         dma_fence_put(f);
 640
 641         return 0;
 642
 643 err:
 644         amdgpu_job_free(job);
 645         return r;
 646 }
 647
 648 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 649 {
 650         struct dma_fence *fence = NULL;
 651         struct amdgpu_bo *bo = NULL;
 652         long r;
 653
 654         r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
 655                                       AMDGPU_GEM_DOMAIN_VRAM,
 656                                       &bo, NULL, NULL);
 657         if (r)
 658                 return r;
 659
 660         r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
 661         if (r)
 662                 goto error;
 663
 664         r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
 665         if (r)
 666                 goto error;
 667
 668         r = dma_fence_wait_timeout(fence, false, timeout);
 669         if (r == 0)
 670                 r = -ETIMEDOUT;
 671         else if (r > 0)
 672                 r = 0;
 673
 674 error:
 675         dma_fence_put(fence);
 676         amdgpu_bo_unreserve(bo);
 677         amdgpu_bo_unref(&bo);
 678         return r;
 679 }