drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 #include "amdgpu_ras.h"
  43
  44 /* 1 second timeout */
  45 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  46
  47 /* Firmware versions for VI */
  48 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
  49 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
  50 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
  51 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
  52
  53 /* Polaris10/11 firmware version */
  54 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
  55
  56 /* Firmware Names */
  57 #ifdef CONFIG_DRM_AMDGPU_CIK
  58 #define FIRMWARE_BONAIRE        "/*(DEBLOBBED)*/"
  59 #define FIRMWARE_KABINI "/*(DEBLOBBED)*/"
  60 #define FIRMWARE_KAVERI "/*(DEBLOBBED)*/"
  61 #define FIRMWARE_HAWAII "/*(DEBLOBBED)*/"
  62 #define FIRMWARE_MULLINS        "/*(DEBLOBBED)*/"
  63 #endif
  64 #define FIRMWARE_TONGA          "/*(DEBLOBBED)*/"
  65 #define FIRMWARE_CARRIZO        "/*(DEBLOBBED)*/"
  66 #define FIRMWARE_FIJI           "/*(DEBLOBBED)*/"
  67 #define FIRMWARE_STONEY         "/*(DEBLOBBED)*/"
  68 #define FIRMWARE_POLARIS10      "/*(DEBLOBBED)*/"
  69 #define FIRMWARE_POLARIS11      "/*(DEBLOBBED)*/"
  70 #define FIRMWARE_POLARIS12      "/*(DEBLOBBED)*/"
  71 #define FIRMWARE_VEGAM          "/*(DEBLOBBED)*/"
  72
  73 #define FIRMWARE_VEGA10         "/*(DEBLOBBED)*/"
  74 #define FIRMWARE_VEGA12         "/*(DEBLOBBED)*/"
  75 #define FIRMWARE_VEGA20         "/*(DEBLOBBED)*/"
  76
  77 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
  78 #define UVD_GPCOM_VCPU_CMD              0x03c3
  79 #define UVD_GPCOM_VCPU_DATA0    0x03c4
  80 #define UVD_GPCOM_VCPU_DATA1    0x03c5
  81 #define UVD_NO_OP                               0x03ff
  82 #define UVD_BASE_SI                             0x3800
  83
  84 /**
  85  * amdgpu_uvd_cs_ctx - Command submission parser context
  86  *
  87  * Used for emulating virtual memory support on UVD 4.2.
  88  */
  89 struct amdgpu_uvd_cs_ctx {
  90         struct amdgpu_cs_parser *parser;
  91         unsigned reg, count;
  92         unsigned data0, data1;
  93         unsigned idx;
  94         unsigned ib_idx;
  95
  96         /* does the IB has a msg command */
  97         bool has_msg_cmd;
  98
  99         /* minimum buffer sizes */
 100         unsigned *buf_sizes;
 101 };
 102
 103 #ifdef CONFIG_DRM_AMDGPU_CIK
 104 /*(DEBLOBBED)*/
 105 #endif
 106 /*(DEBLOBBED)*/
 107
 108 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 109
 110 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 111 {
 112         unsigned long bo_size;
 113         const char *fw_name;
 114         const struct common_firmware_header *hdr;
 115         unsigned family_id;
 116         int i, j, r;
 117
 118         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 119
 120         switch (adev->asic_type) {
 121 #ifdef CONFIG_DRM_AMDGPU_CIK
 122         case CHIP_BONAIRE:
 123                 fw_name = FIRMWARE_BONAIRE;
 124                 break;
 125         case CHIP_KABINI:
 126                 fw_name = FIRMWARE_KABINI;
 127                 break;
 128         case CHIP_KAVERI:
 129                 fw_name = FIRMWARE_KAVERI;
 130                 break;
 131         case CHIP_HAWAII:
 132                 fw_name = FIRMWARE_HAWAII;
 133                 break;
 134         case CHIP_MULLINS:
 135                 fw_name = FIRMWARE_MULLINS;
 136                 break;
 137 #endif
 138         case CHIP_TONGA:
 139                 fw_name = FIRMWARE_TONGA;
 140                 break;
 141         case CHIP_FIJI:
 142                 fw_name = FIRMWARE_FIJI;
 143                 break;
 144         case CHIP_CARRIZO:
 145                 fw_name = FIRMWARE_CARRIZO;
 146                 break;
 147         case CHIP_STONEY:
 148                 fw_name = FIRMWARE_STONEY;
 149                 break;
 150         case CHIP_POLARIS10:
 151                 fw_name = FIRMWARE_POLARIS10;
 152                 break;
 153         case CHIP_POLARIS11:
 154                 fw_name = FIRMWARE_POLARIS11;
 155                 break;
 156         case CHIP_POLARIS12:
 157                 fw_name = FIRMWARE_POLARIS12;
 158                 break;
 159         case CHIP_VEGA10:
 160                 fw_name = FIRMWARE_VEGA10;
 161                 break;
 162         case CHIP_VEGA12:
 163                 fw_name = FIRMWARE_VEGA12;
 164                 break;
 165         case CHIP_VEGAM:
 166                 fw_name = FIRMWARE_VEGAM;
 167                 break;
 168         case CHIP_VEGA20:
 169                 fw_name = FIRMWARE_VEGA20;
 170                 break;
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         r = reject_firmware(&adev->uvd.fw, fw_name, adev->dev);
 176         if (r) {
 177                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 178                         fw_name);
 179                 return r;
 180         }
 181
 182         r = amdgpu_ucode_validate(adev->uvd.fw);
 183         if (r) {
 184                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 185                         fw_name);
 186                 release_firmware(adev->uvd.fw);
 187                 adev->uvd.fw = NULL;
 188                 return r;
 189         }
 190
 191         /* Set the default UVD handles that the firmware can handle */
 192         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 193
 194         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 195         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 196
 197         if (adev->asic_type < CHIP_VEGA20) {
 198                 unsigned version_major, version_minor;
 199
 200                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 201                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 202                 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 203                         version_major, version_minor, family_id);
 204
 205                 /*
 206                  * Limit the number of UVD handles depending on microcode major
 207                  * and minor versions. The firmware version which has 40 UVD
 208                  * instances support is 1.80. So all subsequent versions should
 209                  * also have the same support.
 210                  */
 211                 if ((version_major > 0x01) ||
 212                     ((version_major == 0x01) && (version_minor >= 0x50)))
 213                         adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 214
 215                 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 216                                         (family_id << 8));
 217
 218                 if ((adev->asic_type == CHIP_POLARIS10 ||
 219                      adev->asic_type == CHIP_POLARIS11) &&
 220                     (adev->uvd.fw_version < FW_1_66_16))
 221                         DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
 222                                   version_major, version_minor);
 223         } else {
 224                 unsigned int enc_major, enc_minor, dec_minor;
 225
 226                 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 227                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
 228                 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
 229                 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
 230                         enc_major, enc_minor, dec_minor, family_id);
 231
 232                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 233
 234                 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
 235         }
 236
 237         bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 238                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 239         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 240                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 241
 242         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 243                 if (adev->uvd.harvest_config & (1 << j))
 244                         continue;
 245                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 246                                             AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
 247                                             &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
 248                 if (r) {
 249                         dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 250                         return r;
 251                 }
 252         }
 253
 254         for (i = 0; i < adev->uvd.max_handles; ++i) {
 255                 atomic_set(&adev->uvd.handles[i], 0);
 256                 adev->uvd.filp[i] = NULL;
 257         }
 258
 259         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 260         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 261                 adev->uvd.address_64_bit = true;
 262
 263         switch (adev->asic_type) {
 264         case CHIP_TONGA:
 265                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
 266                 break;
 267         case CHIP_CARRIZO:
 268                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
 269                 break;
 270         case CHIP_FIJI:
 271                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
 272                 break;
 273         case CHIP_STONEY:
 274                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
 275                 break;
 276         default:
 277                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
 278         }
 279
 280         return 0;
 281 }
 282
 283 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 284 {
 285         int i, j;
 286
 287         cancel_delayed_work_sync(&adev->uvd.idle_work);
 288         drm_sched_entity_destroy(&adev->uvd.entity);
 289
 290         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 291                 if (adev->uvd.harvest_config & (1 << j))
 292                         continue;
 293                 kvfree(adev->uvd.inst[j].saved_bo);
 294
 295                 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
 296                                       &adev->uvd.inst[j].gpu_addr,
 297                                       (void **)&adev->uvd.inst[j].cpu_addr);
 298
 299                 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
 300
 301                 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
 302                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 303         }
 304         release_firmware(adev->uvd.fw);
 305
 306         return 0;
 307 }
 308
 309 /**
 310  * amdgpu_uvd_entity_init - init entity
 311  *
 312  * @adev: amdgpu_device pointer
 313  *
 314  */
 315 int amdgpu_uvd_entity_init(struct amdgpu_device *adev)
 316 {
 317         struct amdgpu_ring *ring;
 318         struct drm_gpu_scheduler *sched;
 319         int r;
 320
 321         ring = &adev->uvd.inst[0].ring;
 322         sched = &ring->sched;
 323         r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,
 324                                   &sched, 1, NULL);
 325         if (r) {
 326                 DRM_ERROR("Failed setting up UVD kernel entity.\n");
 327                 return r;
 328         }
 329
 330         return 0;
 331 }
 332
 333 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 334 {
 335         unsigned size;
 336         void *ptr;
 337         int i, j;
 338         bool in_ras_intr = amdgpu_ras_intr_triggered();
 339
 340         cancel_delayed_work_sync(&adev->uvd.idle_work);
 341
 342         /* only valid for physical mode */
 343         if (adev->asic_type < CHIP_POLARIS10) {
 344                 for (i = 0; i < adev->uvd.max_handles; ++i)
 345                         if (atomic_read(&adev->uvd.handles[i]))
 346                                 break;
 347
 348                 if (i == adev->uvd.max_handles)
 349                         return 0;
 350         }
 351
 352         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 353                 if (adev->uvd.harvest_config & (1 << j))
 354                         continue;
 355                 if (adev->uvd.inst[j].vcpu_bo == NULL)
 356                         continue;
 357
 358                 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
 359                 ptr = adev->uvd.inst[j].cpu_addr;
 360
 361                 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);
 362                 if (!adev->uvd.inst[j].saved_bo)
 363                         return -ENOMEM;
 364
 365                 /* re-write 0 since err_event_athub will corrupt VCPU buffer */
 366                 if (in_ras_intr)
 367                         memset(adev->uvd.inst[j].saved_bo, 0, size);
 368                 else
 369                         memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
 370         }
 371
 372         if (in_ras_intr)
 373                 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n");
 374
 375         return 0;
 376 }
 377
 378 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 379 {
 380         unsigned size;
 381         void *ptr;
 382         int i;
 383
 384         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 385                 if (adev->uvd.harvest_config & (1 << i))
 386                         continue;
 387                 if (adev->uvd.inst[i].vcpu_bo == NULL)
 388                         return -EINVAL;
 389
 390                 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
 391                 ptr = adev->uvd.inst[i].cpu_addr;
 392
 393                 if (adev->uvd.inst[i].saved_bo != NULL) {
 394                         memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
 395                         kvfree(adev->uvd.inst[i].saved_bo);
 396                         adev->uvd.inst[i].saved_bo = NULL;
 397                 } else {
 398                         const struct common_firmware_header *hdr;
 399                         unsigned offset;
 400
 401                         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 402                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 403                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 404                                 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
 405                                             le32_to_cpu(hdr->ucode_size_bytes));
 406                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 407                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 408                         }
 409                         memset_io(ptr, 0, size);
 410                         /* to restore uvd fence seq */
 411                         amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
 412                 }
 413         }
 414         return 0;
 415 }
 416
 417 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 418 {
 419         struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
 420         int i, r;
 421
 422         for (i = 0; i < adev->uvd.max_handles; ++i) {
 423                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 424
 425                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 426                         struct dma_fence *fence;
 427
 428                         r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
 429                                                        &fence);
 430                         if (r) {
 431                                 DRM_ERROR("Error destroying UVD %d!\n", r);
 432                                 continue;
 433                         }
 434
 435                         dma_fence_wait(fence, false);
 436                         dma_fence_put(fence);
 437
 438                         adev->uvd.filp[i] = NULL;
 439                         atomic_set(&adev->uvd.handles[i], 0);
 440                 }
 441         }
 442 }
 443
 444 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
 445 {
 446         int i;
 447         for (i = 0; i < abo->placement.num_placement; ++i) {
 448                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 449                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 450         }
 451 }
 452
 453 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
 454 {
 455         uint32_t lo, hi;
 456         uint64_t addr;
 457
 458         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 459         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 460         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 461
 462         return addr;
 463 }
 464
 465 /**
 466  * amdgpu_uvd_cs_pass1 - first parsing round
 467  *
 468  * @ctx: UVD parser context
 469  *
 470  * Make sure UVD message and feedback buffers are in VRAM and
 471  * nobody is violating an 256MB boundary.
 472  */
 473 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 474 {
 475         struct ttm_operation_ctx tctx = { false, false };
 476         struct amdgpu_bo_va_mapping *mapping;
 477         struct amdgpu_bo *bo;
 478         uint32_t cmd;
 479         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 480         int r = 0;
 481
 482         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 483         if (r) {
 484                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 485                 return r;
 486         }
 487
 488         if (!ctx->parser->adev->uvd.address_64_bit) {
 489                 /* check if it's a message or feedback command */
 490                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 491                 if (cmd == 0x0 || cmd == 0x3) {
 492                         /* yes, force it into VRAM */
 493                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 494                         amdgpu_bo_placement_from_domain(bo, domain);
 495                 }
 496                 amdgpu_uvd_force_into_uvd_segment(bo);
 497
 498                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
 499         }
 500
 501         return r;
 502 }
 503
 504 /**
 505  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 506  *
 507  * @msg: pointer to message structure
 508  * @buf_sizes: returned buffer sizes
 509  *
 510  * Peek into the decode message and calculate the necessary buffer sizes.
 511  */
 512 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
 513         unsigned buf_sizes[])
 514 {
 515         unsigned stream_type = msg[4];
 516         unsigned width = msg[6];
 517         unsigned height = msg[7];
 518         unsigned dpb_size = msg[9];
 519         unsigned pitch = msg[28];
 520         unsigned level = msg[57];
 521
 522         unsigned width_in_mb = width / 16;
 523         unsigned height_in_mb = ALIGN(height / 16, 2);
 524         unsigned fs_in_mb = width_in_mb * height_in_mb;
 525
 526         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 527         unsigned min_ctx_size = ~0;
 528
 529         image_size = width * height;
 530         image_size += image_size / 2;
 531         image_size = ALIGN(image_size, 1024);
 532
 533         switch (stream_type) {
 534         case 0: /* H264 */
 535                 switch(level) {
 536                 case 30:
 537                         num_dpb_buffer = 8100 / fs_in_mb;
 538                         break;
 539                 case 31:
 540                         num_dpb_buffer = 18000 / fs_in_mb;
 541                         break;
 542                 case 32:
 543                         num_dpb_buffer = 20480 / fs_in_mb;
 544                         break;
 545                 case 41:
 546                         num_dpb_buffer = 32768 / fs_in_mb;
 547                         break;
 548                 case 42:
 549                         num_dpb_buffer = 34816 / fs_in_mb;
 550                         break;
 551                 case 50:
 552                         num_dpb_buffer = 110400 / fs_in_mb;
 553                         break;
 554                 case 51:
 555                         num_dpb_buffer = 184320 / fs_in_mb;
 556                         break;
 557                 default:
 558                         num_dpb_buffer = 184320 / fs_in_mb;
 559                         break;
 560                 }
 561                 num_dpb_buffer++;
 562                 if (num_dpb_buffer > 17)
 563                         num_dpb_buffer = 17;
 564
 565                 /* reference picture buffer */
 566                 min_dpb_size = image_size * num_dpb_buffer;
 567
 568                 /* macroblock context buffer */
 569                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 570
 571                 /* IT surface buffer */
 572                 min_dpb_size += width_in_mb * height_in_mb * 32;
 573                 break;
 574
 575         case 1: /* VC1 */
 576
 577                 /* reference picture buffer */
 578                 min_dpb_size = image_size * 3;
 579
 580                 /* CONTEXT_BUFFER */
 581                 min_dpb_size += width_in_mb * height_in_mb * 128;
 582
 583                 /* IT surface buffer */
 584                 min_dpb_size += width_in_mb * 64;
 585
 586                 /* DB surface buffer */
 587                 min_dpb_size += width_in_mb * 128;
 588
 589                 /* BP */
 590                 tmp = max(width_in_mb, height_in_mb);
 591                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 592                 break;
 593
 594         case 3: /* MPEG2 */
 595
 596                 /* reference picture buffer */
 597                 min_dpb_size = image_size * 3;
 598                 break;
 599
 600         case 4: /* MPEG4 */
 601
 602                 /* reference picture buffer */
 603                 min_dpb_size = image_size * 3;
 604
 605                 /* CM */
 606                 min_dpb_size += width_in_mb * height_in_mb * 64;
 607
 608                 /* IT surface buffer */
 609                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 610                 break;
 611
 612         case 7: /* H264 Perf */
 613                 switch(level) {
 614                 case 30:
 615                         num_dpb_buffer = 8100 / fs_in_mb;
 616                         break;
 617                 case 31:
 618                         num_dpb_buffer = 18000 / fs_in_mb;
 619                         break;
 620                 case 32:
 621                         num_dpb_buffer = 20480 / fs_in_mb;
 622                         break;
 623                 case 41:
 624                         num_dpb_buffer = 32768 / fs_in_mb;
 625                         break;
 626                 case 42:
 627                         num_dpb_buffer = 34816 / fs_in_mb;
 628                         break;
 629                 case 50:
 630                         num_dpb_buffer = 110400 / fs_in_mb;
 631                         break;
 632                 case 51:
 633                         num_dpb_buffer = 184320 / fs_in_mb;
 634                         break;
 635                 default:
 636                         num_dpb_buffer = 184320 / fs_in_mb;
 637                         break;
 638                 }
 639                 num_dpb_buffer++;
 640                 if (num_dpb_buffer > 17)
 641                         num_dpb_buffer = 17;
 642
 643                 /* reference picture buffer */
 644                 min_dpb_size = image_size * num_dpb_buffer;
 645
 646                 if (!adev->uvd.use_ctx_buf){
 647                         /* macroblock context buffer */
 648                         min_dpb_size +=
 649                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 650
 651                         /* IT surface buffer */
 652                         min_dpb_size += width_in_mb * height_in_mb * 32;
 653                 } else {
 654                         /* macroblock context buffer */
 655                         min_ctx_size =
 656                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 657                 }
 658                 break;
 659
 660         case 8: /* MJPEG */
 661                 min_dpb_size = 0;
 662                 break;
 663
 664         case 16: /* H265 */
 665                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 666                 image_size = ALIGN(image_size, 256);
 667
 668                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 669                 min_dpb_size = image_size * num_dpb_buffer;
 670                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 671                                            * 16 * num_dpb_buffer + 52 * 1024;
 672                 break;
 673
 674         default:
 675                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 676                 return -EINVAL;
 677         }
 678
 679         if (width > pitch) {
 680                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 681                 return -EINVAL;
 682         }
 683
 684         if (dpb_size < min_dpb_size) {
 685                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 686                           dpb_size, min_dpb_size);
 687                 return -EINVAL;
 688         }
 689
 690         buf_sizes[0x1] = dpb_size;
 691         buf_sizes[0x2] = image_size;
 692         buf_sizes[0x4] = min_ctx_size;
 693         /* store image width to adjust nb memory pstate */
 694         adev->uvd.decode_image_width = width;
 695         return 0;
 696 }
 697
 698 /**
 699  * amdgpu_uvd_cs_msg - handle UVD message
 700  *
 701  * @ctx: UVD parser context
 702  * @bo: buffer object containing the message
 703  * @offset: offset into the buffer object
 704  *
 705  * Peek into the UVD message and extract the session id.
 706  * Make sure that we don't open up to many sessions.
 707  */
 708 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 709                              struct amdgpu_bo *bo, unsigned offset)
 710 {
 711         struct amdgpu_device *adev = ctx->parser->adev;
 712         int32_t *msg, msg_type, handle;
 713         void *ptr;
 714         long r;
 715         int i;
 716
 717         if (offset & 0x3F) {
 718                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 719                 return -EINVAL;
 720         }
 721
 722         r = amdgpu_bo_kmap(bo, &ptr);
 723         if (r) {
 724                 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
 725                 return r;
 726         }
 727
 728         msg = ptr + offset;
 729
 730         msg_type = msg[1];
 731         handle = msg[2];
 732
 733         if (handle == 0) {
 734                 DRM_ERROR("Invalid UVD handle!\n");
 735                 return -EINVAL;
 736         }
 737
 738         switch (msg_type) {
 739         case 0:
 740                 /* it's a create msg, calc image size (width * height) */
 741                 amdgpu_bo_kunmap(bo);
 742
 743                 /* try to alloc a new handle */
 744                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 745                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 746                                 DRM_ERROR(")Handle 0x%x already in use!\n",
 747                                           handle);
 748                                 return -EINVAL;
 749                         }
 750
 751                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 752                                 adev->uvd.filp[i] = ctx->parser->filp;
 753                                 return 0;
 754                         }
 755                 }
 756
 757                 DRM_ERROR("No more free UVD handles!\n");
 758                 return -ENOSPC;
 759
 760         case 1:
 761                 /* it's a decode msg, calc buffer sizes */
 762                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
 763                 amdgpu_bo_kunmap(bo);
 764                 if (r)
 765                         return r;
 766
 767                 /* validate the handle */
 768                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 769                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 770                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 771                                         DRM_ERROR("UVD handle collision detected!\n");
 772                                         return -EINVAL;
 773                                 }
 774                                 return 0;
 775                         }
 776                 }
 777
 778                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 779                 return -ENOENT;
 780
 781         case 2:
 782                 /* it's a destroy msg, free the handle */
 783                 for (i = 0; i < adev->uvd.max_handles; ++i)
 784                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 785                 amdgpu_bo_kunmap(bo);
 786                 return 0;
 787
 788         default:
 789                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 790                 return -EINVAL;
 791         }
 792         BUG();
 793         return -EINVAL;
 794 }
 795
 796 /**
 797  * amdgpu_uvd_cs_pass2 - second parsing round
 798  *
 799  * @ctx: UVD parser context
 800  *
 801  * Patch buffer addresses, make sure buffer sizes are correct.
 802  */
 803 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 804 {
 805         struct amdgpu_bo_va_mapping *mapping;
 806         struct amdgpu_bo *bo;
 807         uint32_t cmd;
 808         uint64_t start, end;
 809         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 810         int r;
 811
 812         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 813         if (r) {
 814                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 815                 return r;
 816         }
 817
 818         start = amdgpu_bo_gpu_offset(bo);
 819
 820         end = (mapping->last + 1 - mapping->start);
 821         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 822
 823         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 824         start += addr;
 825
 826         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 827                             lower_32_bits(start));
 828         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 829                             upper_32_bits(start));
 830
 831         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 832         if (cmd < 0x4) {
 833                 if ((end - start) < ctx->buf_sizes[cmd]) {
 834                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 835                                   (unsigned)(end - start),
 836                                   ctx->buf_sizes[cmd]);
 837                         return -EINVAL;
 838                 }
 839
 840         } else if (cmd == 0x206) {
 841                 if ((end - start) < ctx->buf_sizes[4]) {
 842                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 843                                           (unsigned)(end - start),
 844                                           ctx->buf_sizes[4]);
 845                         return -EINVAL;
 846                 }
 847         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 848                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 849                 return -EINVAL;
 850         }
 851
 852         if (!ctx->parser->adev->uvd.address_64_bit) {
 853                 if ((start >> 28) != ((end - 1) >> 28)) {
 854                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 855                                   start, end);
 856                         return -EINVAL;
 857                 }
 858
 859                 if ((cmd == 0 || cmd == 0x3) &&
 860                     (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
 861                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 862                                   start, end);
 863                         return -EINVAL;
 864                 }
 865         }
 866
 867         if (cmd == 0) {
 868                 ctx->has_msg_cmd = true;
 869                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 870                 if (r)
 871                         return r;
 872         } else if (!ctx->has_msg_cmd) {
 873                 DRM_ERROR("Message needed before other commands are send!\n");
 874                 return -EINVAL;
 875         }
 876
 877         return 0;
 878 }
 879
 880 /**
 881  * amdgpu_uvd_cs_reg - parse register writes
 882  *
 883  * @ctx: UVD parser context
 884  * @cb: callback function
 885  *
 886  * Parse the register writes, call cb on each complete command.
 887  */
 888 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 889                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 890 {
 891         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 892         int i, r;
 893
 894         ctx->idx++;
 895         for (i = 0; i <= ctx->count; ++i) {
 896                 unsigned reg = ctx->reg + i;
 897
 898                 if (ctx->idx >= ib->length_dw) {
 899                         DRM_ERROR("Register command after end of CS!\n");
 900                         return -EINVAL;
 901                 }
 902
 903                 switch (reg) {
 904                 case mmUVD_GPCOM_VCPU_DATA0:
 905                         ctx->data0 = ctx->idx;
 906                         break;
 907                 case mmUVD_GPCOM_VCPU_DATA1:
 908                         ctx->data1 = ctx->idx;
 909                         break;
 910                 case mmUVD_GPCOM_VCPU_CMD:
 911                         r = cb(ctx);
 912                         if (r)
 913                                 return r;
 914                         break;
 915                 case mmUVD_ENGINE_CNTL:
 916                 case mmUVD_NO_OP:
 917                         break;
 918                 default:
 919                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 920                         return -EINVAL;
 921                 }
 922                 ctx->idx++;
 923         }
 924         return 0;
 925 }
 926
 927 /**
 928  * amdgpu_uvd_cs_packets - parse UVD packets
 929  *
 930  * @ctx: UVD parser context
 931  * @cb: callback function
 932  *
 933  * Parse the command stream packets.
 934  */
 935 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 936                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 937 {
 938         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 939         int r;
 940
 941         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 942                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 943                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 944                 switch (type) {
 945                 case PACKET_TYPE0:
 946                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 947                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 948                         r = amdgpu_uvd_cs_reg(ctx, cb);
 949                         if (r)
 950                                 return r;
 951                         break;
 952                 case PACKET_TYPE2:
 953                         ++ctx->idx;
 954                         break;
 955                 default:
 956                         DRM_ERROR("Unknown packet type %d !\n", type);
 957                         return -EINVAL;
 958                 }
 959         }
 960         return 0;
 961 }
 962
 963 /**
 964  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 965  *
 966  * @parser: Command submission parser context
 967  *
 968  * Parse the command stream, patch in addresses as necessary.
 969  */
 970 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 971 {
 972         struct amdgpu_uvd_cs_ctx ctx = {};
 973         unsigned buf_sizes[] = {
 974                 [0x00000000]    =       2048,
 975                 [0x00000001]    =       0xFFFFFFFF,
 976                 [0x00000002]    =       0xFFFFFFFF,
 977                 [0x00000003]    =       2048,
 978                 [0x00000004]    =       0xFFFFFFFF,
 979         };
 980         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 981         int r;
 982
 983         parser->job->vm = NULL;
 984         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 985
 986         if (ib->length_dw % 16) {
 987                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 988                           ib->length_dw);
 989                 return -EINVAL;
 990         }
 991
 992         ctx.parser = parser;
 993         ctx.buf_sizes = buf_sizes;
 994         ctx.ib_idx = ib_idx;
 995
 996         /* first round only required on chips without UVD 64 bit address support */
 997         if (!parser->adev->uvd.address_64_bit) {
 998                 /* first round, make sure the buffers are actually in the UVD segment */
 999                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
1000                 if (r)
1001                         return r;
1002         }
1003
1004         /* second round, patch buffer addresses into the command stream */
1005         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
1006         if (r)
1007                 return r;
1008
1009         if (!ctx.has_msg_cmd) {
1010                 DRM_ERROR("UVD-IBs need a msg command!\n");
1011                 return -EINVAL;
1012         }
1013
1014         return 0;
1015 }
1016
1017 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1018                                bool direct, struct dma_fence **fence)
1019 {
1020         struct amdgpu_device *adev = ring->adev;
1021         struct dma_fence *f = NULL;
1022         struct amdgpu_job *job;
1023         struct amdgpu_ib *ib;
1024         uint32_t data[4];
1025         uint64_t addr;
1026         long r;
1027         int i;
1028         unsigned offset_idx = 0;
1029         unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1030
1031         amdgpu_bo_kunmap(bo);
1032         amdgpu_bo_unpin(bo);
1033
1034         if (!ring->adev->uvd.address_64_bit) {
1035                 struct ttm_operation_ctx ctx = { true, false };
1036
1037                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1038                 amdgpu_uvd_force_into_uvd_segment(bo);
1039                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1040                 if (r)
1041                         goto err;
1042         }
1043
1044         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1045         if (r)
1046                 goto err;
1047
1048         if (adev->asic_type >= CHIP_VEGA10) {
1049                 offset_idx = 1 + ring->me;
1050                 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1051                 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1052         }
1053
1054         data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1055         data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1056         data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1057         data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1058
1059         ib = &job->ibs[0];
1060         addr = amdgpu_bo_gpu_offset(bo);
1061         ib->ptr[0] = data[0];
1062         ib->ptr[1] = addr;
1063         ib->ptr[2] = data[1];
1064         ib->ptr[3] = addr >> 32;
1065         ib->ptr[4] = data[2];
1066         ib->ptr[5] = 0;
1067         for (i = 6; i < 16; i += 2) {
1068                 ib->ptr[i] = data[3];
1069                 ib->ptr[i+1] = 0;
1070         }
1071         ib->length_dw = 16;
1072
1073         if (direct) {
1074                 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
1075                                                         true, false,
1076                                                         msecs_to_jiffies(10));
1077                 if (r == 0)
1078                         r = -ETIMEDOUT;
1079                 if (r < 0)
1080                         goto err_free;
1081
1082                 r = amdgpu_job_submit_direct(job, ring, &f);
1083                 if (r)
1084                         goto err_free;
1085         } else {
1086                 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv,
1087                                      AMDGPU_SYNC_ALWAYS,
1088                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1089                 if (r)
1090                         goto err_free;
1091
1092                 r = amdgpu_job_submit(job, &adev->uvd.entity,
1093                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1094                 if (r)
1095                         goto err_free;
1096         }
1097
1098         amdgpu_bo_fence(bo, f, false);
1099         amdgpu_bo_unreserve(bo);
1100         amdgpu_bo_unref(&bo);
1101
1102         if (fence)
1103                 *fence = dma_fence_get(f);
1104         dma_fence_put(f);
1105
1106         return 0;
1107
1108 err_free:
1109         amdgpu_job_free(job);
1110
1111 err:
1112         amdgpu_bo_unreserve(bo);
1113         amdgpu_bo_unref(&bo);
1114         return r;
1115 }
1116
1117 /* multiple fence commands without any stream commands in between can
1118    crash the vcpu so just try to emmit a dummy create/destroy msg to
1119    avoid this */
1120 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1121                               struct dma_fence **fence)
1122 {
1123         struct amdgpu_device *adev = ring->adev;
1124         struct amdgpu_bo *bo = NULL;
1125         uint32_t *msg;
1126         int r, i;
1127
1128         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1129                                       AMDGPU_GEM_DOMAIN_VRAM,
1130                                       &bo, NULL, (void **)&msg);
1131         if (r)
1132                 return r;
1133
1134         /* stitch together an UVD create msg */
1135         msg[0] = cpu_to_le32(0x00000de4);
1136         msg[1] = cpu_to_le32(0x00000000);
1137         msg[2] = cpu_to_le32(handle);
1138         msg[3] = cpu_to_le32(0x00000000);
1139         msg[4] = cpu_to_le32(0x00000000);
1140         msg[5] = cpu_to_le32(0x00000000);
1141         msg[6] = cpu_to_le32(0x00000000);
1142         msg[7] = cpu_to_le32(0x00000780);
1143         msg[8] = cpu_to_le32(0x00000440);
1144         msg[9] = cpu_to_le32(0x00000000);
1145         msg[10] = cpu_to_le32(0x01b37000);
1146         for (i = 11; i < 1024; ++i)
1147                 msg[i] = cpu_to_le32(0x0);
1148
1149         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1150 }
1151
1152 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1153                                bool direct, struct dma_fence **fence)
1154 {
1155         struct amdgpu_device *adev = ring->adev;
1156         struct amdgpu_bo *bo = NULL;
1157         uint32_t *msg;
1158         int r, i;
1159
1160         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1161                                       AMDGPU_GEM_DOMAIN_VRAM,
1162                                       &bo, NULL, (void **)&msg);
1163         if (r)
1164                 return r;
1165
1166         /* stitch together an UVD destroy msg */
1167         msg[0] = cpu_to_le32(0x00000de4);
1168         msg[1] = cpu_to_le32(0x00000002);
1169         msg[2] = cpu_to_le32(handle);
1170         msg[3] = cpu_to_le32(0x00000000);
1171         for (i = 4; i < 1024; ++i)
1172                 msg[i] = cpu_to_le32(0x0);
1173
1174         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1175 }
1176
1177 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1178 {
1179         struct amdgpu_device *adev =
1180                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1181         unsigned fences = 0, i, j;
1182
1183         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1184                 if (adev->uvd.harvest_config & (1 << i))
1185                         continue;
1186                 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1187                 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1188                         fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1189                 }
1190         }
1191
1192         if (fences == 0) {
1193                 if (adev->pm.dpm_enabled) {
1194                         amdgpu_dpm_enable_uvd(adev, false);
1195                 } else {
1196                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1197                         /* shutdown the UVD block */
1198                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1199                                                                AMD_PG_STATE_GATE);
1200                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1201                                                                AMD_CG_STATE_GATE);
1202                 }
1203         } else {
1204                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1205         }
1206 }
1207
1208 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1209 {
1210         struct amdgpu_device *adev = ring->adev;
1211         bool set_clocks;
1212
1213         if (amdgpu_sriov_vf(adev))
1214                 return;
1215
1216         set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1217         if (set_clocks) {
1218                 if (adev->pm.dpm_enabled) {
1219                         amdgpu_dpm_enable_uvd(adev, true);
1220                 } else {
1221                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1222                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1223                                                                AMD_CG_STATE_UNGATE);
1224                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1225                                                                AMD_PG_STATE_UNGATE);
1226                 }
1227         }
1228 }
1229
1230 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1231 {
1232         if (!amdgpu_sriov_vf(ring->adev))
1233                 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1234 }
1235
1236 /**
1237  * amdgpu_uvd_ring_test_ib - test ib execution
1238  *
1239  * @ring: amdgpu_ring pointer
1240  *
1241  * Test if we can successfully execute an IB
1242  */
1243 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1244 {
1245         struct dma_fence *fence;
1246         long r;
1247
1248         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1249         if (r)
1250                 goto error;
1251
1252         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1253         if (r)
1254                 goto error;
1255
1256         r = dma_fence_wait_timeout(fence, false, timeout);
1257         if (r == 0)
1258                 r = -ETIMEDOUT;
1259         else if (r > 0)
1260                 r = 0;
1261
1262         dma_fence_put(fence);
1263
1264 error:
1265         return r;
1266 }
1267
1268 /**
1269  * amdgpu_uvd_used_handles - returns used UVD handles
1270  *
1271  * @adev: amdgpu_device pointer
1272  *
1273  * Returns the number of UVD handles in use
1274  */
1275 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1276 {
1277         unsigned i;
1278         uint32_t used_handles = 0;
1279
1280         for (i = 0; i < adev->uvd.max_handles; ++i) {
1281                 /*
1282                  * Handles can be freed in any order, and not
1283                  * necessarily linear. So we need to count
1284                  * all non-zero handles.
1285                  */
1286                 if (atomic_read(&adev->uvd.handles[i]))
1287                         used_handles++;
1288         }
1289
1290         return used_handles;
1291 }