2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amdgpu_gfx.h"
28 #include "amdgpu_rlc.h"
29 #include "amdgpu_ras.h"
31 /* delay 0.1 second to enable gfx off feature */
32 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
35 * GPU GFX IP block helpers function.
38 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
43 bit += mec * adev->gfx.mec.num_pipe_per_mec
44 * adev->gfx.mec.num_queue_per_pipe;
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
51 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
52 int *mec, int *pipe, int *queue)
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
56 % adev->gfx.mec.num_pipe_per_mec;
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
58 / adev->gfx.mec.num_pipe_per_mec;
62 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
63 int mec, int pipe, int queue)
65 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
66 adev->gfx.mec.queue_bitmap);
69 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
70 int me, int pipe, int queue)
74 bit += me * adev->gfx.me.num_pipe_per_me
75 * adev->gfx.me.num_queue_per_pipe;
76 bit += pipe * adev->gfx.me.num_queue_per_pipe;
82 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
83 int *me, int *pipe, int *queue)
85 *queue = bit % adev->gfx.me.num_queue_per_pipe;
86 *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
87 % adev->gfx.me.num_pipe_per_me;
88 *me = (bit / adev->gfx.me.num_queue_per_pipe)
89 / adev->gfx.me.num_pipe_per_me;
92 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
93 int me, int pipe, int queue)
95 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
96 adev->gfx.me.queue_bitmap);
100 * amdgpu_gfx_scratch_get - Allocate a scratch register
102 * @adev: amdgpu_device pointer
103 * @reg: scratch register mmio offset
105 * Allocate a CP scratch register for use by the driver (all asics).
106 * Returns 0 on success or -EINVAL on failure.
108 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
112 i = ffs(adev->gfx.scratch.free_mask);
113 if (i != 0 && i <= adev->gfx.scratch.num_reg) {
115 adev->gfx.scratch.free_mask &= ~(1u << i);
116 *reg = adev->gfx.scratch.reg_base + i;
123 * amdgpu_gfx_scratch_free - Free a scratch register
125 * @adev: amdgpu_device pointer
126 * @reg: scratch register mmio offset
128 * Free a CP scratch register allocated for use by the driver (all asics)
130 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
132 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
136 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
138 * @mask: array in which the per-shader array disable masks will be stored
139 * @max_se: number of SEs
140 * @max_sh: number of SHs
142 * The bitmask of CUs to be disabled in the shader array determined by se and
143 * sh is stored in mask[se * max_sh + sh].
145 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
150 memset(mask, 0, sizeof(*mask) * max_se * max_sh);
152 if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
155 p = amdgpu_disable_cu;
158 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
160 DRM_ERROR("amdgpu: could not parse disable_cu\n");
164 if (se < max_se && sh < max_sh && cu < 16) {
165 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
166 mask[se * max_sh + sh] |= 1u << cu;
168 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
172 next = strchr(p, ',');
179 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
181 if (amdgpu_compute_multipipe != -1) {
182 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
183 amdgpu_compute_multipipe);
184 return amdgpu_compute_multipipe == 1;
187 /* FIXME: spreading the queues across pipes causes perf regressions
188 * on POLARIS11 compute workloads */
189 if (adev->asic_type == CHIP_POLARIS11)
192 return adev->gfx.mec.num_mec > 1;
195 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
198 /* Policy: make queue 0 of each pipe as high priority compute queue */
203 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
205 int i, queue, pipe, mec;
206 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
208 /* policy for amdgpu compute queue ownership */
209 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
210 queue = i % adev->gfx.mec.num_queue_per_pipe;
211 pipe = (i / adev->gfx.mec.num_queue_per_pipe)
212 % adev->gfx.mec.num_pipe_per_mec;
213 mec = (i / adev->gfx.mec.num_queue_per_pipe)
214 / adev->gfx.mec.num_pipe_per_mec;
216 /* we've run out of HW */
217 if (mec >= adev->gfx.mec.num_mec)
220 if (multipipe_policy) {
221 /* policy: amdgpu owns the first two queues of the first MEC */
222 if (mec == 0 && queue < 2)
223 set_bit(i, adev->gfx.mec.queue_bitmap);
225 /* policy: amdgpu owns all queues in the first pipe */
226 if (mec == 0 && pipe == 0)
227 set_bit(i, adev->gfx.mec.queue_bitmap);
231 /* update the number of active compute rings */
232 adev->gfx.num_compute_rings =
233 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
235 /* If you hit this case and edited the policy, you probably just
236 * need to increase AMDGPU_MAX_COMPUTE_RINGS */
237 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS))
238 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
241 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
245 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) {
246 queue = i % adev->gfx.me.num_queue_per_pipe;
247 me = (i / adev->gfx.me.num_queue_per_pipe)
248 / adev->gfx.me.num_pipe_per_me;
250 if (me >= adev->gfx.me.num_me)
252 /* policy: amdgpu owns the first queue per pipe at this stage
253 * will extend to mulitple queues per pipe later */
254 if (me == 0 && queue < 1)
255 set_bit(i, adev->gfx.me.queue_bitmap);
258 /* update the number of active graphics rings */
259 adev->gfx.num_gfx_rings =
260 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
263 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
264 struct amdgpu_ring *ring)
267 int mec, pipe, queue;
269 queue_bit = adev->gfx.mec.num_mec
270 * adev->gfx.mec.num_pipe_per_mec
271 * adev->gfx.mec.num_queue_per_pipe;
273 while (queue_bit-- >= 0) {
274 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
277 amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
280 * 1. Using pipes 2/3 from MEC 2 seems cause problems.
281 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
282 * only can be issued on queue 0.
284 if ((mec == 1 && pipe > 1) || queue != 0)
294 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
298 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
299 struct amdgpu_ring *ring,
300 struct amdgpu_irq_src *irq)
302 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
305 spin_lock_init(&kiq->ring_lock);
307 r = amdgpu_device_wb_get(adev, &kiq->reg_val_offs);
312 ring->ring_obj = NULL;
313 ring->use_doorbell = true;
314 ring->doorbell_index = adev->doorbell_index.kiq;
316 r = amdgpu_gfx_kiq_acquire(adev, ring);
320 ring->eop_gpu_addr = kiq->eop_gpu_addr;
321 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);
322 r = amdgpu_ring_init(adev, ring, 1024,
323 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0);
325 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
330 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
332 amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
333 amdgpu_ring_fini(ring);
336 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev)
338 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
340 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
343 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
348 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
350 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
351 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
352 &kiq->eop_gpu_addr, (void **)&hpd);
354 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
358 memset(hpd, 0, hpd_size);
360 r = amdgpu_bo_reserve(kiq->eop_obj, true);
361 if (unlikely(r != 0))
362 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
363 amdgpu_bo_kunmap(kiq->eop_obj);
364 amdgpu_bo_unreserve(kiq->eop_obj);
369 /* create MQD for each compute/gfx queue */
370 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
373 struct amdgpu_ring *ring = NULL;
376 /* create MQD for KIQ */
377 ring = &adev->gfx.kiq.ring;
378 if (!ring->mqd_obj) {
379 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
380 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
381 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
382 * KIQ MQD no matter SRIOV or Bare-metal
384 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
385 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
386 &ring->mqd_gpu_addr, &ring->mqd_ptr);
388 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
392 /* prepare MQD backup */
393 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL);
394 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS])
395 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
398 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
399 /* create MQD for each KGQ */
400 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
401 ring = &adev->gfx.gfx_ring[i];
402 if (!ring->mqd_obj) {
403 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
404 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
405 &ring->mqd_gpu_addr, &ring->mqd_ptr);
407 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
411 /* prepare MQD backup */
412 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
413 if (!adev->gfx.me.mqd_backup[i])
414 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
419 /* create MQD for each KCQ */
420 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
421 ring = &adev->gfx.compute_ring[i];
422 if (!ring->mqd_obj) {
423 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
424 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
425 &ring->mqd_gpu_addr, &ring->mqd_ptr);
427 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
431 /* prepare MQD backup */
432 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
433 if (!adev->gfx.mec.mqd_backup[i])
434 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
441 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev)
443 struct amdgpu_ring *ring = NULL;
446 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
447 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
448 ring = &adev->gfx.gfx_ring[i];
449 kfree(adev->gfx.me.mqd_backup[i]);
450 amdgpu_bo_free_kernel(&ring->mqd_obj,
456 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
457 ring = &adev->gfx.compute_ring[i];
458 kfree(adev->gfx.mec.mqd_backup[i]);
459 amdgpu_bo_free_kernel(&ring->mqd_obj,
464 ring = &adev->gfx.kiq.ring;
465 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
466 amdgpu_bo_free_kernel(&ring->mqd_obj,
471 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
473 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
474 struct amdgpu_ring *kiq_ring = &kiq->ring;
477 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
480 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
481 adev->gfx.num_compute_rings))
484 for (i = 0; i < adev->gfx.num_compute_rings; i++)
485 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i],
488 return amdgpu_ring_test_helper(kiq_ring);
491 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
493 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
494 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
495 uint64_t queue_mask = 0;
498 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
501 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
502 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
505 /* This situation may be hit in the future if a new HW
506 * generation exposes more than 64 queues. If so, the
507 * definition of queue_mask needs updating */
508 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
509 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
513 queue_mask |= (1ull << i);
516 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
519 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
520 adev->gfx.num_compute_rings +
521 kiq->pmf->set_resources_size);
523 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
527 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
528 for (i = 0; i < adev->gfx.num_compute_rings; i++)
529 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
531 r = amdgpu_ring_test_helper(kiq_ring);
533 DRM_ERROR("KCQ enable failed\n");
538 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
540 * @adev: amdgpu_device pointer
541 * @bool enable true: enable gfx off feature, false: disable gfx off feature
543 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
544 * 2. other client can send request to disable gfx off feature, the request should be honored.
545 * 3. other client can cancel their request of disable gfx off feature
546 * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
549 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
551 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
554 mutex_lock(&adev->gfx.gfx_off_mutex);
557 adev->gfx.gfx_off_req_count++;
558 else if (adev->gfx.gfx_off_req_count > 0)
559 adev->gfx.gfx_off_req_count--;
561 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) {
562 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE);
563 } else if (!enable && adev->gfx.gfx_off_state) {
564 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false))
565 adev->gfx.gfx_off_state = false;
568 mutex_unlock(&adev->gfx.gfx_off_mutex);
571 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
574 struct ras_fs_if fs_info = {
575 .sysfs_name = "gfx_err_count",
577 struct ras_ih_if ih_info = {
578 .cb = amdgpu_gfx_process_ras_data_cb,
581 if (!adev->gfx.ras_if) {
582 adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
583 if (!adev->gfx.ras_if)
585 adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
586 adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
587 adev->gfx.ras_if->sub_block_index = 0;
588 strcpy(adev->gfx.ras_if->name, "gfx");
590 fs_info.head = ih_info.head = *adev->gfx.ras_if;
592 r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
597 if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
598 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
602 /* free gfx ras_if if ras is not supported */
609 amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
611 kfree(adev->gfx.ras_if);
612 adev->gfx.ras_if = NULL;
616 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
618 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
620 struct ras_common_if *ras_if = adev->gfx.ras_if;
621 struct ras_ih_if ih_info = {
623 .cb = amdgpu_gfx_process_ras_data_cb,
626 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
631 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
633 struct amdgpu_iv_entry *entry)
635 /* TODO ue will trigger an interrupt.
637 * When “Full RAS” is enabled, the per-IP interrupt sources should
638 * be disabled and the driver should only look for the aggregated
639 * interrupt via sync flood
641 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
642 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
643 if (adev->gfx.funcs->query_ras_error_count)
644 adev->gfx.funcs->query_ras_error_count(adev, err_data);
645 amdgpu_ras_reset_gpu(adev);
647 return AMDGPU_RAS_SUCCESS;
650 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
651 struct amdgpu_irq_src *source,
652 struct amdgpu_iv_entry *entry)
654 struct ras_common_if *ras_if = adev->gfx.ras_if;
655 struct ras_dispatch_if ih_data = {
662 ih_data.head = *ras_if;
664 DRM_ERROR("CP ECC ERROR IRQ\n");
665 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
669 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
671 signed long r, cnt = 0;
674 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
675 struct amdgpu_ring *ring = &kiq->ring;
677 BUG_ON(!ring->funcs->emit_rreg);
679 spin_lock_irqsave(&kiq->ring_lock, flags);
680 amdgpu_ring_alloc(ring, 32);
681 amdgpu_ring_emit_rreg(ring, reg);
682 amdgpu_fence_emit_polling(ring, &seq);
683 amdgpu_ring_commit(ring);
684 spin_unlock_irqrestore(&kiq->ring_lock, flags);
686 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
688 /* don't wait anymore for gpu reset case because this way may
689 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
690 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
691 * never return if we keep waiting in virt_kiq_rreg, which cause
692 * gpu_recover() hang there.
694 * also don't wait anymore for IRQ context
696 if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
697 goto failed_kiq_read;
700 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
701 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
702 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
705 if (cnt > MAX_KIQ_REG_TRY)
706 goto failed_kiq_read;
708 return adev->wb.wb[kiq->reg_val_offs];
711 pr_err("failed to read reg:%x\n", reg);
715 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
717 signed long r, cnt = 0;
720 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
721 struct amdgpu_ring *ring = &kiq->ring;
723 BUG_ON(!ring->funcs->emit_wreg);
725 spin_lock_irqsave(&kiq->ring_lock, flags);
726 amdgpu_ring_alloc(ring, 32);
727 amdgpu_ring_emit_wreg(ring, reg, v);
728 amdgpu_fence_emit_polling(ring, &seq);
729 amdgpu_ring_commit(ring);
730 spin_unlock_irqrestore(&kiq->ring_lock, flags);
732 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
734 /* don't wait anymore for gpu reset case because this way may
735 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
736 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
737 * never return if we keep waiting in virt_kiq_rreg, which cause
738 * gpu_recover() hang there.
740 * also don't wait anymore for IRQ context
742 if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
743 goto failed_kiq_write;
746 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
748 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
749 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
752 if (cnt > MAX_KIQ_REG_TRY)
753 goto failed_kiq_write;
758 pr_err("failed to write reg:%x\n", reg);