1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
9 #include <linux/list.h>
13 #include <dt-bindings/gpio/gpio.h>
15 #define XILINX_GPIO_MAX_BANK 2
23 struct xilinx_gpio_platdata {
24 struct gpio_regs *regs;
25 int bank_max[XILINX_GPIO_MAX_BANK];
26 int bank_input[XILINX_GPIO_MAX_BANK];
27 int bank_output[XILINX_GPIO_MAX_BANK];
30 static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
31 u32 *bank_pin_num, struct udevice *dev)
33 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
35 /* the first gpio is 0 not 1 */
38 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
39 max_pins = platdata->bank_max[bank];
40 if (pin_num < max_pins) {
41 debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
44 *bank_pin_num = pin_num;
53 static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
56 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
60 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
64 val = readl(&platdata->regs->gpiodata + bank * 2);
66 debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x\n",
67 __func__, (ulong)platdata->regs, value, offset, bank, pin);
70 val = val | (1 << pin);
72 val = val & ~(1 << pin);
74 writel(val, &platdata->regs->gpiodata + bank * 2);
79 static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
81 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
85 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
89 debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
90 (ulong)platdata->regs, offset, bank, pin);
92 val = readl(&platdata->regs->gpiodata + bank * 2);
93 val = !!(val & (1 << pin));
98 static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
100 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
104 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
108 /* Check if all pins are inputs */
109 if (platdata->bank_input[bank])
112 /* Check if all pins are outputs */
113 if (platdata->bank_output[bank])
116 /* FIXME test on dual */
117 val = readl(&platdata->regs->gpiodir + bank * 2);
118 val = !(val & (1 << pin));
120 /* input is 1 in reg but GPIOF_INPUT is 0 */
121 /* output is 0 in reg but GPIOF_OUTPUT is 1 */
126 static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
129 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
133 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
137 /* can't change it if all is input by default */
138 if (platdata->bank_input[bank])
141 xilinx_gpio_set_value(dev, offset, value);
143 if (!platdata->bank_output[bank]) {
144 val = readl(&platdata->regs->gpiodir + bank * 2);
145 val = val & ~(1 << pin);
146 writel(val, &platdata->regs->gpiodir + bank * 2);
152 static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
154 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
158 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
163 if (platdata->bank_input[bank])
166 /* can't change it if all is output by default */
167 if (platdata->bank_output[bank])
170 val = readl(&platdata->regs->gpiodir + bank * 2);
171 val = val | (1 << pin);
172 writel(val, &platdata->regs->gpiodir + bank * 2);
177 static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
178 struct ofnode_phandle_args *args)
180 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
182 desc->offset = args->args[0];
184 debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
185 args->args_count, args->args[0], args->args[1], args->args[2]);
188 * The second cell is channel offset:
189 * 0 is first channel, 8 is second channel
191 * U-Boot driver just combine channels together that's why simply
192 * add amount of pins in second channel if present.
195 if (!platdata->bank_max[1]) {
196 printf("%s: %s has no second channel\n",
197 __func__, dev->name);
201 desc->offset += platdata->bank_max[0];
204 /* The third cell is optional */
205 if (args->args_count > 2)
206 desc->flags = (args->args[2] &
207 GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
209 debug("%s: offset %x, flags %lx\n",
210 __func__, desc->offset, desc->flags);
214 static const struct dm_gpio_ops xilinx_gpio_ops = {
215 .direction_input = xilinx_gpio_direction_input,
216 .direction_output = xilinx_gpio_direction_output,
217 .get_value = xilinx_gpio_get_value,
218 .set_value = xilinx_gpio_set_value,
219 .get_function = xilinx_gpio_get_function,
220 .xlate = xilinx_gpio_xlate,
223 static int xilinx_gpio_probe(struct udevice *dev)
225 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
226 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
228 uc_priv->bank_name = dev->name;
230 uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
235 static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
237 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
240 platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
242 platdata->bank_max[0] = dev_read_u32_default(dev,
243 "xlnx,gpio-width", 0);
244 platdata->bank_input[0] = dev_read_u32_default(dev,
245 "xlnx,all-inputs", 0);
246 platdata->bank_output[0] = dev_read_u32_default(dev,
247 "xlnx,all-outputs", 0);
249 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
251 platdata->bank_max[1] = dev_read_u32_default(dev,
252 "xlnx,gpio2-width", 0);
253 platdata->bank_input[1] = dev_read_u32_default(dev,
254 "xlnx,all-inputs-2", 0);
255 platdata->bank_output[1] = dev_read_u32_default(dev,
256 "xlnx,all-outputs-2", 0);
262 static const struct udevice_id xilinx_gpio_ids[] = {
263 { .compatible = "xlnx,xps-gpio-1.00.a",},
267 U_BOOT_DRIVER(xilinx_gpio) = {
270 .ops = &xilinx_gpio_ops,
271 .of_match = xilinx_gpio_ids,
272 .ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
273 .probe = xilinx_gpio_probe,
274 .platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),