1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
9 #include <linux/list.h>
13 #include <dt-bindings/gpio/gpio.h>
15 #define XILINX_GPIO_MAX_BANK 2
23 struct xilinx_gpio_platdata {
24 struct gpio_regs *regs;
25 int bank_max[XILINX_GPIO_MAX_BANK];
26 int bank_input[XILINX_GPIO_MAX_BANK];
27 int bank_output[XILINX_GPIO_MAX_BANK];
28 u32 dout_default[XILINX_GPIO_MAX_BANK];
31 struct xilinx_gpio_privdata {
32 u32 output_val[XILINX_GPIO_MAX_BANK];
35 static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
36 u32 *bank_pin_num, struct udevice *dev)
38 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
40 /* the first gpio is 0 not 1 */
43 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
44 max_pins = platdata->bank_max[bank];
45 if (pin_num < max_pins) {
46 debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
49 *bank_pin_num = pin_num;
58 static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
61 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
62 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
66 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
70 val = priv->output_val[bank];
72 debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
73 __func__, (ulong)platdata->regs, value, offset, bank, pin, val);
76 val = val | (1 << pin);
78 val = val & ~(1 << pin);
80 writel(val, &platdata->regs->gpiodata + bank * 2);
82 priv->output_val[bank] = val;
87 static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
89 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
90 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
94 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
98 debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
99 (ulong)platdata->regs, offset, bank, pin);
101 if (platdata->bank_output[bank]) {
102 debug("%s: Read saved output value\n", __func__);
103 val = priv->output_val[bank];
105 debug("%s: Read input value from reg\n", __func__);
106 val = readl(&platdata->regs->gpiodata + bank * 2);
109 val = !!(val & (1 << pin));
114 static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
116 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
120 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
124 /* Check if all pins are inputs */
125 if (platdata->bank_input[bank])
128 /* Check if all pins are outputs */
129 if (platdata->bank_output[bank])
132 /* FIXME test on dual */
133 val = readl(&platdata->regs->gpiodir + bank * 2);
134 val = !(val & (1 << pin));
136 /* input is 1 in reg but GPIOF_INPUT is 0 */
137 /* output is 0 in reg but GPIOF_OUTPUT is 1 */
142 static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
145 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
149 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
153 /* can't change it if all is input by default */
154 if (platdata->bank_input[bank])
157 xilinx_gpio_set_value(dev, offset, value);
159 if (!platdata->bank_output[bank]) {
160 val = readl(&platdata->regs->gpiodir + bank * 2);
161 val = val & ~(1 << pin);
162 writel(val, &platdata->regs->gpiodir + bank * 2);
168 static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
170 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
174 ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
179 if (platdata->bank_input[bank])
182 /* can't change it if all is output by default */
183 if (platdata->bank_output[bank])
186 val = readl(&platdata->regs->gpiodir + bank * 2);
187 val = val | (1 << pin);
188 writel(val, &platdata->regs->gpiodir + bank * 2);
193 static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
194 struct ofnode_phandle_args *args)
196 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
198 desc->offset = args->args[0];
200 debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
201 args->args_count, args->args[0], args->args[1], args->args[2]);
204 * The second cell is channel offset:
205 * 0 is first channel, 8 is second channel
207 * U-Boot driver just combine channels together that's why simply
208 * add amount of pins in second channel if present.
211 if (!platdata->bank_max[1]) {
212 printf("%s: %s has no second channel\n",
213 __func__, dev->name);
217 desc->offset += platdata->bank_max[0];
220 /* The third cell is optional */
221 if (args->args_count > 2)
222 desc->flags = (args->args[2] &
223 GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
225 debug("%s: offset %x, flags %lx\n",
226 __func__, desc->offset, desc->flags);
230 static const struct dm_gpio_ops xilinx_gpio_ops = {
231 .direction_input = xilinx_gpio_direction_input,
232 .direction_output = xilinx_gpio_direction_output,
233 .get_value = xilinx_gpio_get_value,
234 .set_value = xilinx_gpio_set_value,
235 .get_function = xilinx_gpio_get_function,
236 .xlate = xilinx_gpio_xlate,
239 static int xilinx_gpio_probe(struct udevice *dev)
241 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
242 struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
243 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
244 const void *label_ptr;
246 label_ptr = dev_read_prop(dev, "label", NULL);
248 uc_priv->bank_name = strdup(label_ptr);
249 if (!uc_priv->bank_name)
252 uc_priv->bank_name = dev->name;
255 uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
257 priv->output_val[0] = platdata->dout_default[0];
259 if (platdata->bank_max[1])
260 priv->output_val[1] = platdata->dout_default[1];
265 static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
267 struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
270 platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
272 platdata->bank_max[0] = dev_read_u32_default(dev,
273 "xlnx,gpio-width", 0);
274 platdata->bank_input[0] = dev_read_u32_default(dev,
275 "xlnx,all-inputs", 0);
276 platdata->bank_output[0] = dev_read_u32_default(dev,
277 "xlnx,all-outputs", 0);
278 platdata->dout_default[0] = dev_read_u32_default(dev,
282 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
284 platdata->bank_max[1] = dev_read_u32_default(dev,
285 "xlnx,gpio2-width", 0);
286 platdata->bank_input[1] = dev_read_u32_default(dev,
287 "xlnx,all-inputs-2", 0);
288 platdata->bank_output[1] = dev_read_u32_default(dev,
289 "xlnx,all-outputs-2", 0);
290 platdata->dout_default[1] = dev_read_u32_default(dev,
291 "xlnx,dout-default-2", 0);
297 static const struct udevice_id xilinx_gpio_ids[] = {
298 { .compatible = "xlnx,xps-gpio-1.00.a",},
302 U_BOOT_DRIVER(xilinx_gpio) = {
305 .ops = &xilinx_gpio_ops,
306 .of_match = xilinx_gpio_ids,
307 .ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
308 .probe = xilinx_gpio_probe,
309 .platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
310 .priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),