3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
6 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * Copyright 2015 ATS Advanced Telematics Systems GmbH
9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/errno.h>
17 #include <asm/arch/stm32.h>
18 #include <asm/arch/gpio.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_STM32F4)
23 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
24 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
25 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
26 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
27 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
28 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
29 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
30 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
31 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
33 static const unsigned long io_base[] = {
34 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
35 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
36 STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
39 struct stm32_gpio_regs {
40 u32 moder; /* GPIO port mode */
41 u32 otyper; /* GPIO port output type */
42 u32 ospeedr; /* GPIO port output speed */
43 u32 pupdr; /* GPIO port pull-up/pull-down */
44 u32 idr; /* GPIO port input data */
45 u32 odr; /* GPIO port output data */
46 u32 bsrr; /* GPIO port bit set/reset */
47 u32 lckr; /* GPIO port configuration lock */
48 u32 afr[2]; /* GPIO alternate function */
51 #define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
52 #define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
53 x->pupd > 2 || x->speed > 3)
55 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
56 const struct stm32_gpio_ctl *ctl)
58 struct stm32_gpio_regs *gpio_regs;
71 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
73 i = (dsc->pin & 0x07) * 4;
74 clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
78 clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
79 clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
80 clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
81 clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
87 #elif defined(CONFIG_STM32F1)
88 #define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
89 #define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
90 #define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
91 #define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
92 #define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
93 #define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
94 #define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
96 static const unsigned long io_base[] = {
97 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
98 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
102 #define STM32_GPIO_CR_MODE_MASK 0x3
103 #define STM32_GPIO_CR_MODE_SHIFT(p) (p * 4)
104 #define STM32_GPIO_CR_CNF_MASK 0x3
105 #define STM32_GPIO_CR_CNF_SHIFT(p) (p * 4 + 2)
107 struct stm32_gpio_regs {
108 u32 crl; /* GPIO port configuration low */
109 u32 crh; /* GPIO port configuration high */
110 u32 idr; /* GPIO port input data */
111 u32 odr; /* GPIO port output data */
112 u32 bsrr; /* GPIO port bit set/reset */
113 u32 brr; /* GPIO port bit reset */
114 u32 lckr; /* GPIO port configuration lock */
117 #define CHECK_DSC(x) (!x || x->port > 6 || x->pin > 15)
118 #define CHECK_CTL(x) (!x || x->mode > 3 || x->icnf > 3 || x->ocnf > 3 || \
121 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
122 const struct stm32_gpio_ctl *ctl)
124 struct stm32_gpio_regs *gpio_regs;
129 if (CHECK_DSC(dsc)) {
133 if (CHECK_CTL(ctl)) {
140 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
143 cr = &gpio_regs->crl;
146 cr = &gpio_regs->crh;
150 clrbits_le32(cr, 0x3 << STM32_GPIO_CR_MODE_SHIFT(crp));
151 setbits_le32(cr, ctl->mode << STM32_GPIO_CR_MODE_SHIFT(crp));
153 clrbits_le32(cr, 0x3 << STM32_GPIO_CR_CNF_SHIFT(crp));
154 /* Inputs set the optional pull up / pull down */
155 if (ctl->mode == STM32_GPIO_MODE_IN) {
156 setbits_le32(cr, ctl->icnf << STM32_GPIO_CR_CNF_SHIFT(crp));
157 clrbits_le32(&gpio_regs->odr, 0x1 << p);
158 setbits_le32(&gpio_regs->odr, ctl->pupd << p);
160 setbits_le32(cr, ctl->ocnf << STM32_GPIO_CR_CNF_SHIFT(crp));
168 #error STM32 family not supported
171 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
173 struct stm32_gpio_regs *gpio_regs;
176 if (CHECK_DSC(dsc)) {
181 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
184 writel(1 << dsc->pin, &gpio_regs->bsrr);
186 writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
193 int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
195 struct stm32_gpio_regs *gpio_regs;
198 if (CHECK_DSC(dsc)) {
203 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
204 rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
209 /* Common GPIO API */
211 int gpio_request(unsigned gpio, const char *label)
216 int gpio_free(unsigned gpio)
221 int gpio_direction_input(unsigned gpio)
223 struct stm32_gpio_dsc dsc;
224 struct stm32_gpio_ctl ctl;
226 dsc.port = stm32_gpio_to_port(gpio);
227 dsc.pin = stm32_gpio_to_pin(gpio);
228 #if defined(CONFIG_STM32F4)
229 ctl.af = STM32_GPIO_AF0;
230 ctl.mode = STM32_GPIO_MODE_IN;
231 ctl.otype = STM32_GPIO_OTYPE_PP;
232 ctl.pupd = STM32_GPIO_PUPD_NO;
233 ctl.speed = STM32_GPIO_SPEED_50M;
234 #elif defined(CONFIG_STM32F1)
235 ctl.mode = STM32_GPIO_MODE_IN;
236 ctl.icnf = STM32_GPIO_ICNF_IN_FLT;
237 ctl.ocnf = STM32_GPIO_OCNF_GP_PP; /* ignored for input */
238 ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for floating */
240 #error STM32 family not supported
243 return stm32_gpio_config(&dsc, &ctl);
246 int gpio_direction_output(unsigned gpio, int value)
248 struct stm32_gpio_dsc dsc;
249 struct stm32_gpio_ctl ctl;
252 dsc.port = stm32_gpio_to_port(gpio);
253 dsc.pin = stm32_gpio_to_pin(gpio);
254 #if defined(CONFIG_STM32F4)
255 ctl.af = STM32_GPIO_AF0;
256 ctl.mode = STM32_GPIO_MODE_OUT;
257 ctl.pupd = STM32_GPIO_PUPD_NO;
258 ctl.speed = STM32_GPIO_SPEED_50M;
259 #elif defined(CONFIG_STM32F1)
260 ctl.mode = STM32_GPIO_MODE_OUT_50M;
261 ctl.ocnf = STM32_GPIO_OCNF_GP_PP;
262 ctl.icnf = STM32_GPIO_ICNF_IN_FLT; /* ignored for output */
263 ctl.pupd = STM32_GPIO_PUPD_UP; /* ignored for output */
265 #error STM32 family not supported
268 res = stm32_gpio_config(&dsc, &ctl);
271 res = stm32_gpout_set(&dsc, value);
276 int gpio_get_value(unsigned gpio)
278 struct stm32_gpio_dsc dsc;
280 dsc.port = stm32_gpio_to_port(gpio);
281 dsc.pin = stm32_gpio_to_pin(gpio);
283 return stm32_gpin_get(&dsc);
286 int gpio_set_value(unsigned gpio, int value)
288 struct stm32_gpio_dsc dsc;
290 dsc.port = stm32_gpio_to_port(gpio);
291 dsc.pin = stm32_gpio_to_pin(gpio);
293 return stm32_gpout_set(&dsc, value);