1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019 SiFive, Inc.
10 #include <asm/arch/gpio.h>
14 #include <linux/bitops.h>
16 static int sifive_gpio_probe(struct udevice *dev)
18 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
19 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
22 sprintf(name, "gpio@%4lx_", (uintptr_t)plat->base);
26 uc_priv->bank_name = str;
29 * Use the gpio count mentioned in device tree,
30 * if not specified in dt, set NR_GPIOS as default
32 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", NR_GPIOS);
37 static void sifive_update_gpio_reg(void *bptr, u32 offset, bool value)
39 void __iomem *ptr = (void __iomem *)bptr;
41 u32 bit = BIT(offset);
45 writel(old | bit, ptr);
47 writel(old & ~bit, ptr);
50 static int sifive_gpio_direction_input(struct udevice *dev, u32 offset)
52 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
53 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
55 if (offset > uc_priv->gpio_count)
58 /* Configure gpio direction as input */
59 sifive_update_gpio_reg(plat->base + GPIO_INPUT_EN, offset, true);
60 sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_EN, offset, false);
65 static int sifive_gpio_direction_output(struct udevice *dev, u32 offset,
68 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
69 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
71 if (offset > uc_priv->gpio_count)
74 /* Configure gpio direction as output */
75 sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_EN, offset, true);
76 sifive_update_gpio_reg(plat->base + GPIO_INPUT_EN, offset, false);
78 /* Set the output state of the pin */
79 sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_VAL, offset, value);
84 static int sifive_gpio_get_value(struct udevice *dev, u32 offset)
86 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
87 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
91 if (offset > uc_priv->gpio_count)
94 /* Get direction of the pin */
95 dir = !(readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset));
98 val = readl(plat->base + GPIO_INPUT_VAL) & BIT(offset);
100 val = readl(plat->base + GPIO_OUTPUT_VAL) & BIT(offset);
102 return val ? HIGH : LOW;
105 static int sifive_gpio_set_value(struct udevice *dev, u32 offset, int value)
107 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
108 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
110 if (offset > uc_priv->gpio_count)
113 sifive_update_gpio_reg(plat->base + GPIO_OUTPUT_VAL, offset, value);
118 static int sifive_gpio_get_function(struct udevice *dev, unsigned int offset)
120 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
121 u32 outdir, indir, val;
122 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
124 if (offset > uc_priv->gpio_count)
127 /* Get direction of the pin */
128 outdir = readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset);
129 indir = readl(plat->base + GPIO_INPUT_EN) & BIT(offset);
132 /* Pin at specified offset is configured as output */
135 /* Pin at specified offset is configured as input */
138 /*The requested GPIO is not set as input or output */
144 static const struct udevice_id sifive_gpio_match[] = {
145 { .compatible = "sifive,gpio0" },
149 static const struct dm_gpio_ops sifive_gpio_ops = {
150 .direction_input = sifive_gpio_direction_input,
151 .direction_output = sifive_gpio_direction_output,
152 .get_value = sifive_gpio_get_value,
153 .set_value = sifive_gpio_set_value,
154 .get_function = sifive_gpio_get_function,
157 static int sifive_gpio_ofdata_to_platdata(struct udevice *dev)
159 struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
162 addr = devfdt_get_addr(dev);
163 if (addr == FDT_ADDR_T_NONE)
166 plat->base = (void *)addr;
170 U_BOOT_DRIVER(gpio_sifive) = {
171 .name = "gpio_sifive",
173 .of_match = sifive_gpio_match,
174 .ofdata_to_platdata = of_match_ptr(sifive_gpio_ofdata_to_platdata),
175 .platdata_auto_alloc_size = sizeof(struct sifive_gpio_platdata),
176 .ops = &sifive_gpio_ops,
177 .probe = sifive_gpio_probe,