1 // SPDX-License-Identifier: GPL-2.0+
3 * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
5 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
11 * The driver's compatible table is borrowed from Linux Kernel,
12 * but now max supported gpio pins is 24 and only PCA953X_TYPE
13 * is supported. PCA957X_TYPE is not supported now.
14 * Also the Polarity Inversion feature is not supported now.
17 * 1. Support PCA957X_TYPE
18 * 2. Support Polarity Inversion
29 #include <dt-bindings/gpio/gpio.h>
31 #define PCA953X_INPUT 0
32 #define PCA953X_OUTPUT 1
33 #define PCA953X_INVERT 2
34 #define PCA953X_DIRECTION 3
36 #define PCA_GPIO_MASK 0x00FF
37 #define PCA_INT 0x0100
38 #define PCA953X_TYPE 0x1000
39 #define PCA957X_TYPE 0x2000
40 #define PCA_TYPE_MASK 0xF000
41 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
45 PCA953X_DIRECTION_OUT,
52 * struct pca953x_info - Data for pca953x
54 * @dev: udevice structure for the device
55 * @addr: i2c slave address
56 * @invert: Polarity inversion or not
57 * @gpio_count: the number of gpio pins that the device supports
58 * @chip_type: indicate the chip type,PCA953X or PCA957X
59 * @bank_count: the number of banks that the device supports
60 * @reg_output: array to hold the value of output registers
61 * @reg_direction: array to hold the value of direction registers
70 u8 reg_output[MAX_BANK];
71 u8 reg_direction[MAX_BANK];
74 static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
77 struct pca953x_info *info = dev_get_platdata(dev);
78 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
79 int off = offset / BANK_SZ;
82 ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
84 dev_err(dev, "%s error\n", __func__);
91 static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
94 struct pca953x_info *info = dev_get_platdata(dev);
95 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
96 int off = offset / BANK_SZ;
100 ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
102 dev_err(dev, "%s error\n", __func__);
111 static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
113 struct pca953x_info *info = dev_get_platdata(dev);
116 if (info->gpio_count <= 8) {
117 ret = dm_i2c_read(dev, reg, val, 1);
118 } else if (info->gpio_count <= 16) {
119 ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
120 } else if (info->gpio_count <= 24) {
122 ret = dm_i2c_read(dev, (reg << 2) | 0x80, val,
124 } else if (info->gpio_count == 40) {
126 ret = dm_i2c_read(dev, (reg << 3) | 0x80, val,
129 dev_err(dev, "Unsupported now\n");
136 static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
138 struct pca953x_info *info = dev_get_platdata(dev);
141 if (info->gpio_count <= 8) {
142 ret = dm_i2c_write(dev, reg, val, 1);
143 } else if (info->gpio_count <= 16) {
144 ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
145 } else if (info->gpio_count <= 24) {
147 ret = dm_i2c_write(dev, (reg << 2) | 0x80, val,
149 } else if (info->gpio_count == 40) {
151 ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count);
159 static int pca953x_is_output(struct udevice *dev, int offset)
161 struct pca953x_info *info = dev_get_platdata(dev);
163 int bank = offset / BANK_SZ;
164 int off = offset % BANK_SZ;
166 /*0: output; 1: input */
167 return !(info->reg_direction[bank] & (1 << off));
170 static int pca953x_get_value(struct udevice *dev, uint offset)
175 int off = offset % BANK_SZ;
177 ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
181 return (val >> off) & 0x1;
184 static int pca953x_set_value(struct udevice *dev, uint offset, int value)
186 struct pca953x_info *info = dev_get_platdata(dev);
187 int bank = offset / BANK_SZ;
188 int off = offset % BANK_SZ;
193 val = info->reg_output[bank] | (1 << off);
195 val = info->reg_output[bank] & ~(1 << off);
197 ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
201 info->reg_output[bank] = val;
206 static int pca953x_set_direction(struct udevice *dev, uint offset, int dir)
208 struct pca953x_info *info = dev_get_platdata(dev);
209 int bank = offset / BANK_SZ;
210 int off = offset % BANK_SZ;
214 if (dir == PCA953X_DIRECTION_IN)
215 val = info->reg_direction[bank] | (1 << off);
217 val = info->reg_direction[bank] & ~(1 << off);
219 ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
223 info->reg_direction[bank] = val;
228 static int pca953x_direction_input(struct udevice *dev, uint offset)
230 return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
233 static int pca953x_direction_output(struct udevice *dev, uint offset, int value)
235 /* Configure output value. */
236 pca953x_set_value(dev, offset, value);
238 /* Configure direction as output. */
239 pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
244 static int pca953x_get_function(struct udevice *dev, uint offset)
246 if (pca953x_is_output(dev, offset))
252 static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
253 struct ofnode_phandle_args *args)
255 desc->offset = args->args[0];
256 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
261 static const struct dm_gpio_ops pca953x_ops = {
262 .direction_input = pca953x_direction_input,
263 .direction_output = pca953x_direction_output,
264 .get_value = pca953x_get_value,
265 .set_value = pca953x_set_value,
266 .get_function = pca953x_get_function,
267 .xlate = pca953x_xlate,
270 static int pca953x_probe(struct udevice *dev)
272 struct pca953x_info *info = dev_get_platdata(dev);
273 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
274 char name[32], label[8], *str;
282 addr = dev_read_addr(dev);
288 driver_data = dev_get_driver_data(dev);
290 info->gpio_count = driver_data & PCA_GPIO_MASK;
291 if (info->gpio_count > MAX_BANK * BANK_SZ) {
292 dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
296 info->chip_type = PCA_CHIP_TYPE(driver_data);
297 if (info->chip_type != PCA953X_TYPE) {
298 dev_err(dev, "Only support PCA953X chip type now.\n");
302 info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
304 ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
306 dev_err(dev, "Error reading output register\n");
310 ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
312 dev_err(dev, "Error reading direction register\n");
316 tmp = dev_read_prop(dev, "label", &size);
319 memcpy(label, tmp, sizeof(label) - 1);
320 label[sizeof(label) - 1] = '\0';
321 snprintf(name, sizeof(name), "%s@%x_", label, info->addr);
323 snprintf(name, sizeof(name), "gpio@%x_", info->addr);
326 /* Clear the polarity registers to no invert */
327 memset(val, 0, MAX_BANK);
328 ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
330 dev_err(dev, "Error writing invert register\n");
337 uc_priv->bank_name = str;
338 uc_priv->gpio_count = info->gpio_count;
340 dev_dbg(dev, "%s is ready\n", str);
345 #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
346 #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
348 static const struct udevice_id pca953x_ids[] = {
349 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
350 { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
351 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
352 { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
353 { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
354 { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
355 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
356 { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
357 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
358 { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
359 { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
360 { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
361 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
362 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
364 { .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
365 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
366 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
367 { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
369 { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
370 { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
371 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
372 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
373 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
375 { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
377 { .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
381 U_BOOT_DRIVER(pca953x) = {
385 .probe = pca953x_probe,
386 .platdata_auto_alloc_size = sizeof(struct pca953x_info),
387 .of_match = pca953x_ids,