1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
5 * Based on the Linux driver version which is:
6 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
18 #include <dm/device-internal.h>
19 #include <dt-bindings/gpio/gpio.h>
21 #define MTK_MAX_BANK 3
22 #define MTK_BANK_WIDTH 32
24 enum mediatek_gpio_reg {
38 static void __iomem *mediatek_gpio_membase;
40 struct mediatek_gpio_platdata {
41 char bank_name[3]; /* Name of bank, e.g. "PA", "PB" etc */
46 static u32 reg_offs(struct mediatek_gpio_platdata *plat, int reg)
48 return (reg * 0x10) + (plat->bank * 0x4);
51 static int mediatek_gpio_get_value(struct udevice *dev, unsigned int offset)
53 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
55 return !!(ioread32(mediatek_gpio_membase +
56 reg_offs(plat, GPIO_REG_DATA)) & BIT(offset));
59 static int mediatek_gpio_set_value(struct udevice *dev, unsigned int offset,
62 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
64 iowrite32(BIT(offset), mediatek_gpio_membase +
65 reg_offs(plat, value ? GPIO_REG_DSET : GPIO_REG_DCLR));
70 static int mediatek_gpio_direction_input(struct udevice *dev, unsigned int offset)
72 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
74 clrbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
80 static int mediatek_gpio_direction_output(struct udevice *dev, unsigned int offset,
83 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
85 setbits_le32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL),
87 mediatek_gpio_set_value(dev, offset, value);
92 static int mediatek_gpio_get_function(struct udevice *dev, unsigned int offset)
94 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
97 t = ioread32(mediatek_gpio_membase + reg_offs(plat, GPIO_REG_CTRL));
104 static const struct dm_gpio_ops gpio_mediatek_ops = {
105 .direction_input = mediatek_gpio_direction_input,
106 .direction_output = mediatek_gpio_direction_output,
107 .get_value = mediatek_gpio_get_value,
108 .set_value = mediatek_gpio_set_value,
109 .get_function = mediatek_gpio_get_function,
112 static int gpio_mediatek_probe(struct udevice *dev)
114 struct mediatek_gpio_platdata *plat = dev_get_platdata(dev);
115 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
117 /* Tell the uclass how many GPIOs we have */
119 uc_priv->gpio_count = plat->gpio_count;
120 uc_priv->bank_name = plat->bank_name;
127 * We have a top-level GPIO device with no actual GPIOs. It has a child
128 * device for each Mediatek bank.
130 static int gpio_mediatek_bind(struct udevice *parent)
132 struct mediatek_gpio_platdata *plat = parent->platdata;
137 /* If this is a child device, there is nothing to do here */
141 mediatek_gpio_membase = dev_remap_addr(parent);
142 if (!mediatek_gpio_membase)
145 for (node = dev_read_first_subnode(parent); ofnode_valid(node);
146 node = dev_read_next_subnode(node)) {
147 struct mediatek_gpio_platdata *plat;
150 plat = calloc(1, sizeof(*plat));
153 plat->bank_name[0] = 'P';
154 plat->bank_name[1] = 'A' + bank;
155 plat->bank_name[2] = '\0';
156 plat->gpio_count = MTK_BANK_WIDTH;
159 ret = device_bind(parent, parent->driver,
160 plat->bank_name, plat, -1, &dev);
171 static const struct udevice_id mediatek_gpio_ids[] = {
172 { .compatible = "mtk,mt7621-gpio" },
176 U_BOOT_DRIVER(gpio_mediatek) = {
177 .name = "gpio_mediatek",
179 .ops = &gpio_mediatek_ops,
180 .of_match = mediatek_gpio_ids,
181 .bind = gpio_mediatek_bind,
182 .probe = gpio_mediatek_probe,