1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs serial gpio driver
5 * Author: <lars.povlsen@microchip.com>
7 * Copyright (c) 2018 Microsemi Corporation
16 #include <dm/device_compat.h>
17 #include <linux/err.h>
19 #define MSCC_SGPIOS_PER_BANK 32
20 #define MSCC_SGPIO_BANK_DEPTH 4
31 struct mscc_sgpio_bf {
36 struct mscc_sgpio_props {
38 struct mscc_sgpio_bf auto_repeat;
39 struct mscc_sgpio_bf port_width;
40 struct mscc_sgpio_bf clk_freq;
41 struct mscc_sgpio_bf bit_source;
44 #define __M(bf) GENMASK((bf).end, (bf).beg)
45 #define __F(bf, x) (__M(bf) & ((x) << (bf).beg))
46 #define __X(bf, x) (((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
48 #define MSCC_M_CFG_SIO_AUTO_REPEAT(p) BIT(p->props->auto_repeat.beg)
49 #define MSCC_F_CFG_SIO_PORT_WIDTH(p, x) __F(p->props->port_width, x)
50 #define MSCC_M_CFG_SIO_PORT_WIDTH(p) __M(p->props->port_width)
51 #define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x) __F(p->props->clk_freq, x)
52 #define MSCC_M_CLOCK_SIO_CLK_FREQ(p) __M(p->props->clk_freq)
53 #define MSCC_F_PORT_CFG_BIT_SOURCE(p, x) __F(p->props->bit_source, x)
54 #define MSCC_X_PORT_CFG_BIT_SOURCE(p, x) __X(p->props->bit_source, x)
56 const struct mscc_sgpio_props props_luton = {
57 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
58 .auto_repeat = { 5, 5 },
59 .port_width = { 2, 3 },
60 .clk_freq = { 0, 11 },
61 .bit_source = { 0, 11 },
64 const struct mscc_sgpio_props props_ocelot = {
65 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
66 .auto_repeat = { 10, 10 },
67 .port_width = { 7, 8 },
68 .clk_freq = { 8, 19 },
69 .bit_source = { 12, 23 },
72 struct mscc_sgpio_priv {
76 u32 mode[MSCC_SGPIOS_PER_BANK];
78 const struct mscc_sgpio_props *props;
81 static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
83 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
88 static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
89 u32 val, u32 rno, u32 off)
91 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
96 static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
97 u32 rno, u32 off, u32 clear, u32 set)
99 u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
101 clrsetbits_le32(reg, clear, set);
104 static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
106 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
108 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
109 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
111 priv->mode[port] |= BIT(bit);
116 static int mscc_sgpio_direction_output(struct udevice *dev,
117 unsigned int gpio, int value)
119 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
120 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
121 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
122 u32 mask = 3 << (3 * bit);
124 debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
125 port, bit, mask, value);
127 value = (value & 3) << (3 * bit);
128 sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
129 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
130 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
131 clrbits_le32(&priv->mode[port], BIT(bit));
136 static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
138 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
139 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
140 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
141 u32 val = priv->mode[port] & BIT(bit);
149 static int mscc_sgpio_set_value(struct udevice *dev,
150 unsigned int gpio, int value)
152 return mscc_sgpio_direction_output(dev, gpio, value);
155 static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
157 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
158 u32 port = gpio % MSCC_SGPIOS_PER_BANK;
159 u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
162 if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
163 ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
165 u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
167 ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
168 ret = !!(ret & (3 << (3 * bit)));
171 debug("get: gpio %d, port %d, bit %d, value %d\n",
172 gpio, port, bit, ret);
176 static int mscc_sgpio_get_count(struct udevice *dev)
178 struct ofnode_phandle_args args;
179 int count = 0, i = 0, ret;
181 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
182 while (ret != -ENOENT) {
183 count += args.args[2];
184 ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
190 static int mscc_sgpio_probe(struct udevice *dev)
192 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
193 struct mscc_sgpio_priv *priv = dev_get_priv(dev);
194 int err, div_clock = 0, port;
198 err = clk_get_by_index(dev, 0, &clk);
200 err = clk_get_rate(&clk);
201 if (IS_ERR_VALUE(err)) {
202 dev_err(dev, "Invalid clk rate\n");
207 dev_err(dev, "Failed to get clock\n");
211 priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
212 priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
213 priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
215 if (priv->clock <= 0 || priv->clock > div_clock) {
216 dev_err(dev, "Invalid frequency %d\n", priv->clock);
220 uc_priv->gpio_count = mscc_sgpio_get_count(dev);
221 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
222 uc_priv->gpio_count);
223 if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
224 (4 * MSCC_SGPIOS_PER_BANK)) {
225 dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
228 priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
229 MSCC_SGPIOS_PER_BANK);
230 debug("probe: gpios = %d, bit-count = %d\n",
231 uc_priv->gpio_count, priv->bitcount);
233 priv->regs = (u32 __iomem *)dev_read_addr(dev);
234 uc_priv->bank_name = "sgpio";
236 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
237 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
238 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
239 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
240 val = div_clock / priv->clock;
241 debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
242 div_clock / 1000, priv->clock / 1000, val);
243 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
244 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
245 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
247 for (port = 0; port < 32; port++)
248 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
249 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
251 debug("probe: sgpio regs = %p\n", priv->regs);
256 static const struct dm_gpio_ops mscc_sgpio_ops = {
257 .direction_input = mscc_sgpio_direction_input,
258 .direction_output = mscc_sgpio_direction_output,
259 .get_function = mscc_sgpio_get_function,
260 .get_value = mscc_sgpio_get_value,
261 .set_value = mscc_sgpio_set_value,
264 static const struct udevice_id mscc_sgpio_ids[] = {
265 { .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
266 { .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
270 U_BOOT_DRIVER(gpio_mscc_sgpio) = {
271 .name = "mscc-sgpio",
273 .of_match = mscc_sgpio_ids,
274 .ops = &mscc_sgpio_ops,
275 .probe = mscc_sgpio_probe,
276 .priv_auto_alloc_size = sizeof(struct mscc_sgpio_priv),