1 // SPDX-License-Identifier: GPL-2.0+
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
6 * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
8 * Copyright 2010 eXMeritus, A Boeing Company
25 struct mpc8xxx_gpio_data {
26 /* The bank's register base in memory */
27 struct ccsr_gpio __iomem *base;
28 /* The address of the registers; used to identify the bank */
30 /* The GPIO count of the bank */
32 /* The GPDAT register cannot be used to determine the value of output
33 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
45 inline u32 gpio_mask(uint gpio)
47 return (1U << (31 - (gpio)));
50 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
52 return in_be32(&base->gpdat) & mask;
55 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
57 return in_be32(&base->gpdir) & mask;
60 static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
62 clrbits_be32(&base->gpdat, gpios);
63 /* GPDIR register 1 -> output */
64 setbits_be32(&base->gpdir, gpios);
67 static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
69 setbits_be32(&base->gpdat, gpios);
70 /* GPDIR register 1 -> output */
71 setbits_be32(&base->gpdir, gpios);
74 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
76 return in_be32(&base->gpodr) & mask;
79 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
82 /* GPODR register 1 -> open drain on */
83 setbits_be32(&base->gpodr, gpios);
86 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
89 /* GPODR register 0 -> open drain off (actively driven) */
90 clrbits_be32(&base->gpodr, gpios);
93 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
95 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
96 u32 mask = gpio_mask(gpio);
98 /* GPDIR register 0 -> input */
99 clrbits_be32(&data->base->gpdir, mask);
104 static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
106 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
109 data->dat_shadow |= gpio_mask(gpio);
110 mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio));
112 data->dat_shadow &= ~gpio_mask(gpio);
113 mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio));
118 static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
121 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
123 /* GPIO 28..31 are input only on MPC5121 */
124 if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
127 return mpc8xxx_gpio_set_value(dev, gpio, value);
130 static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
132 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
134 if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
135 /* Output -> use shadowed value */
136 return !!(data->dat_shadow & gpio_mask(gpio));
139 /* Input -> read value from GPDAT register */
140 return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
143 static int mpc8xxx_gpio_get_open_drain(struct udevice *dev, uint gpio)
145 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
147 return !!mpc8xxx_gpio_open_drain_val(data->base, gpio_mask(gpio));
150 static int mpc8xxx_gpio_set_open_drain(struct udevice *dev, uint gpio,
153 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
156 mpc8xxx_gpio_open_drain_on(data->base, gpio_mask(gpio));
158 mpc8xxx_gpio_open_drain_off(data->base, gpio_mask(gpio));
163 static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
165 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
168 dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
169 return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
172 #if CONFIG_IS_ENABLED(OF_CONTROL)
173 static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
175 struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
179 dev_read_u32_array(dev, "reg", reg, 2);
180 addr = dev_translate_address(dev, reg);
184 plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
190 static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
192 struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
193 struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
194 unsigned long size = plat->size;
195 ulong driver_data = dev_get_driver_data(dev);
200 priv->addr = plat->addr;
201 priv->base = map_sysmem(plat->addr, size);
206 priv->gpio_count = plat->ngpios;
207 priv->dat_shadow = 0;
209 priv->type = driver_data;
214 static int mpc8xxx_gpio_probe(struct udevice *dev)
216 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
217 struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
220 mpc8xxx_gpio_platdata_to_priv(dev);
222 snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
228 uc_priv->bank_name = str;
229 uc_priv->gpio_count = data->gpio_count;
234 static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
235 .direction_input = mpc8xxx_gpio_direction_input,
236 .direction_output = mpc8xxx_gpio_direction_output,
237 .get_value = mpc8xxx_gpio_get_value,
238 .set_value = mpc8xxx_gpio_set_value,
239 .get_open_drain = mpc8xxx_gpio_get_open_drain,
240 .set_open_drain = mpc8xxx_gpio_set_open_drain,
241 .get_function = mpc8xxx_gpio_get_function,
244 static const struct udevice_id mpc8xxx_gpio_ids[] = {
245 { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
246 { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
247 { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
248 { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
249 { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
250 { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
251 { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
255 U_BOOT_DRIVER(gpio_mpc8xxx) = {
256 .name = "gpio_mpc8xxx",
258 .ops = &gpio_mpc8xxx_ops,
259 #if CONFIG_IS_ENABLED(OF_CONTROL)
260 .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
261 .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
262 .of_match = mpc8xxx_gpio_ids,
264 .probe = mpc8xxx_gpio_probe,
265 .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),