1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
17 #include <asm/intel_pinctrl.h>
18 #include <asm/intel_pinctrl_defs.h>
21 #include <asm/arch/gpio.h>
22 #include <dt-bindings/gpio/x86-gpio.h>
24 static int intel_gpio_direction_input(struct udevice *dev, uint offset)
26 struct udevice *pinctrl = dev_get_parent(dev);
27 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
29 pcr_clrsetbits32(pinctrl, config_offset,
30 PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
32 PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
37 static int intel_gpio_direction_output(struct udevice *dev, uint offset,
40 struct udevice *pinctrl = dev_get_parent(dev);
41 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
43 pcr_clrsetbits32(pinctrl, config_offset,
44 PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
45 PAD_CFG0_TX_DISABLE | PAD_CFG0_TX_STATE,
46 PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
47 (value ? PAD_CFG0_TX_STATE : 0));
52 static int intel_gpio_get_value(struct udevice *dev, uint offset)
54 struct udevice *pinctrl = dev_get_parent(dev);
58 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
59 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
61 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
62 if (rx_tx == PAD_CFG0_TX_DISABLE)
63 return reg & PAD_CFG0_RX_STATE ? 1 : 0;
64 else if (rx_tx == PAD_CFG0_RX_DISABLE)
65 return reg & PAD_CFG0_TX_STATE ? 1 : 0;
71 static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
73 struct udevice *pinctrl = dev_get_parent(dev);
74 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
76 pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
77 value ? PAD_CFG0_TX_STATE : 0);
82 static int intel_gpio_get_function(struct udevice *dev, uint offset)
84 struct udevice *pinctrl = dev_get_parent(dev);
88 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
89 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
91 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
92 if (rx_tx == PAD_CFG0_TX_DISABLE)
94 else if (rx_tx == PAD_CFG0_RX_DISABLE)
101 static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
102 struct ofnode_phandle_args *args)
104 struct udevice *pinctrl, *dev;
108 * GPIO numbers are global in the device tree so it doesn't matter
111 gpio = args->args[0];
112 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
114 return log_msg_ret("bad", ret);
115 device_find_first_child(pinctrl, &dev);
117 return log_msg_ret("no child", -ENOENT);
118 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
124 static int intel_gpio_probe(struct udevice *dev)
129 static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
131 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
132 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
133 const struct pad_community *comm = pinctrl_priv->comm;
135 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
136 upriv->bank_name = dev->name;
141 static const struct dm_gpio_ops gpio_intel_ops = {
142 .direction_input = intel_gpio_direction_input,
143 .direction_output = intel_gpio_direction_output,
144 .get_value = intel_gpio_get_value,
145 .set_value = intel_gpio_set_value,
146 .get_function = intel_gpio_get_function,
147 .xlate = intel_gpio_xlate,
150 static const struct udevice_id intel_intel_gpio_ids[] = {
151 { .compatible = "intel,gpio" },
155 U_BOOT_DRIVER(gpio_intel) = {
156 .name = "gpio_intel",
158 .of_match = intel_intel_gpio_ids,
159 .ops = &gpio_intel_ops,
160 .ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
161 .probe = intel_gpio_probe,