1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
16 #include <asm/intel_pinctrl.h>
17 #include <asm/intel_pinctrl_defs.h>
20 #include <asm/arch/gpio.h>
21 #include <dt-bindings/gpio/x86-gpio.h>
23 static int intel_gpio_direction_input(struct udevice *dev, uint offset)
25 struct udevice *pinctrl = dev_get_parent(dev);
26 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
28 pcr_clrsetbits32(pinctrl, config_offset,
29 PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
31 PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE);
36 static int intel_gpio_direction_output(struct udevice *dev, uint offset,
39 struct udevice *pinctrl = dev_get_parent(dev);
40 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
42 pcr_clrsetbits32(pinctrl, config_offset,
43 PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
44 PAD_CFG0_TX_DISABLE | PAD_CFG0_TX_STATE,
45 PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE |
46 (value ? PAD_CFG0_TX_STATE : 0));
51 static int intel_gpio_get_value(struct udevice *dev, uint offset)
53 struct udevice *pinctrl = dev_get_parent(dev);
57 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
58 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
60 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
61 if (rx_tx == PAD_CFG0_TX_DISABLE)
62 return reg & PAD_CFG0_RX_STATE ? 1 : 0;
63 else if (rx_tx == PAD_CFG0_RX_DISABLE)
64 return reg & PAD_CFG0_TX_STATE ? 1 : 0;
70 static int intel_gpio_set_value(struct udevice *dev, unsigned offset, int value)
72 struct udevice *pinctrl = dev_get_parent(dev);
73 uint config_offset = intel_pinctrl_get_config_reg_addr(pinctrl, offset);
75 pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
76 value ? PAD_CFG0_TX_STATE : 0);
81 static int intel_gpio_get_function(struct udevice *dev, uint offset)
83 struct udevice *pinctrl = dev_get_parent(dev);
87 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
88 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
90 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
91 if (rx_tx == PAD_CFG0_TX_DISABLE)
93 else if (rx_tx == PAD_CFG0_RX_DISABLE)
100 static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
101 struct ofnode_phandle_args *args)
103 struct udevice *pinctrl, *dev;
107 * GPIO numbers are global in the device tree so it doesn't matter
110 gpio = args->args[0];
111 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
113 return log_msg_ret("bad", ret);
114 device_find_first_child(pinctrl, &dev);
116 return log_msg_ret("no child", -ENOENT);
117 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
123 static int intel_gpio_probe(struct udevice *dev)
128 static int intel_gpio_ofdata_to_platdata(struct udevice *dev)
130 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
131 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
132 const struct pad_community *comm = pinctrl_priv->comm;
134 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
135 upriv->bank_name = dev->name;
140 static const struct dm_gpio_ops gpio_intel_ops = {
141 .direction_input = intel_gpio_direction_input,
142 .direction_output = intel_gpio_direction_output,
143 .get_value = intel_gpio_get_value,
144 .set_value = intel_gpio_set_value,
145 .get_function = intel_gpio_get_function,
146 .xlate = intel_gpio_xlate,
149 static const struct udevice_id intel_intel_gpio_ids[] = {
150 { .compatible = "intel,gpio" },
154 U_BOOT_DRIVER(gpio_intel) = {
155 .name = "gpio_intel",
157 .of_match = intel_intel_gpio_ids,
158 .ops = &gpio_intel_ops,
159 .ofdata_to_platdata = intel_gpio_ofdata_to_platdata,
160 .probe = intel_gpio_probe,