1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
10 #include <dm/device_compat.h>
11 #include <dm/pinctrl.h>
15 #include <linux/bitops.h>
16 #include "../pinctrl/renesas/sh_pfc.h"
18 #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
19 #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
20 #define GPIO_OUTDT 0x08 /* General Output Register */
21 #define GPIO_INDT 0x0c /* General Input Register */
22 #define GPIO_INTDT 0x10 /* Interrupt Display Register */
23 #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
24 #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
25 #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
26 #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
27 #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
28 #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
29 #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
31 #define RCAR_MAX_GPIO_PER_BANK 32
33 DECLARE_GLOBAL_DATA_PTR;
35 struct rcar_gpio_priv {
40 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
42 struct rcar_gpio_priv *priv = dev_get_priv(dev);
43 const u32 bit = BIT(offset);
46 * Testing on r8a7790 shows that INDT does not show correct pin state
47 * when configured as output, so use OUTDT in case of output pins.
49 if (readl(priv->regs + GPIO_INOUTSEL) & bit)
50 return !!(readl(priv->regs + GPIO_OUTDT) & bit);
52 return !!(readl(priv->regs + GPIO_INDT) & bit);
55 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
58 struct rcar_gpio_priv *priv = dev_get_priv(dev);
61 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
63 clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
68 static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
72 * follow steps in the GPIO documentation for
73 * "Setting General Output Mode" and
74 * "Setting General Input Mode"
77 /* Configure postive logic in POSNEG */
78 clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
80 /* Select "General Input/Output Mode" in IOINTSEL */
81 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
83 /* Select Input Mode or Output Mode in INOUTSEL */
85 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
87 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
90 static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
92 struct rcar_gpio_priv *priv = dev_get_priv(dev);
94 rcar_gpio_set_direction(priv->regs, offset, false);
99 static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
102 struct rcar_gpio_priv *priv = dev_get_priv(dev);
104 /* write GPIO value to output before selecting output mode of pin */
105 rcar_gpio_set_value(dev, offset, value);
106 rcar_gpio_set_direction(priv->regs, offset, true);
111 static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
113 struct rcar_gpio_priv *priv = dev_get_priv(dev);
115 if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
121 static int rcar_gpio_request(struct udevice *dev, unsigned offset,
124 return pinctrl_gpio_request(dev, offset);
127 static int rcar_gpio_free(struct udevice *dev, unsigned offset)
129 return pinctrl_gpio_free(dev, offset);
132 static const struct dm_gpio_ops rcar_gpio_ops = {
133 .request = rcar_gpio_request,
134 .rfree = rcar_gpio_free,
135 .direction_input = rcar_gpio_direction_input,
136 .direction_output = rcar_gpio_direction_output,
137 .get_value = rcar_gpio_get_value,
138 .set_value = rcar_gpio_set_value,
139 .get_function = rcar_gpio_get_function,
142 static int rcar_gpio_probe(struct udevice *dev)
144 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
145 struct rcar_gpio_priv *priv = dev_get_priv(dev);
146 struct fdtdec_phandle_args args;
148 int node = dev_of_offset(dev);
151 priv->regs = (void __iomem *)devfdt_get_addr(dev);
152 uc_priv->bank_name = dev->name;
154 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
156 priv->pfc_offset = ret == 0 ? args.args[1] : -1;
157 uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
159 ret = clk_get_by_index(dev, 0, &clk);
161 dev_err(dev, "Failed to get GPIO bank clock\n");
165 ret = clk_enable(&clk);
168 dev_err(dev, "Failed to enable GPIO bank clock\n");
175 static const struct udevice_id rcar_gpio_ids[] = {
176 { .compatible = "renesas,gpio-r8a7795" },
177 { .compatible = "renesas,gpio-r8a7796" },
178 { .compatible = "renesas,gpio-r8a77965" },
179 { .compatible = "renesas,gpio-r8a77970" },
180 { .compatible = "renesas,gpio-r8a77990" },
181 { .compatible = "renesas,gpio-r8a77995" },
182 { .compatible = "renesas,rcar-gen2-gpio" },
183 { .compatible = "renesas,rcar-gen3-gpio" },
187 U_BOOT_DRIVER(rcar_gpio) = {
190 .of_match = rcar_gpio_ids,
191 .ops = &rcar_gpio_ops,
192 .priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),
193 .probe = rcar_gpio_probe,