1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
12 #include "../pinctrl/renesas/sh_pfc.h"
14 #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
15 #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */
16 #define GPIO_OUTDT 0x08 /* General Output Register */
17 #define GPIO_INDT 0x0c /* General Input Register */
18 #define GPIO_INTDT 0x10 /* Interrupt Display Register */
19 #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */
20 #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */
21 #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */
22 #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */
23 #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */
24 #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */
25 #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
27 #define RCAR_MAX_GPIO_PER_BANK 32
29 DECLARE_GLOBAL_DATA_PTR;
31 struct rcar_gpio_priv {
36 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset)
38 struct rcar_gpio_priv *priv = dev_get_priv(dev);
39 const u32 bit = BIT(offset);
42 * Testing on r8a7790 shows that INDT does not show correct pin state
43 * when configured as output, so use OUTDT in case of output pins.
45 if (readl(priv->regs + GPIO_INOUTSEL) & bit)
46 return !!(readl(priv->regs + GPIO_OUTDT) & bit);
48 return !!(readl(priv->regs + GPIO_INDT) & bit);
51 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset,
54 struct rcar_gpio_priv *priv = dev_get_priv(dev);
57 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
59 clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset));
64 static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
68 * follow steps in the GPIO documentation for
69 * "Setting General Output Mode" and
70 * "Setting General Input Mode"
73 /* Configure postive logic in POSNEG */
74 clrbits_le32(regs + GPIO_POSNEG, BIT(offset));
76 /* Select "General Input/Output Mode" in IOINTSEL */
77 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset));
79 /* Select Input Mode or Output Mode in INOUTSEL */
81 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
83 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset));
86 static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
88 struct rcar_gpio_priv *priv = dev_get_priv(dev);
90 rcar_gpio_set_direction(priv->regs, offset, false);
95 static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
98 struct rcar_gpio_priv *priv = dev_get_priv(dev);
100 /* write GPIO value to output before selecting output mode of pin */
101 rcar_gpio_set_value(dev, offset, value);
102 rcar_gpio_set_direction(priv->regs, offset, true);
107 static int rcar_gpio_get_function(struct udevice *dev, unsigned offset)
109 struct rcar_gpio_priv *priv = dev_get_priv(dev);
111 if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset))
117 static int rcar_gpio_request(struct udevice *dev, unsigned offset,
120 struct rcar_gpio_priv *priv = dev_get_priv(dev);
121 struct udevice *pctldev;
124 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pctldev);
128 return sh_pfc_config_mux_for_gpio(pctldev, priv->pfc_offset + offset);
131 static const struct dm_gpio_ops rcar_gpio_ops = {
132 .request = rcar_gpio_request,
133 .direction_input = rcar_gpio_direction_input,
134 .direction_output = rcar_gpio_direction_output,
135 .get_value = rcar_gpio_get_value,
136 .set_value = rcar_gpio_set_value,
137 .get_function = rcar_gpio_get_function,
140 static int rcar_gpio_probe(struct udevice *dev)
142 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
143 struct rcar_gpio_priv *priv = dev_get_priv(dev);
144 struct fdtdec_phandle_args args;
146 int node = dev_of_offset(dev);
149 priv->regs = (void __iomem *)devfdt_get_addr(dev);
150 uc_priv->bank_name = dev->name;
152 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
154 priv->pfc_offset = ret == 0 ? args.args[1] : -1;
155 uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
157 ret = clk_get_by_index(dev, 0, &clk);
159 dev_err(dev, "Failed to get GPIO bank clock\n");
163 ret = clk_enable(&clk);
166 dev_err(dev, "Failed to enable GPIO bank clock\n");
173 static const struct udevice_id rcar_gpio_ids[] = {
174 { .compatible = "renesas,gpio-r8a7795" },
175 { .compatible = "renesas,gpio-r8a7796" },
176 { .compatible = "renesas,gpio-r8a77965" },
177 { .compatible = "renesas,gpio-r8a77970" },
178 { .compatible = "renesas,gpio-r8a77990" },
179 { .compatible = "renesas,gpio-r8a77995" },
180 { .compatible = "renesas,rcar-gen2-gpio" },
181 { .compatible = "renesas,rcar-gen3-gpio" },
185 U_BOOT_DRIVER(rcar_gpio) = {
188 .of_match = rcar_gpio_ids,
189 .ops = &rcar_gpio_ops,
190 .priv_auto_alloc_size = sizeof(struct rcar_gpio_priv),
191 .probe = rcar_gpio_probe,