2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 static LIST_HEAD(omap_gpio_list);
52 struct list_head node;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
76 int context_loss_count;
78 bool workaround_enabled;
80 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
81 int (*get_context_loss_count)(struct device *dev);
83 struct omap_gpio_reg_offs *regs;
86 #define GPIO_MOD_CTRL_BIT BIT(0)
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
89 #define LINE_USED(line, offset) (line & (BIT(offset)))
91 static void omap_gpio_unmask_irq(struct irq_data *d);
93 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
95 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
96 return container_of(chip, struct gpio_bank, chip);
99 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
102 void __iomem *reg = bank->base;
105 reg += bank->regs->direction;
106 l = readl_relaxed(reg);
111 writel_relaxed(l, reg);
112 bank->context.oe = l;
116 /* set data out value using dedicate set/clear register */
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
120 void __iomem *reg = bank->base;
124 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l;
127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
131 writel_relaxed(l, reg);
134 /* set data out value using mask register */
135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
138 void __iomem *reg = bank->base + bank->regs->dataout;
139 u32 gpio_bit = BIT(offset);
142 l = readl_relaxed(reg);
147 writel_relaxed(l, reg);
148 bank->context.dataout = l;
151 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
153 void __iomem *reg = bank->base + bank->regs->datain;
155 return (readl_relaxed(reg) & (BIT(offset))) != 0;
158 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
160 void __iomem *reg = bank->base + bank->regs->dataout;
162 return (readl_relaxed(reg) & (BIT(offset))) != 0;
165 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
167 int l = readl_relaxed(base + reg);
174 writel_relaxed(l, base + reg);
177 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
179 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
180 clk_enable(bank->dbck);
181 bank->dbck_enabled = true;
183 writel_relaxed(bank->dbck_enable_mask,
184 bank->base + bank->regs->debounce_en);
188 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
190 if (bank->dbck_enable_mask && bank->dbck_enabled) {
192 * Disable debounce before cutting it's clock. If debounce is
193 * enabled but the clock is not, GPIO module seems to be unable
194 * to detect events and generate interrupts at least on OMAP3.
196 writel_relaxed(0, bank->base + bank->regs->debounce_en);
198 clk_disable(bank->dbck);
199 bank->dbck_enabled = false;
204 * omap2_set_gpio_debounce - low level gpio debounce time
205 * @bank: the gpio bank we're acting upon
206 * @offset: the gpio number on this @bank
207 * @debounce: debounce time to use
209 * OMAP's debounce time is in 31us steps
210 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
211 * so we need to convert and round up to the closest unit.
213 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
219 bool enable = !!debounce;
221 if (!bank->dbck_flag)
225 debounce = DIV_ROUND_UP(debounce, 31) - 1;
226 debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
231 clk_enable(bank->dbck);
232 reg = bank->base + bank->regs->debounce;
233 writel_relaxed(debounce, reg);
235 reg = bank->base + bank->regs->debounce_en;
236 val = readl_relaxed(reg);
242 bank->dbck_enable_mask = val;
244 writel_relaxed(val, reg);
245 clk_disable(bank->dbck);
247 * Enable debounce clock per module.
248 * This call is mandatory because in omap_gpio_request() when
249 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
250 * runtime callbck fails to turn on dbck because dbck_enable_mask
251 * used within _gpio_dbck_enable() is still not initialized at
252 * that point. Therefore we have to enable dbck here.
254 omap_gpio_dbck_enable(bank);
255 if (bank->dbck_enable_mask) {
256 bank->context.debounce = debounce;
257 bank->context.debounce_en = val;
262 * omap_clear_gpio_debounce - clear debounce settings for a gpio
263 * @bank: the gpio bank we're acting upon
264 * @offset: the gpio number on this @bank
266 * If a gpio is using debounce, then clear the debounce enable bit and if
267 * this is the only gpio in this bank using debounce, then clear the debounce
268 * time too. The debounce clock will also be disabled when calling this function
269 * if this is the only gpio in the bank using debounce.
271 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
273 u32 gpio_bit = BIT(offset);
275 if (!bank->dbck_flag)
278 if (!(bank->dbck_enable_mask & gpio_bit))
281 bank->dbck_enable_mask &= ~gpio_bit;
282 bank->context.debounce_en &= ~gpio_bit;
283 writel_relaxed(bank->context.debounce_en,
284 bank->base + bank->regs->debounce_en);
286 if (!bank->dbck_enable_mask) {
287 bank->context.debounce = 0;
288 writel_relaxed(bank->context.debounce, bank->base +
289 bank->regs->debounce);
290 clk_disable(bank->dbck);
291 bank->dbck_enabled = false;
296 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
297 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
298 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
299 * are capable waking up the system from off mode.
301 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
303 u32 no_wake = bank->non_wakeup_gpios;
306 return !!(~no_wake & gpio_mask);
311 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
314 void __iomem *base = bank->base;
315 u32 gpio_bit = BIT(gpio);
317 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
318 trigger & IRQ_TYPE_LEVEL_LOW);
319 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
320 trigger & IRQ_TYPE_LEVEL_HIGH);
321 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
322 trigger & IRQ_TYPE_EDGE_RISING);
323 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
324 trigger & IRQ_TYPE_EDGE_FALLING);
326 bank->context.leveldetect0 =
327 readl_relaxed(bank->base + bank->regs->leveldetect0);
328 bank->context.leveldetect1 =
329 readl_relaxed(bank->base + bank->regs->leveldetect1);
330 bank->context.risingdetect =
331 readl_relaxed(bank->base + bank->regs->risingdetect);
332 bank->context.fallingdetect =
333 readl_relaxed(bank->base + bank->regs->fallingdetect);
335 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
336 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
337 bank->context.wake_en =
338 readl_relaxed(bank->base + bank->regs->wkup_en);
341 /* This part needs to be executed always for OMAP{34xx, 44xx} */
342 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
344 * Log the edge gpio and manually trigger the IRQ
345 * after resume if the input level changes
346 * to avoid irq lost during PER RET/OFF mode
347 * Applies for omap2 non-wakeup gpio and all omap3 gpios
349 if (trigger & IRQ_TYPE_EDGE_BOTH)
350 bank->enabled_non_wakeup_gpios |= gpio_bit;
352 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
356 readl_relaxed(bank->base + bank->regs->leveldetect0) |
357 readl_relaxed(bank->base + bank->regs->leveldetect1);
360 #ifdef CONFIG_ARCH_OMAP1
362 * This only applies to chips that can't do both rising and falling edge
363 * detection at once. For all other chips, this function is a noop.
365 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
367 void __iomem *reg = bank->base;
370 if (!bank->regs->irqctrl)
373 reg += bank->regs->irqctrl;
375 l = readl_relaxed(reg);
381 writel_relaxed(l, reg);
384 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
387 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
390 void __iomem *reg = bank->base;
391 void __iomem *base = bank->base;
394 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
395 omap_set_gpio_trigger(bank, gpio, trigger);
396 } else if (bank->regs->irqctrl) {
397 reg += bank->regs->irqctrl;
399 l = readl_relaxed(reg);
400 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
401 bank->toggle_mask |= BIT(gpio);
402 if (trigger & IRQ_TYPE_EDGE_RISING)
404 else if (trigger & IRQ_TYPE_EDGE_FALLING)
409 writel_relaxed(l, reg);
410 } else if (bank->regs->edgectrl1) {
412 reg += bank->regs->edgectrl2;
414 reg += bank->regs->edgectrl1;
417 l = readl_relaxed(reg);
418 l &= ~(3 << (gpio << 1));
419 if (trigger & IRQ_TYPE_EDGE_RISING)
420 l |= 2 << (gpio << 1);
421 if (trigger & IRQ_TYPE_EDGE_FALLING)
424 /* Enable wake-up during idle for dynamic tick */
425 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
426 bank->context.wake_en =
427 readl_relaxed(bank->base + bank->regs->wkup_en);
428 writel_relaxed(l, reg);
433 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
435 if (bank->regs->pinctrl) {
436 void __iomem *reg = bank->base + bank->regs->pinctrl;
438 /* Claim the pin for MPU */
439 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
442 if (bank->regs->ctrl && !BANK_USED(bank)) {
443 void __iomem *reg = bank->base + bank->regs->ctrl;
446 ctrl = readl_relaxed(reg);
447 /* Module is enabled, clocks are not gated */
448 ctrl &= ~GPIO_MOD_CTRL_BIT;
449 writel_relaxed(ctrl, reg);
450 bank->context.ctrl = ctrl;
454 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
456 void __iomem *base = bank->base;
458 if (bank->regs->wkup_en &&
459 !LINE_USED(bank->mod_usage, offset) &&
460 !LINE_USED(bank->irq_usage, offset)) {
461 /* Disable wake-up during idle for dynamic tick */
462 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
463 bank->context.wake_en =
464 readl_relaxed(bank->base + bank->regs->wkup_en);
467 if (bank->regs->ctrl && !BANK_USED(bank)) {
468 void __iomem *reg = bank->base + bank->regs->ctrl;
471 ctrl = readl_relaxed(reg);
472 /* Module is disabled, clocks are gated */
473 ctrl |= GPIO_MOD_CTRL_BIT;
474 writel_relaxed(ctrl, reg);
475 bank->context.ctrl = ctrl;
479 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
481 void __iomem *reg = bank->base + bank->regs->direction;
483 return readl_relaxed(reg) & BIT(offset);
486 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
488 if (!LINE_USED(bank->mod_usage, offset)) {
489 omap_enable_gpio_module(bank, offset);
490 omap_set_gpio_direction(bank, offset, 1);
492 bank->irq_usage |= BIT(offset);
495 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
497 struct gpio_bank *bank = omap_irq_data_get_bank(d);
500 unsigned offset = d->hwirq;
502 if (type & ~IRQ_TYPE_SENSE_MASK)
505 if (!bank->regs->leveldetect0 &&
506 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
509 raw_spin_lock_irqsave(&bank->lock, flags);
510 retval = omap_set_gpio_triggering(bank, offset, type);
512 raw_spin_unlock_irqrestore(&bank->lock, flags);
515 omap_gpio_init_irq(bank, offset);
516 if (!omap_gpio_is_input(bank, offset)) {
517 raw_spin_unlock_irqrestore(&bank->lock, flags);
521 raw_spin_unlock_irqrestore(&bank->lock, flags);
523 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
524 irq_set_handler_locked(d, handle_level_irq);
525 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
526 irq_set_handler_locked(d, handle_edge_irq);
534 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
536 void __iomem *reg = bank->base;
538 reg += bank->regs->irqstatus;
539 writel_relaxed(gpio_mask, reg);
541 /* Workaround for clearing DSP GPIO interrupts to allow retention */
542 if (bank->regs->irqstatus2) {
543 reg = bank->base + bank->regs->irqstatus2;
544 writel_relaxed(gpio_mask, reg);
547 /* Flush posted write for the irq status to avoid spurious interrupts */
551 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
554 omap_clear_gpio_irqbank(bank, BIT(offset));
557 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
559 void __iomem *reg = bank->base;
561 u32 mask = (BIT(bank->width)) - 1;
563 reg += bank->regs->irqenable;
564 l = readl_relaxed(reg);
565 if (bank->regs->irqenable_inv)
571 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
573 void __iomem *reg = bank->base;
576 if (bank->regs->set_irqenable) {
577 reg += bank->regs->set_irqenable;
579 bank->context.irqenable1 |= gpio_mask;
581 reg += bank->regs->irqenable;
582 l = readl_relaxed(reg);
583 if (bank->regs->irqenable_inv)
587 bank->context.irqenable1 = l;
590 writel_relaxed(l, reg);
593 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
595 void __iomem *reg = bank->base;
598 if (bank->regs->clr_irqenable) {
599 reg += bank->regs->clr_irqenable;
601 bank->context.irqenable1 &= ~gpio_mask;
603 reg += bank->regs->irqenable;
604 l = readl_relaxed(reg);
605 if (bank->regs->irqenable_inv)
609 bank->context.irqenable1 = l;
612 writel_relaxed(l, reg);
615 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
616 unsigned offset, int enable)
619 omap_enable_gpio_irqbank(bank, BIT(offset));
621 omap_disable_gpio_irqbank(bank, BIT(offset));
625 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
626 * 1510 does not seem to have a wake-up register. If JTAG is connected
627 * to the target, system will wake up always on GPIO events. While
628 * system is running all registered GPIO interrupts need to have wake-up
629 * enabled. When system is suspended, only selected GPIO interrupts need
630 * to have wake-up enabled.
632 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
635 u32 gpio_bit = BIT(offset);
638 if (bank->non_wakeup_gpios & gpio_bit) {
640 "Unable to modify wakeup on non-wakeup GPIO%d\n",
645 raw_spin_lock_irqsave(&bank->lock, flags);
647 bank->context.wake_en |= gpio_bit;
649 bank->context.wake_en &= ~gpio_bit;
651 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
652 raw_spin_unlock_irqrestore(&bank->lock, flags);
657 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
658 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
660 struct gpio_bank *bank = omap_irq_data_get_bank(d);
661 unsigned offset = d->hwirq;
664 ret = omap_set_gpio_wakeup(bank, offset, enable);
666 ret = irq_set_irq_wake(bank->irq, enable);
671 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
673 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
677 * If this is the first gpio_request for the bank,
678 * enable the bank module.
680 if (!BANK_USED(bank))
681 pm_runtime_get_sync(bank->dev);
683 raw_spin_lock_irqsave(&bank->lock, flags);
684 omap_enable_gpio_module(bank, offset);
685 bank->mod_usage |= BIT(offset);
686 raw_spin_unlock_irqrestore(&bank->lock, flags);
691 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
693 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
696 raw_spin_lock_irqsave(&bank->lock, flags);
697 bank->mod_usage &= ~(BIT(offset));
698 if (!LINE_USED(bank->irq_usage, offset)) {
699 omap_set_gpio_direction(bank, offset, 1);
700 omap_clear_gpio_debounce(bank, offset);
702 omap_disable_gpio_module(bank, offset);
703 raw_spin_unlock_irqrestore(&bank->lock, flags);
706 * If this is the last gpio to be freed in the bank,
707 * disable the bank module.
709 if (!BANK_USED(bank))
710 pm_runtime_put(bank->dev);
714 * We need to unmask the GPIO bank interrupt as soon as possible to
715 * avoid missing GPIO interrupts for other lines in the bank.
716 * Then we need to mask-read-clear-unmask the triggered GPIO lines
717 * in the bank to avoid missing nested interrupts for a GPIO line.
718 * If we wait to unmask individual GPIO lines in the bank after the
719 * line's interrupt handler has been run, we may miss some nested
722 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
724 void __iomem *isr_reg = NULL;
727 struct gpio_bank *bank = gpiobank;
728 unsigned long wa_lock_flags;
729 unsigned long lock_flags;
731 isr_reg = bank->base + bank->regs->irqstatus;
732 if (WARN_ON(!isr_reg))
735 pm_runtime_get_sync(bank->dev);
738 u32 isr_saved, level_mask = 0;
741 raw_spin_lock_irqsave(&bank->lock, lock_flags);
743 enabled = omap_get_gpio_irqbank_mask(bank);
744 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
746 if (bank->level_mask)
747 level_mask = bank->level_mask & enabled;
749 /* clear edge sensitive interrupts before handler(s) are
750 called so that we don't miss any interrupt occurred while
752 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
753 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
754 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
756 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
765 raw_spin_lock_irqsave(&bank->lock, lock_flags);
767 * Some chips can't respond to both rising and falling
768 * at the same time. If this irq was requested with
769 * both flags, we need to flip the ICR data for the IRQ
770 * to respond to the IRQ for the opposite direction.
771 * This will be indicated in the bank toggle_mask.
773 if (bank->toggle_mask & (BIT(bit)))
774 omap_toggle_gpio_edge_triggering(bank, bit);
776 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
778 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
780 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
783 raw_spin_unlock_irqrestore(&bank->wa_lock,
788 pm_runtime_put(bank->dev);
792 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
794 struct gpio_bank *bank = omap_irq_data_get_bank(d);
796 unsigned offset = d->hwirq;
798 raw_spin_lock_irqsave(&bank->lock, flags);
800 if (!LINE_USED(bank->mod_usage, offset))
801 omap_set_gpio_direction(bank, offset, 1);
802 else if (!omap_gpio_is_input(bank, offset))
804 omap_enable_gpio_module(bank, offset);
805 bank->irq_usage |= BIT(offset);
807 raw_spin_unlock_irqrestore(&bank->lock, flags);
808 omap_gpio_unmask_irq(d);
812 raw_spin_unlock_irqrestore(&bank->lock, flags);
816 static void omap_gpio_irq_shutdown(struct irq_data *d)
818 struct gpio_bank *bank = omap_irq_data_get_bank(d);
820 unsigned offset = d->hwirq;
822 raw_spin_lock_irqsave(&bank->lock, flags);
823 bank->irq_usage &= ~(BIT(offset));
824 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
825 omap_clear_gpio_irqstatus(bank, offset);
826 omap_set_gpio_irqenable(bank, offset, 0);
827 if (!LINE_USED(bank->mod_usage, offset))
828 omap_clear_gpio_debounce(bank, offset);
829 omap_disable_gpio_module(bank, offset);
830 raw_spin_unlock_irqrestore(&bank->lock, flags);
833 static void omap_gpio_irq_bus_lock(struct irq_data *data)
835 struct gpio_bank *bank = omap_irq_data_get_bank(data);
837 if (!BANK_USED(bank))
838 pm_runtime_get_sync(bank->dev);
841 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
843 struct gpio_bank *bank = omap_irq_data_get_bank(data);
846 * If this is the last IRQ to be freed in the bank,
847 * disable the bank module.
849 if (!BANK_USED(bank))
850 pm_runtime_put(bank->dev);
853 static void omap_gpio_ack_irq(struct irq_data *d)
855 struct gpio_bank *bank = omap_irq_data_get_bank(d);
856 unsigned offset = d->hwirq;
858 omap_clear_gpio_irqstatus(bank, offset);
861 static void omap_gpio_mask_irq(struct irq_data *d)
863 struct gpio_bank *bank = omap_irq_data_get_bank(d);
864 unsigned offset = d->hwirq;
867 raw_spin_lock_irqsave(&bank->lock, flags);
868 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
869 omap_set_gpio_irqenable(bank, offset, 0);
870 raw_spin_unlock_irqrestore(&bank->lock, flags);
873 static void omap_gpio_unmask_irq(struct irq_data *d)
875 struct gpio_bank *bank = omap_irq_data_get_bank(d);
876 unsigned offset = d->hwirq;
877 u32 trigger = irqd_get_trigger_type(d);
880 raw_spin_lock_irqsave(&bank->lock, flags);
881 omap_set_gpio_irqenable(bank, offset, 1);
884 * For level-triggered GPIOs, clearing must be done after the source
885 * is cleared, thus after the handler has run. OMAP4 needs this done
886 * after enabing the interrupt to clear the wakeup status.
888 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
889 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
890 omap_clear_gpio_irqstatus(bank, offset);
893 omap_set_gpio_triggering(bank, offset, trigger);
895 raw_spin_unlock_irqrestore(&bank->lock, flags);
898 /*---------------------------------------------------------------------*/
900 static int omap_mpuio_suspend_noirq(struct device *dev)
902 struct platform_device *pdev = to_platform_device(dev);
903 struct gpio_bank *bank = platform_get_drvdata(pdev);
904 void __iomem *mask_reg = bank->base +
905 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
908 raw_spin_lock_irqsave(&bank->lock, flags);
909 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
910 raw_spin_unlock_irqrestore(&bank->lock, flags);
915 static int omap_mpuio_resume_noirq(struct device *dev)
917 struct platform_device *pdev = to_platform_device(dev);
918 struct gpio_bank *bank = platform_get_drvdata(pdev);
919 void __iomem *mask_reg = bank->base +
920 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
923 raw_spin_lock_irqsave(&bank->lock, flags);
924 writel_relaxed(bank->context.wake_en, mask_reg);
925 raw_spin_unlock_irqrestore(&bank->lock, flags);
930 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
931 .suspend_noirq = omap_mpuio_suspend_noirq,
932 .resume_noirq = omap_mpuio_resume_noirq,
935 /* use platform_driver for this. */
936 static struct platform_driver omap_mpuio_driver = {
939 .pm = &omap_mpuio_dev_pm_ops,
943 static struct platform_device omap_mpuio_device = {
947 .driver = &omap_mpuio_driver.driver,
949 /* could list the /proc/iomem resources */
952 static inline void omap_mpuio_init(struct gpio_bank *bank)
954 platform_set_drvdata(&omap_mpuio_device, bank);
956 if (platform_driver_register(&omap_mpuio_driver) == 0)
957 (void) platform_device_register(&omap_mpuio_device);
960 /*---------------------------------------------------------------------*/
962 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
964 struct gpio_bank *bank;
969 bank = container_of(chip, struct gpio_bank, chip);
970 reg = bank->base + bank->regs->direction;
971 raw_spin_lock_irqsave(&bank->lock, flags);
972 dir = !!(readl_relaxed(reg) & BIT(offset));
973 raw_spin_unlock_irqrestore(&bank->lock, flags);
977 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
979 struct gpio_bank *bank;
982 bank = container_of(chip, struct gpio_bank, chip);
983 raw_spin_lock_irqsave(&bank->lock, flags);
984 omap_set_gpio_direction(bank, offset, 1);
985 raw_spin_unlock_irqrestore(&bank->lock, flags);
989 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
991 struct gpio_bank *bank;
993 bank = container_of(chip, struct gpio_bank, chip);
995 if (omap_gpio_is_input(bank, offset))
996 return omap_get_gpio_datain(bank, offset);
998 return omap_get_gpio_dataout(bank, offset);
1001 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1003 struct gpio_bank *bank;
1004 unsigned long flags;
1006 bank = container_of(chip, struct gpio_bank, chip);
1007 raw_spin_lock_irqsave(&bank->lock, flags);
1008 bank->set_dataout(bank, offset, value);
1009 omap_set_gpio_direction(bank, offset, 0);
1010 raw_spin_unlock_irqrestore(&bank->lock, flags);
1014 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1017 struct gpio_bank *bank;
1018 unsigned long flags;
1020 bank = container_of(chip, struct gpio_bank, chip);
1022 raw_spin_lock_irqsave(&bank->lock, flags);
1023 omap2_set_gpio_debounce(bank, offset, debounce);
1024 raw_spin_unlock_irqrestore(&bank->lock, flags);
1029 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1031 struct gpio_bank *bank;
1032 unsigned long flags;
1034 bank = container_of(chip, struct gpio_bank, chip);
1035 raw_spin_lock_irqsave(&bank->lock, flags);
1036 bank->set_dataout(bank, offset, value);
1037 raw_spin_unlock_irqrestore(&bank->lock, flags);
1040 /*---------------------------------------------------------------------*/
1042 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1047 if (called || bank->regs->revision == USHRT_MAX)
1050 rev = readw_relaxed(bank->base + bank->regs->revision);
1051 pr_info("OMAP GPIO hardware version %d.%d\n",
1052 (rev >> 4) & 0x0f, rev & 0x0f);
1057 static void omap_gpio_mod_init(struct gpio_bank *bank)
1059 void __iomem *base = bank->base;
1062 if (bank->width == 16)
1065 if (bank->is_mpuio) {
1066 writel_relaxed(l, bank->base + bank->regs->irqenable);
1070 omap_gpio_rmw(base, bank->regs->irqenable, l,
1071 bank->regs->irqenable_inv);
1072 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1073 !bank->regs->irqenable_inv);
1074 if (bank->regs->debounce_en)
1075 writel_relaxed(0, base + bank->regs->debounce_en);
1077 /* Save OE default value (0xffffffff) in the context */
1078 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1079 /* Initialize interface clk ungated, module enabled */
1080 if (bank->regs->ctrl)
1081 writel_relaxed(0, base + bank->regs->ctrl);
1084 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1091 * REVISIT eventually switch from OMAP-specific gpio structs
1092 * over to the generic ones
1094 bank->chip.request = omap_gpio_request;
1095 bank->chip.free = omap_gpio_free;
1096 bank->chip.get_direction = omap_gpio_get_direction;
1097 bank->chip.direction_input = omap_gpio_input;
1098 bank->chip.get = omap_gpio_get;
1099 bank->chip.direction_output = omap_gpio_output;
1100 bank->chip.set_debounce = omap_gpio_debounce;
1101 bank->chip.set = omap_gpio_set;
1102 if (bank->is_mpuio) {
1103 bank->chip.label = "mpuio";
1104 if (bank->regs->wkup_en)
1105 bank->chip.dev = &omap_mpuio_device.dev;
1106 bank->chip.base = OMAP_MPUIO(0);
1108 bank->chip.label = "gpio";
1109 bank->chip.base = gpio;
1111 bank->chip.ngpio = bank->width;
1113 ret = gpiochip_add(&bank->chip);
1115 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1119 if (!bank->is_mpuio)
1120 gpio += bank->width;
1122 #ifdef CONFIG_ARCH_OMAP1
1124 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1125 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1127 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1129 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1134 /* MPUIO is a bit different, reading IRQ status clears it */
1135 if (bank->is_mpuio) {
1136 irqc->irq_ack = dummy_irq_chip.irq_ack;
1137 if (!bank->regs->wkup_en)
1138 irqc->irq_set_wake = NULL;
1141 ret = gpiochip_irqchip_add(&bank->chip, irqc,
1142 irq_base, handle_bad_irq,
1146 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1147 gpiochip_remove(&bank->chip);
1151 gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL);
1153 ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler,
1154 0, dev_name(bank->dev), bank);
1156 gpiochip_remove(&bank->chip);
1161 static const struct of_device_id omap_gpio_match[];
1163 static int omap_gpio_probe(struct platform_device *pdev)
1165 struct device *dev = &pdev->dev;
1166 struct device_node *node = dev->of_node;
1167 const struct of_device_id *match;
1168 const struct omap_gpio_platform_data *pdata;
1169 struct resource *res;
1170 struct gpio_bank *bank;
1171 struct irq_chip *irqc;
1174 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1176 pdata = match ? match->data : dev_get_platdata(dev);
1180 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1182 dev_err(dev, "Memory alloc failed\n");
1186 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1190 irqc->irq_startup = omap_gpio_irq_startup,
1191 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1192 irqc->irq_ack = omap_gpio_ack_irq,
1193 irqc->irq_mask = omap_gpio_mask_irq,
1194 irqc->irq_unmask = omap_gpio_unmask_irq,
1195 irqc->irq_set_type = omap_gpio_irq_type,
1196 irqc->irq_set_wake = omap_gpio_wake_enable,
1197 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1198 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1199 irqc->name = dev_name(&pdev->dev);
1201 bank->irq = platform_get_irq(pdev, 0);
1202 if (bank->irq <= 0) {
1205 if (bank->irq != -EPROBE_DEFER)
1207 "can't get irq resource ret=%d\n", bank->irq);
1212 bank->chip.dev = dev;
1213 bank->chip.owner = THIS_MODULE;
1214 bank->dbck_flag = pdata->dbck_flag;
1215 bank->stride = pdata->bank_stride;
1216 bank->width = pdata->bank_width;
1217 bank->is_mpuio = pdata->is_mpuio;
1218 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1219 bank->regs = pdata->regs;
1220 #ifdef CONFIG_OF_GPIO
1221 bank->chip.of_node = of_node_get(node);
1224 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1225 bank->loses_context = true;
1227 bank->loses_context = pdata->loses_context;
1229 if (bank->loses_context)
1230 bank->get_context_loss_count =
1231 pdata->get_context_loss_count;
1234 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1235 bank->set_dataout = omap_set_gpio_dataout_reg;
1237 bank->set_dataout = omap_set_gpio_dataout_mask;
1239 raw_spin_lock_init(&bank->lock);
1240 raw_spin_lock_init(&bank->wa_lock);
1242 /* Static mapping, never released */
1243 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244 bank->base = devm_ioremap_resource(dev, res);
1245 if (IS_ERR(bank->base)) {
1246 return PTR_ERR(bank->base);
1249 if (bank->dbck_flag) {
1250 bank->dbck = devm_clk_get(bank->dev, "dbclk");
1251 if (IS_ERR(bank->dbck)) {
1253 "Could not get gpio dbck. Disable debounce\n");
1254 bank->dbck_flag = false;
1256 clk_prepare(bank->dbck);
1260 platform_set_drvdata(pdev, bank);
1262 pm_runtime_enable(bank->dev);
1263 pm_runtime_irq_safe(bank->dev);
1264 pm_runtime_get_sync(bank->dev);
1267 omap_mpuio_init(bank);
1269 omap_gpio_mod_init(bank);
1271 ret = omap_gpio_chip_init(bank, irqc);
1273 pm_runtime_put_sync(bank->dev);
1274 pm_runtime_disable(bank->dev);
1278 omap_gpio_show_rev(bank);
1280 pm_runtime_put(bank->dev);
1282 list_add_tail(&bank->node, &omap_gpio_list);
1287 static int omap_gpio_remove(struct platform_device *pdev)
1289 struct gpio_bank *bank = platform_get_drvdata(pdev);
1291 list_del(&bank->node);
1292 gpiochip_remove(&bank->chip);
1293 pm_runtime_disable(bank->dev);
1294 if (bank->dbck_flag)
1295 clk_unprepare(bank->dbck);
1300 #ifdef CONFIG_ARCH_OMAP2PLUS
1302 #if defined(CONFIG_PM)
1303 static void omap_gpio_restore_context(struct gpio_bank *bank);
1305 static int omap_gpio_runtime_suspend(struct device *dev)
1307 struct platform_device *pdev = to_platform_device(dev);
1308 struct gpio_bank *bank = platform_get_drvdata(pdev);
1310 unsigned long flags;
1311 u32 wake_low, wake_hi;
1313 raw_spin_lock_irqsave(&bank->lock, flags);
1316 * Only edges can generate a wakeup event to the PRCM.
1318 * Therefore, ensure any wake-up capable GPIOs have
1319 * edge-detection enabled before going idle to ensure a wakeup
1320 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1323 * The normal values will be restored upon ->runtime_resume()
1324 * by writing back the values saved in bank->context.
1326 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1328 writel_relaxed(wake_low | bank->context.fallingdetect,
1329 bank->base + bank->regs->fallingdetect);
1330 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1332 writel_relaxed(wake_hi | bank->context.risingdetect,
1333 bank->base + bank->regs->risingdetect);
1335 if (!bank->enabled_non_wakeup_gpios)
1336 goto update_gpio_context_count;
1338 if (bank->power_mode != OFF_MODE) {
1339 bank->power_mode = 0;
1340 goto update_gpio_context_count;
1343 * If going to OFF, remove triggering for all
1344 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1345 * generated. See OMAP2420 Errata item 1.101.
1347 bank->saved_datain = readl_relaxed(bank->base +
1348 bank->regs->datain);
1349 l1 = bank->context.fallingdetect;
1350 l2 = bank->context.risingdetect;
1352 l1 &= ~bank->enabled_non_wakeup_gpios;
1353 l2 &= ~bank->enabled_non_wakeup_gpios;
1355 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1356 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1358 bank->workaround_enabled = true;
1360 update_gpio_context_count:
1361 if (bank->get_context_loss_count)
1362 bank->context_loss_count =
1363 bank->get_context_loss_count(bank->dev);
1365 omap_gpio_dbck_disable(bank);
1366 raw_spin_unlock_irqrestore(&bank->lock, flags);
1371 static void omap_gpio_init_context(struct gpio_bank *p);
1373 static int omap_gpio_runtime_resume(struct device *dev)
1375 struct platform_device *pdev = to_platform_device(dev);
1376 struct gpio_bank *bank = platform_get_drvdata(pdev);
1377 u32 l = 0, gen, gen0, gen1;
1378 unsigned long flags;
1381 raw_spin_lock_irqsave(&bank->lock, flags);
1384 * On the first resume during the probe, the context has not
1385 * been initialised and so initialise it now. Also initialise
1386 * the context loss count.
1388 if (bank->loses_context && !bank->context_valid) {
1389 omap_gpio_init_context(bank);
1391 if (bank->get_context_loss_count)
1392 bank->context_loss_count =
1393 bank->get_context_loss_count(bank->dev);
1396 omap_gpio_dbck_enable(bank);
1399 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1400 * GPIOs were set to edge trigger also in order to be able to
1401 * generate a PRCM wakeup. Here we restore the
1402 * pre-runtime_suspend() values for edge triggering.
1404 writel_relaxed(bank->context.fallingdetect,
1405 bank->base + bank->regs->fallingdetect);
1406 writel_relaxed(bank->context.risingdetect,
1407 bank->base + bank->regs->risingdetect);
1409 if (bank->loses_context) {
1410 if (!bank->get_context_loss_count) {
1411 omap_gpio_restore_context(bank);
1413 c = bank->get_context_loss_count(bank->dev);
1414 if (c != bank->context_loss_count) {
1415 omap_gpio_restore_context(bank);
1417 raw_spin_unlock_irqrestore(&bank->lock, flags);
1423 if (!bank->workaround_enabled) {
1424 raw_spin_unlock_irqrestore(&bank->lock, flags);
1428 l = readl_relaxed(bank->base + bank->regs->datain);
1431 * Check if any of the non-wakeup interrupt GPIOs have changed
1432 * state. If so, generate an IRQ by software. This is
1433 * horribly racy, but it's the best we can do to work around
1436 l ^= bank->saved_datain;
1437 l &= bank->enabled_non_wakeup_gpios;
1440 * No need to generate IRQs for the rising edge for gpio IRQs
1441 * configured with falling edge only; and vice versa.
1443 gen0 = l & bank->context.fallingdetect;
1444 gen0 &= bank->saved_datain;
1446 gen1 = l & bank->context.risingdetect;
1447 gen1 &= ~(bank->saved_datain);
1449 /* FIXME: Consider GPIO IRQs with level detections properly! */
1450 gen = l & (~(bank->context.fallingdetect) &
1451 ~(bank->context.risingdetect));
1452 /* Consider all GPIO IRQs needed to be updated */
1458 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1459 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1461 if (!bank->regs->irqstatus_raw0) {
1462 writel_relaxed(old0 | gen, bank->base +
1463 bank->regs->leveldetect0);
1464 writel_relaxed(old1 | gen, bank->base +
1465 bank->regs->leveldetect1);
1468 if (bank->regs->irqstatus_raw0) {
1469 writel_relaxed(old0 | l, bank->base +
1470 bank->regs->leveldetect0);
1471 writel_relaxed(old1 | l, bank->base +
1472 bank->regs->leveldetect1);
1474 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1475 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1478 bank->workaround_enabled = false;
1479 raw_spin_unlock_irqrestore(&bank->lock, flags);
1483 #endif /* CONFIG_PM */
1485 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1486 void omap2_gpio_prepare_for_idle(int pwr_mode)
1488 struct gpio_bank *bank;
1490 list_for_each_entry(bank, &omap_gpio_list, node) {
1491 if (!BANK_USED(bank) || !bank->loses_context)
1494 bank->power_mode = pwr_mode;
1496 pm_runtime_put_sync_suspend(bank->dev);
1500 void omap2_gpio_resume_after_idle(void)
1502 struct gpio_bank *bank;
1504 list_for_each_entry(bank, &omap_gpio_list, node) {
1505 if (!BANK_USED(bank) || !bank->loses_context)
1508 pm_runtime_get_sync(bank->dev);
1513 #if defined(CONFIG_PM)
1514 static void omap_gpio_init_context(struct gpio_bank *p)
1516 struct omap_gpio_reg_offs *regs = p->regs;
1517 void __iomem *base = p->base;
1519 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1520 p->context.oe = readl_relaxed(base + regs->direction);
1521 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1522 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1523 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1524 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1525 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1526 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1527 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1529 if (regs->set_dataout && p->regs->clr_dataout)
1530 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1532 p->context.dataout = readl_relaxed(base + regs->dataout);
1534 p->context_valid = true;
1537 static void omap_gpio_restore_context(struct gpio_bank *bank)
1539 writel_relaxed(bank->context.wake_en,
1540 bank->base + bank->regs->wkup_en);
1541 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1542 writel_relaxed(bank->context.leveldetect0,
1543 bank->base + bank->regs->leveldetect0);
1544 writel_relaxed(bank->context.leveldetect1,
1545 bank->base + bank->regs->leveldetect1);
1546 writel_relaxed(bank->context.risingdetect,
1547 bank->base + bank->regs->risingdetect);
1548 writel_relaxed(bank->context.fallingdetect,
1549 bank->base + bank->regs->fallingdetect);
1550 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1551 writel_relaxed(bank->context.dataout,
1552 bank->base + bank->regs->set_dataout);
1554 writel_relaxed(bank->context.dataout,
1555 bank->base + bank->regs->dataout);
1556 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1558 if (bank->dbck_enable_mask) {
1559 writel_relaxed(bank->context.debounce, bank->base +
1560 bank->regs->debounce);
1561 writel_relaxed(bank->context.debounce_en,
1562 bank->base + bank->regs->debounce_en);
1565 writel_relaxed(bank->context.irqenable1,
1566 bank->base + bank->regs->irqenable);
1567 writel_relaxed(bank->context.irqenable2,
1568 bank->base + bank->regs->irqenable2);
1570 #endif /* CONFIG_PM */
1572 #define omap_gpio_runtime_suspend NULL
1573 #define omap_gpio_runtime_resume NULL
1574 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1577 static const struct dev_pm_ops gpio_pm_ops = {
1578 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1582 #if defined(CONFIG_OF)
1583 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1584 .revision = OMAP24XX_GPIO_REVISION,
1585 .direction = OMAP24XX_GPIO_OE,
1586 .datain = OMAP24XX_GPIO_DATAIN,
1587 .dataout = OMAP24XX_GPIO_DATAOUT,
1588 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1589 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1590 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1591 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1592 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1593 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1594 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1595 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1596 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1597 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1598 .ctrl = OMAP24XX_GPIO_CTRL,
1599 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1600 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1601 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1602 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1603 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1606 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1607 .revision = OMAP4_GPIO_REVISION,
1608 .direction = OMAP4_GPIO_OE,
1609 .datain = OMAP4_GPIO_DATAIN,
1610 .dataout = OMAP4_GPIO_DATAOUT,
1611 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1612 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1613 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1614 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1615 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1616 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1617 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1618 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1619 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1620 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1621 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1622 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1623 .ctrl = OMAP4_GPIO_CTRL,
1624 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1625 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1626 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1627 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1628 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1631 static const struct omap_gpio_platform_data omap2_pdata = {
1632 .regs = &omap2_gpio_regs,
1637 static const struct omap_gpio_platform_data omap3_pdata = {
1638 .regs = &omap2_gpio_regs,
1643 static const struct omap_gpio_platform_data omap4_pdata = {
1644 .regs = &omap4_gpio_regs,
1649 static const struct of_device_id omap_gpio_match[] = {
1651 .compatible = "ti,omap4-gpio",
1652 .data = &omap4_pdata,
1655 .compatible = "ti,omap3-gpio",
1656 .data = &omap3_pdata,
1659 .compatible = "ti,omap2-gpio",
1660 .data = &omap2_pdata,
1664 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1667 static struct platform_driver omap_gpio_driver = {
1668 .probe = omap_gpio_probe,
1669 .remove = omap_gpio_remove,
1671 .name = "omap_gpio",
1673 .of_match_table = of_match_ptr(omap_gpio_match),
1678 * gpio driver register needs to be done before
1679 * machine_init functions access gpio APIs.
1680 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1682 static int __init omap_gpio_drv_reg(void)
1684 return platform_driver_register(&omap_gpio_driver);
1686 postcore_initcall(omap_gpio_drv_reg);
1688 static void __exit omap_gpio_exit(void)
1690 platform_driver_unregister(&omap_gpio_driver);
1692 module_exit(omap_gpio_exit);
1694 MODULE_DESCRIPTION("omap gpio driver");
1695 MODULE_ALIAS("platform:gpio-omap");
1696 MODULE_LICENSE("GPL v2");