2 * Copyright (C) 2011-2012 Avionic Design GmbH
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/gpio/driver.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_irq.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
24 struct i2c_client *client;
25 struct gpio_chip gpio;
26 unsigned int reg_shift;
28 struct mutex i2c_lock;
29 struct mutex irq_lock;
39 static inline struct adnp *to_adnp(struct gpio_chip *chip)
41 return container_of(chip, struct adnp, gpio);
44 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
48 err = i2c_smbus_read_byte_data(adnp->client, offset);
50 dev_err(adnp->gpio.dev, "%s failed: %d\n",
51 "i2c_smbus_read_byte_data()", err);
59 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
63 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
65 dev_err(adnp->gpio.dev, "%s failed: %d\n",
66 "i2c_smbus_write_byte_data()", err);
73 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
75 struct adnp *adnp = to_adnp(chip);
76 unsigned int reg = offset >> adnp->reg_shift;
77 unsigned int pos = offset & 7;
81 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
85 return (value & BIT(pos)) ? 1 : 0;
88 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
90 unsigned int reg = offset >> adnp->reg_shift;
91 unsigned int pos = offset & 7;
95 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
104 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
107 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
109 struct adnp *adnp = to_adnp(chip);
111 mutex_lock(&adnp->i2c_lock);
112 __adnp_gpio_set(adnp, offset, value);
113 mutex_unlock(&adnp->i2c_lock);
116 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
118 struct adnp *adnp = to_adnp(chip);
119 unsigned int reg = offset >> adnp->reg_shift;
120 unsigned int pos = offset & 7;
124 mutex_lock(&adnp->i2c_lock);
126 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
132 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
136 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
140 if (value & BIT(pos)) {
148 mutex_unlock(&adnp->i2c_lock);
152 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
155 struct adnp *adnp = to_adnp(chip);
156 unsigned int reg = offset >> adnp->reg_shift;
157 unsigned int pos = offset & 7;
161 mutex_lock(&adnp->i2c_lock);
163 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
169 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
173 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
177 if (!(val & BIT(pos))) {
182 __adnp_gpio_set(adnp, offset, value);
186 mutex_unlock(&adnp->i2c_lock);
190 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
192 struct adnp *adnp = to_adnp(chip);
193 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
196 for (i = 0; i < num_regs; i++) {
197 u8 ddr, plr, ier, isr;
199 mutex_lock(&adnp->i2c_lock);
201 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
203 mutex_unlock(&adnp->i2c_lock);
207 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
209 mutex_unlock(&adnp->i2c_lock);
213 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
215 mutex_unlock(&adnp->i2c_lock);
219 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
221 mutex_unlock(&adnp->i2c_lock);
225 mutex_unlock(&adnp->i2c_lock);
227 for (j = 0; j < 8; j++) {
228 unsigned int bit = (i << adnp->reg_shift) + j;
229 const char *direction = "input ";
230 const char *level = "low ";
231 const char *interrupt = "disabled";
232 const char *pending = "";
235 direction = "output";
241 interrupt = "enabled ";
246 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
247 direction, level, interrupt, pending);
252 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
254 struct gpio_chip *chip = &adnp->gpio;
257 adnp->reg_shift = get_count_order(num_gpios) - 3;
259 chip->direction_input = adnp_gpio_direction_input;
260 chip->direction_output = adnp_gpio_direction_output;
261 chip->get = adnp_gpio_get;
262 chip->set = adnp_gpio_set;
263 chip->can_sleep = true;
265 if (IS_ENABLED(CONFIG_DEBUG_FS))
266 chip->dbg_show = adnp_gpio_dbg_show;
269 chip->ngpio = num_gpios;
270 chip->label = adnp->client->name;
271 chip->dev = &adnp->client->dev;
272 chip->of_node = chip->dev->of_node;
273 chip->owner = THIS_MODULE;
275 err = gpiochip_add(chip);
282 static irqreturn_t adnp_irq(int irq, void *data)
284 struct adnp *adnp = data;
285 unsigned int num_regs, i;
287 num_regs = 1 << adnp->reg_shift;
289 for (i = 0; i < num_regs; i++) {
290 unsigned int base = i << adnp->reg_shift, bit;
291 u8 changed, level, isr, ier;
292 unsigned long pending;
295 mutex_lock(&adnp->i2c_lock);
297 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
299 mutex_unlock(&adnp->i2c_lock);
303 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
305 mutex_unlock(&adnp->i2c_lock);
309 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
311 mutex_unlock(&adnp->i2c_lock);
315 mutex_unlock(&adnp->i2c_lock);
317 /* determine pins that changed levels */
318 changed = level ^ adnp->irq_level[i];
320 /* compute edge-triggered interrupts */
321 pending = changed & ((adnp->irq_fall[i] & ~level) |
322 (adnp->irq_rise[i] & level));
324 /* add in level-triggered interrupts */
325 pending |= (adnp->irq_high[i] & level) |
326 (adnp->irq_low[i] & ~level);
328 /* mask out non-pending and disabled interrupts */
329 pending &= isr & ier;
331 for_each_set_bit(bit, &pending, 8) {
332 unsigned int child_irq;
333 child_irq = irq_find_mapping(adnp->gpio.irqdomain,
335 handle_nested_irq(child_irq);
342 static void adnp_irq_mask(struct irq_data *d)
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
345 struct adnp *adnp = to_adnp(gc);
346 unsigned int reg = d->hwirq >> adnp->reg_shift;
347 unsigned int pos = d->hwirq & 7;
349 adnp->irq_enable[reg] &= ~BIT(pos);
352 static void adnp_irq_unmask(struct irq_data *d)
354 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
355 struct adnp *adnp = to_adnp(gc);
356 unsigned int reg = d->hwirq >> adnp->reg_shift;
357 unsigned int pos = d->hwirq & 7;
359 adnp->irq_enable[reg] |= BIT(pos);
362 static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
364 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 struct adnp *adnp = to_adnp(gc);
366 unsigned int reg = d->hwirq >> adnp->reg_shift;
367 unsigned int pos = d->hwirq & 7;
369 if (type & IRQ_TYPE_EDGE_RISING)
370 adnp->irq_rise[reg] |= BIT(pos);
372 adnp->irq_rise[reg] &= ~BIT(pos);
374 if (type & IRQ_TYPE_EDGE_FALLING)
375 adnp->irq_fall[reg] |= BIT(pos);
377 adnp->irq_fall[reg] &= ~BIT(pos);
379 if (type & IRQ_TYPE_LEVEL_HIGH)
380 adnp->irq_high[reg] |= BIT(pos);
382 adnp->irq_high[reg] &= ~BIT(pos);
384 if (type & IRQ_TYPE_LEVEL_LOW)
385 adnp->irq_low[reg] |= BIT(pos);
387 adnp->irq_low[reg] &= ~BIT(pos);
392 static void adnp_irq_bus_lock(struct irq_data *d)
394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
395 struct adnp *adnp = to_adnp(gc);
397 mutex_lock(&adnp->irq_lock);
400 static void adnp_irq_bus_unlock(struct irq_data *d)
402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 struct adnp *adnp = to_adnp(gc);
404 unsigned int num_regs = 1 << adnp->reg_shift, i;
406 mutex_lock(&adnp->i2c_lock);
408 for (i = 0; i < num_regs; i++)
409 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
411 mutex_unlock(&adnp->i2c_lock);
412 mutex_unlock(&adnp->irq_lock);
415 static struct irq_chip adnp_irq_chip = {
417 .irq_mask = adnp_irq_mask,
418 .irq_unmask = adnp_irq_unmask,
419 .irq_set_type = adnp_irq_set_type,
420 .irq_bus_lock = adnp_irq_bus_lock,
421 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
424 static int adnp_irq_setup(struct adnp *adnp)
426 unsigned int num_regs = 1 << adnp->reg_shift, i;
427 struct gpio_chip *chip = &adnp->gpio;
430 mutex_init(&adnp->irq_lock);
433 * Allocate memory to keep track of the current level and trigger
434 * modes of the interrupts. To avoid multiple allocations, a single
435 * large buffer is allocated and pointers are setup to point at the
436 * corresponding offsets. For consistency, the layout of the buffer
437 * is chosen to match the register layout of the hardware in that
438 * each segment contains the corresponding bits for all interrupts.
440 adnp->irq_enable = devm_kzalloc(chip->dev, num_regs * 6, GFP_KERNEL);
441 if (!adnp->irq_enable)
444 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
445 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
446 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
447 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
448 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
450 for (i = 0; i < num_regs; i++) {
452 * Read the initial level of all pins to allow the emulation
453 * of edge triggered interrupts.
455 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
459 /* disable all interrupts */
460 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
464 adnp->irq_enable[i] = 0x00;
467 err = devm_request_threaded_irq(chip->dev, adnp->client->irq,
469 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
470 dev_name(chip->dev), adnp);
472 dev_err(chip->dev, "can't request IRQ#%d: %d\n",
473 adnp->client->irq, err);
477 err = gpiochip_irqchip_add(chip,
484 "could not connect irqchip to gpiochip\n");
491 static int adnp_i2c_probe(struct i2c_client *client,
492 const struct i2c_device_id *id)
494 struct device_node *np = client->dev.of_node;
499 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
503 client->irq = irq_of_parse_and_map(np, 0);
505 return -EPROBE_DEFER;
507 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
511 mutex_init(&adnp->i2c_lock);
512 adnp->client = client;
514 err = adnp_gpio_setup(adnp, num_gpios);
518 if (of_find_property(np, "interrupt-controller", NULL)) {
519 err = adnp_irq_setup(adnp);
524 i2c_set_clientdata(client, adnp);
529 static int adnp_i2c_remove(struct i2c_client *client)
531 struct adnp *adnp = i2c_get_clientdata(client);
533 gpiochip_remove(&adnp->gpio);
537 static const struct i2c_device_id adnp_i2c_id[] = {
541 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
543 static const struct of_device_id adnp_of_match[] = {
544 { .compatible = "ad,gpio-adnp", },
547 MODULE_DEVICE_TABLE(of, adnp_of_match);
549 static struct i2c_driver adnp_i2c_driver = {
552 .owner = THIS_MODULE,
553 .of_match_table = adnp_of_match,
555 .probe = adnp_i2c_probe,
556 .remove = adnp_i2c_remove,
557 .id_table = adnp_i2c_id,
559 module_i2c_driver(adnp_i2c_driver);
561 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
562 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
563 MODULE_LICENSE("GPL");