1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
6 * Joe Hershberger <joe.hershberger@ni.com>
13 #include <asm/cache.h>
17 #include <linux/delay.h>
18 #include <linux/sizes.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/sys_proto.h>
22 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
23 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
24 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
25 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
26 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
27 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
28 #define DEVCFG_ISR_DMA_DONE 0x00002000
29 #define DEVCFG_ISR_PCFG_DONE 0x00000004
30 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
31 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
32 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
33 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
34 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
35 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
36 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
38 #ifndef CONFIG_SYS_FPGA_WAIT
39 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
42 #ifndef CONFIG_SYS_FPGA_PROG_TIME
43 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
46 #define DUMMY_WORD 0xffffffff
48 /* Xilinx binary format header */
49 static const u32 bin_format[] = {
50 DUMMY_WORD, /* Dummy words */
58 0x000000bb, /* Sync word */
59 0x11220044, /* Sync word */
62 0xaa995566, /* Sync word */
69 * Load the whole word from unaligned buffer
70 * Keep in your mind that it is byte loading on little-endian system
72 static u32 load_word(const void *buf, u32 swap)
78 if (swap == SWAP_NO) {
79 for (p = 0; p < 4; p++) {
84 for (p = 3; p >= 0; p--) {
93 static u32 check_header(const void *buf)
97 u32 *test = (u32 *)buf;
99 debug("%s: Let's check bitstream header\n", __func__);
101 /* Checking that passing bin is not a bitstream */
102 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
103 pattern = load_word(&test[i], swap);
106 * Bitstreams in binary format are swapped
107 * compare to regular bistream.
108 * Do not swap dummy word but if swap is done assume
109 * that parsing buffer is binary format
111 if ((__swab32(pattern) != DUMMY_WORD) &&
112 (__swab32(pattern) == bin_format[i])) {
113 pattern = __swab32(pattern);
115 debug("%s: data swapped - let's swap\n", __func__);
118 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
119 (u32)&test[i], pattern, bin_format[i]);
120 if (pattern != bin_format[i]) {
121 debug("%s: Bitstream is not recognized\n", __func__);
125 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
126 (u32)buf, swap == SWAP_NO ? "without" : "with");
131 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
133 u32 word, p = 0; /* possition */
135 /* Because buf doesn't need to be aligned let's read it by chars */
136 for (p = 0; p < bsize; p++) {
137 word = load_word(&buf[p], SWAP_NO);
138 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
140 /* Find the first bitstream dummy word */
141 if (word == DUMMY_WORD) {
142 debug("%s: Found dummy word at position %x/%x\n",
143 __func__, p, (u32)&buf[p]);
144 *swap = check_header(&buf[p]);
146 /* FIXME add full bitstream checking here */
150 /* Loop can be huge - support CTRL + C */
157 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
162 /* Set up the transfer */
163 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
164 writel(dstbuf, &devcfg_base->dma_dst_addr);
165 writel(srclen, &devcfg_base->dma_src_len);
166 writel(dstlen, &devcfg_base->dma_dst_len);
168 isr_status = readl(&devcfg_base->int_sts);
170 /* Polling the PCAP_INIT status for Set */
172 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
173 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
174 debug("%s: Error: isr = 0x%08X\n", __func__,
176 debug("%s: Write count = 0x%08X\n", __func__,
177 readl(&devcfg_base->write_count));
178 debug("%s: Read count = 0x%08X\n", __func__,
179 readl(&devcfg_base->read_count));
183 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
184 printf("%s: Timeout wait for DMA to complete\n",
188 isr_status = readl(&devcfg_base->int_sts);
191 debug("%s: DMA transfer is done\n", __func__);
193 /* Clear out the DMA status */
194 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
199 static int zynq_dma_xfer_init(bitstream_type bstype)
201 u32 status, control, isr_status;
204 /* Clear loopback bit */
205 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
207 if (bstype != BIT_PARTIAL) {
208 zynq_slcr_devcfg_disable();
210 /* Setting PCFG_PROG_B signal to high */
211 control = readl(&devcfg_base->ctrl);
212 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
215 * Delay is required if AES efuse is selected as
218 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
221 /* Setting PCFG_PROG_B signal to low */
222 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
225 * Delay is required if AES efuse is selected as
228 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
231 /* Polling the PCAP_INIT status for Reset */
233 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
234 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
235 printf("%s: Timeout wait for INIT to clear\n",
241 /* Setting PCFG_PROG_B signal to high */
242 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
244 /* Polling the PCAP_INIT status for Set */
246 while (!(readl(&devcfg_base->status) &
247 DEVCFG_STATUS_PCFG_INIT)) {
248 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
249 printf("%s: Timeout wait for INIT to set\n",
256 isr_status = readl(&devcfg_base->int_sts);
258 /* Clear it all, so if Boot ROM comes back, it can proceed */
259 writel(0xFFFFFFFF, &devcfg_base->int_sts);
261 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
262 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
264 /* If RX FIFO overflow, need to flush RX FIFO first */
265 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
266 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
267 writel(0xFFFFFFFF, &devcfg_base->int_sts);
272 status = readl(&devcfg_base->status);
274 debug("%s: Status = 0x%08X\n", __func__, status);
276 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
277 debug("%s: Error: device busy\n", __func__);
281 debug("%s: Device ready\n", __func__);
283 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
284 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
285 /* Error state, transfer cannot occur */
286 debug("%s: ISR indicates error\n", __func__);
289 /* Clear out the status */
290 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
294 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
295 /* Clear the count of completed DMA transfers */
296 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
302 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
307 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
308 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
311 * This might be dangerous but permits to flash if
312 * ARCH_DMA_MINALIGN is greater than header size
315 debug("%s: Aligned buffer is after buffer start\n",
317 new_buf -= ARCH_DMA_MINALIGN;
319 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
320 (u32)buf, (u32)new_buf, swap);
322 for (i = 0; i < (len/4); i++)
323 new_buf[i] = load_word(&buf[i], swap);
326 } else if (swap != SWAP_DONE) {
327 /* For bitstream which are aligned */
328 u32 *new_buf = (u32 *)buf;
330 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
333 for (i = 0; i < (len/4); i++)
334 new_buf[i] = load_word(&buf[i], swap);
340 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
341 size_t bsize, u32 blocksize, u32 *swap,
342 bitstream_type *bstype)
347 buf_start = check_data((u8 *)buf, blocksize, swap);
352 /* Check if data is postpone from start */
353 diff = (u32)buf_start - (u32)buf;
355 printf("%s: Bitstream is not validated yet (diff %x)\n",
360 if ((u32)buf < SZ_1M) {
361 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
366 if (zynq_dma_xfer_init(*bstype))
372 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
373 bitstream_type bstype)
375 unsigned long ts; /* Timestamp */
376 u32 isr_status, swap;
379 * send bsize inplace of blocksize as it was not a bitstream
382 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
386 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
388 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
389 debug("%s: Size = %zu\n", __func__, bsize);
391 /* flush(clean & invalidate) d-cache range buf */
392 flush_dcache_range((u32)buf, (u32)buf +
393 roundup(bsize, ARCH_DMA_MINALIGN));
395 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
398 isr_status = readl(&devcfg_base->int_sts);
399 /* Check FPGA configuration completion */
401 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
402 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
403 printf("%s: Timeout wait for FPGA to config\n",
407 isr_status = readl(&devcfg_base->int_sts);
410 debug("%s: FPGA config done\n", __func__);
412 if (bstype != BIT_PARTIAL)
413 zynq_slcr_devcfg_enable();
415 puts("INFO:post config was not run, please run manually if needed\n");
420 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
421 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
422 fpga_fs_info *fsinfo)
424 unsigned long ts; /* Timestamp */
425 u32 isr_status, swap;
427 loff_t blocksize, actread;
430 char *interface, *dev_part;
431 const char *filename;
433 blocksize = fsinfo->blocksize;
434 interface = fsinfo->interface;
435 dev_part = fsinfo->dev_part;
436 filename = fsinfo->filename;
437 fstype = fsinfo->fstype;
439 if (fs_set_blk_dev(interface, dev_part, fstype))
442 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
445 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
452 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
454 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
461 if (fs_set_blk_dev(interface, dev_part, fstype))
464 if (bsize > blocksize) {
465 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
468 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
471 } while (bsize > blocksize);
473 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
475 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
480 isr_status = readl(&devcfg_base->int_sts);
482 /* Check FPGA configuration completion */
484 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
485 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
486 printf("%s: Timeout wait for FPGA to config\n",
490 isr_status = readl(&devcfg_base->int_sts);
493 debug("%s: FPGA config done\n", __func__);
496 zynq_slcr_devcfg_enable();
502 struct xilinx_fpga_op zynq_op = {
504 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
505 .loadfs = zynq_loadfs,
509 #ifdef CONFIG_CMD_ZYNQ_AES
511 * Load the encrypted image from src addr and decrypt the image and
512 * place it back the decrypted image into dstaddr.
514 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
516 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
517 printf("%s: src and dst addr should be > 1M\n",
522 if (zynq_dma_xfer_init(BIT_NONE)) {
523 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
527 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
530 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
531 debug("%s: Size = %zu\n", __func__, srclen);
533 /* flush(clean & invalidate) d-cache range buf */
534 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
535 roundup(srclen << 2, ARCH_DMA_MINALIGN));
537 * Flush destination address range only if image is not
540 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
541 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
543 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
546 writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),