1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
6 * Joe Hershberger <joe.hershberger@ni.com>
15 #include <linux/sizes.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/sys_proto.h>
19 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
20 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
21 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
22 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
23 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
24 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
25 #define DEVCFG_ISR_DMA_DONE 0x00002000
26 #define DEVCFG_ISR_PCFG_DONE 0x00000004
27 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
28 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
29 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
30 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
31 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
32 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
33 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
35 #ifndef CONFIG_SYS_FPGA_WAIT
36 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
39 #ifndef CONFIG_SYS_FPGA_PROG_TIME
40 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
43 #define DUMMY_WORD 0xffffffff
45 /* Xilinx binary format header */
46 static const u32 bin_format[] = {
47 DUMMY_WORD, /* Dummy words */
55 0x000000bb, /* Sync word */
56 0x11220044, /* Sync word */
59 0xaa995566, /* Sync word */
66 * Load the whole word from unaligned buffer
67 * Keep in your mind that it is byte loading on little-endian system
69 static u32 load_word(const void *buf, u32 swap)
75 if (swap == SWAP_NO) {
76 for (p = 0; p < 4; p++) {
81 for (p = 3; p >= 0; p--) {
90 static u32 check_header(const void *buf)
94 u32 *test = (u32 *)buf;
96 debug("%s: Let's check bitstream header\n", __func__);
98 /* Checking that passing bin is not a bitstream */
99 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
100 pattern = load_word(&test[i], swap);
103 * Bitstreams in binary format are swapped
104 * compare to regular bistream.
105 * Do not swap dummy word but if swap is done assume
106 * that parsing buffer is binary format
108 if ((__swab32(pattern) != DUMMY_WORD) &&
109 (__swab32(pattern) == bin_format[i])) {
110 pattern = __swab32(pattern);
112 debug("%s: data swapped - let's swap\n", __func__);
115 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
116 (u32)&test[i], pattern, bin_format[i]);
117 if (pattern != bin_format[i]) {
118 debug("%s: Bitstream is not recognized\n", __func__);
122 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
123 (u32)buf, swap == SWAP_NO ? "without" : "with");
128 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
130 u32 word, p = 0; /* possition */
132 /* Because buf doesn't need to be aligned let's read it by chars */
133 for (p = 0; p < bsize; p++) {
134 word = load_word(&buf[p], SWAP_NO);
135 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
137 /* Find the first bitstream dummy word */
138 if (word == DUMMY_WORD) {
139 debug("%s: Found dummy word at position %x/%x\n",
140 __func__, p, (u32)&buf[p]);
141 *swap = check_header(&buf[p]);
143 /* FIXME add full bitstream checking here */
147 /* Loop can be huge - support CTRL + C */
154 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
159 /* Set up the transfer */
160 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
161 writel(dstbuf, &devcfg_base->dma_dst_addr);
162 writel(srclen, &devcfg_base->dma_src_len);
163 writel(dstlen, &devcfg_base->dma_dst_len);
165 isr_status = readl(&devcfg_base->int_sts);
167 /* Polling the PCAP_INIT status for Set */
169 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
170 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
171 debug("%s: Error: isr = 0x%08X\n", __func__,
173 debug("%s: Write count = 0x%08X\n", __func__,
174 readl(&devcfg_base->write_count));
175 debug("%s: Read count = 0x%08X\n", __func__,
176 readl(&devcfg_base->read_count));
180 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
181 printf("%s: Timeout wait for DMA to complete\n",
185 isr_status = readl(&devcfg_base->int_sts);
188 debug("%s: DMA transfer is done\n", __func__);
190 /* Clear out the DMA status */
191 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
196 static int zynq_dma_xfer_init(bitstream_type bstype)
198 u32 status, control, isr_status;
201 /* Clear loopback bit */
202 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
204 if (bstype != BIT_PARTIAL) {
205 zynq_slcr_devcfg_disable();
207 /* Setting PCFG_PROG_B signal to high */
208 control = readl(&devcfg_base->ctrl);
209 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
212 * Delay is required if AES efuse is selected as
215 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
218 /* Setting PCFG_PROG_B signal to low */
219 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
222 * Delay is required if AES efuse is selected as
225 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
228 /* Polling the PCAP_INIT status for Reset */
230 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
231 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
232 printf("%s: Timeout wait for INIT to clear\n",
238 /* Setting PCFG_PROG_B signal to high */
239 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
241 /* Polling the PCAP_INIT status for Set */
243 while (!(readl(&devcfg_base->status) &
244 DEVCFG_STATUS_PCFG_INIT)) {
245 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
246 printf("%s: Timeout wait for INIT to set\n",
253 isr_status = readl(&devcfg_base->int_sts);
255 /* Clear it all, so if Boot ROM comes back, it can proceed */
256 writel(0xFFFFFFFF, &devcfg_base->int_sts);
258 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
259 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
261 /* If RX FIFO overflow, need to flush RX FIFO first */
262 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
263 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
264 writel(0xFFFFFFFF, &devcfg_base->int_sts);
269 status = readl(&devcfg_base->status);
271 debug("%s: Status = 0x%08X\n", __func__, status);
273 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
274 debug("%s: Error: device busy\n", __func__);
278 debug("%s: Device ready\n", __func__);
280 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
281 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
282 /* Error state, transfer cannot occur */
283 debug("%s: ISR indicates error\n", __func__);
286 /* Clear out the status */
287 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
291 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
292 /* Clear the count of completed DMA transfers */
293 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
299 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
304 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
305 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
308 * This might be dangerous but permits to flash if
309 * ARCH_DMA_MINALIGN is greater than header size
312 debug("%s: Aligned buffer is after buffer start\n",
314 new_buf -= ARCH_DMA_MINALIGN;
316 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
317 (u32)buf, (u32)new_buf, swap);
319 for (i = 0; i < (len/4); i++)
320 new_buf[i] = load_word(&buf[i], swap);
323 } else if (swap != SWAP_DONE) {
324 /* For bitstream which are aligned */
325 u32 *new_buf = (u32 *)buf;
327 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
330 for (i = 0; i < (len/4); i++)
331 new_buf[i] = load_word(&buf[i], swap);
337 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
338 size_t bsize, u32 blocksize, u32 *swap,
339 bitstream_type *bstype)
344 buf_start = check_data((u8 *)buf, blocksize, swap);
349 /* Check if data is postpone from start */
350 diff = (u32)buf_start - (u32)buf;
352 printf("%s: Bitstream is not validated yet (diff %x)\n",
357 if ((u32)buf < SZ_1M) {
358 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
363 if (zynq_dma_xfer_init(*bstype))
369 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
370 bitstream_type bstype)
372 unsigned long ts; /* Timestamp */
373 u32 isr_status, swap;
376 * send bsize inplace of blocksize as it was not a bitstream
379 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
383 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
385 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
386 debug("%s: Size = %zu\n", __func__, bsize);
388 /* flush(clean & invalidate) d-cache range buf */
389 flush_dcache_range((u32)buf, (u32)buf +
390 roundup(bsize, ARCH_DMA_MINALIGN));
392 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
395 isr_status = readl(&devcfg_base->int_sts);
396 /* Check FPGA configuration completion */
398 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
399 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
400 printf("%s: Timeout wait for FPGA to config\n",
404 isr_status = readl(&devcfg_base->int_sts);
407 debug("%s: FPGA config done\n", __func__);
409 if (bstype != BIT_PARTIAL)
410 zynq_slcr_devcfg_enable();
412 puts("INFO:post config was not run, please run manually if needed\n");
417 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
418 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
419 fpga_fs_info *fsinfo)
421 unsigned long ts; /* Timestamp */
422 u32 isr_status, swap;
424 loff_t blocksize, actread;
427 char *interface, *dev_part;
428 const char *filename;
430 blocksize = fsinfo->blocksize;
431 interface = fsinfo->interface;
432 dev_part = fsinfo->dev_part;
433 filename = fsinfo->filename;
434 fstype = fsinfo->fstype;
436 if (fs_set_blk_dev(interface, dev_part, fstype))
439 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
442 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
449 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
451 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
458 if (fs_set_blk_dev(interface, dev_part, fstype))
461 if (bsize > blocksize) {
462 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
465 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
468 } while (bsize > blocksize);
470 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
472 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
477 isr_status = readl(&devcfg_base->int_sts);
479 /* Check FPGA configuration completion */
481 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
482 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
483 printf("%s: Timeout wait for FPGA to config\n",
487 isr_status = readl(&devcfg_base->int_sts);
490 debug("%s: FPGA config done\n", __func__);
493 zynq_slcr_devcfg_enable();
499 struct xilinx_fpga_op zynq_op = {
501 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
502 .loadfs = zynq_loadfs,
506 #ifdef CONFIG_CMD_ZYNQ_AES
508 * Load the encrypted image from src addr and decrypt the image and
509 * place it back the decrypted image into dstaddr.
511 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
513 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
514 printf("%s: src and dst addr should be > 1M\n",
519 if (zynq_dma_xfer_init(BIT_NONE)) {
520 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
524 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
527 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
528 debug("%s: Size = %zu\n", __func__, srclen);
530 /* flush(clean & invalidate) d-cache range buf */
531 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
532 roundup(srclen << 2, ARCH_DMA_MINALIGN));
534 * Flush destination address range only if image is not
537 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
538 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
540 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
543 writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),