1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 - 2016, Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
11 #include <linux/sizes.h>
12 #include <asm/arch/sys_proto.h>
15 #define DUMMY_WORD 0xffffffff
17 /* Xilinx binary format header */
18 static const u32 bin_format[] = {
19 DUMMY_WORD, /* Dummy words */
35 0x000000bb, /* Sync word */
36 0x11220044, /* Sync word */
39 0xaa995566, /* Sync word */
46 * Load the whole word from unaligned buffer
47 * Keep in your mind that it is byte loading on little-endian system
49 static u32 load_word(const void *buf, u32 swap)
55 if (swap == SWAP_NO) {
56 for (p = 0; p < 4; p++) {
61 for (p = 3; p >= 0; p--) {
70 static u32 check_header(const void *buf)
74 u32 *test = (u32 *)buf;
76 debug("%s: Let's check bitstream header\n", __func__);
78 /* Checking that passing bin is not a bitstream */
79 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
80 pattern = load_word(&test[i], swap);
83 * Bitstreams in binary format are swapped
84 * compare to regular bistream.
85 * Do not swap dummy word but if swap is done assume
86 * that parsing buffer is binary format
88 if ((__swab32(pattern) != DUMMY_WORD) &&
89 (__swab32(pattern) == bin_format[i])) {
91 debug("%s: data swapped - let's swap\n", __func__);
94 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
95 &test[i], pattern, bin_format[i]);
97 debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
98 buf, swap == SWAP_NO ? "without" : "with");
103 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
105 u32 word, p = 0; /* possition */
107 /* Because buf doesn't need to be aligned let's read it by chars */
108 for (p = 0; p < bsize; p++) {
109 word = load_word(&buf[p], SWAP_NO);
110 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
112 /* Find the first bitstream dummy word */
113 if (word == DUMMY_WORD) {
114 debug("%s: Found dummy word at position %x/%px\n",
115 __func__, p, &buf[p]);
116 *swap = check_header(&buf[p]);
118 /* FIXME add full bitstream checking here */
122 /* Loop can be huge - support CTRL + C */
129 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
134 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
135 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
138 * This might be dangerous but permits to flash if
139 * ARCH_DMA_MINALIGN is greater than header size
141 if (new_buf > (u32 *)buf) {
142 debug("%s: Aligned buffer is after buffer start\n",
144 new_buf -= ARCH_DMA_MINALIGN;
146 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
149 for (i = 0; i < (len/4); i++)
150 new_buf[i] = load_word(&buf[i], swap);
153 } else if ((swap != SWAP_DONE) &&
154 (zynqmp_pmufw_version() <= PMUFW_V1_0)) {
155 /* For bitstream which are aligned */
156 u32 *new_buf = (u32 *)buf;
158 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
161 for (i = 0; i < (len/4); i++)
162 new_buf[i] = load_word(&buf[i], swap);
168 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
169 size_t bsize, u32 blocksize, u32 *swap)
174 buf_start = check_data((u8 *)buf, blocksize, swap);
179 /* Check if data is postpone from start */
180 diff = (ulong)buf_start - (ulong)buf;
182 printf("%s: Bitstream is not validated yet (diff %lx)\n",
187 if ((ulong)buf < SZ_1M) {
188 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
196 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
197 bitstream_type bstype)
199 ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
204 u32 ret_payload[PAYLOAD_ARG_CNT];
205 bool xilfpga_old = false;
207 if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
208 puts("WARN: PMUFW v1.0 or less is detected\n");
209 puts("WARN: Not all bitstream formats are supported\n");
210 puts("WARN: Please upgrade PMUFW\n");
212 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
214 bsizeptr = (u32 *)&bsize;
215 flush_dcache_range((ulong)bsizeptr,
216 (ulong)bsizeptr + sizeof(size_t));
217 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
220 bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
222 debug("%s called!\n", __func__);
223 flush_dcache_range(bin_buf, bin_buf + bsize);
225 buf_lo = (u32)bin_buf;
226 buf_hi = upper_32_bits(bin_buf);
229 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
230 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
232 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
233 (u32)bsize, 0, ret_payload);
236 debug("PL FPGA LOAD fail\n");
241 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
242 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
243 struct fpga_secure_info *fpga_sec_info)
247 u32 ret_payload[PAYLOAD_ARG_CNT];
250 flush_dcache_range((ulong)buf, (ulong)buf +
251 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
253 if (!fpga_sec_info->encflag)
254 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
256 if (fpga_sec_info->userkey_addr &&
257 fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
258 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
259 (ulong)fpga_sec_info->userkey_addr +
261 CONFIG_SYS_CACHELINE_SIZE));
262 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
265 if (!fpga_sec_info->authflag)
266 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
268 if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
269 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
271 buf_lo = lower_32_bits((ulong)buf);
272 buf_hi = upper_32_bits((ulong)buf);
274 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
275 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
278 puts("PL FPGA LOAD fail\n");
280 puts("Bitstream successfully loaded\n");
286 static int zynqmp_pcap_info(xilinx_desc *desc)
289 u32 ret_payload[PAYLOAD_ARG_CNT];
291 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
294 printf("PCAP status\t0x%x\n", ret_payload[1]);
299 struct xilinx_fpga_op zynqmp_op = {
301 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
302 .loads = zynqmp_loads,
304 .info = zynqmp_pcap_info,