drivers/fpga/zynqmppl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2015 - 2016, Xilinx, Inc,
   4  * Michal Simek <michal.simek@xilinx.com>
   5  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
   6  */
   7
   8 #include <console.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <zynqmppl.h>
  12 #include <zynqmp_firmware.h>
  13 #include <linux/sizes.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <memalign.h>
  16
  17 #define DUMMY_WORD      0xffffffff
  18
  19 /* Xilinx binary format header */
  20 static const u32 bin_format[] = {
  21         DUMMY_WORD, /* Dummy words */
  22         DUMMY_WORD,
  23         DUMMY_WORD,
  24         DUMMY_WORD,
  25         DUMMY_WORD,
  26         DUMMY_WORD,
  27         DUMMY_WORD,
  28         DUMMY_WORD,
  29         DUMMY_WORD,
  30         DUMMY_WORD,
  31         DUMMY_WORD,
  32         DUMMY_WORD,
  33         DUMMY_WORD,
  34         DUMMY_WORD,
  35         DUMMY_WORD,
  36         DUMMY_WORD,
  37         0x000000bb, /* Sync word */
  38         0x11220044, /* Sync word */
  39         DUMMY_WORD,
  40         DUMMY_WORD,
  41         0xaa995566, /* Sync word */
  42 };
  43
  44 #define SWAP_NO         1
  45 #define SWAP_DONE       2
  46
  47 /*
  48  * Load the whole word from unaligned buffer
  49  * Keep in your mind that it is byte loading on little-endian system
  50  */
  51 static u32 load_word(const void *buf, u32 swap)
  52 {
  53         u32 word = 0;
  54         u8 *bitc = (u8 *)buf;
  55         int p;
  56
  57         if (swap == SWAP_NO) {
  58                 for (p = 0; p < 4; p++) {
  59                         word <<= 8;
  60                         word |= bitc[p];
  61                 }
  62         } else {
  63                 for (p = 3; p >= 0; p--) {
  64                         word <<= 8;
  65                         word |= bitc[p];
  66                 }
  67         }
  68
  69         return word;
  70 }
  71
  72 static u32 check_header(const void *buf)
  73 {
  74         u32 i, pattern;
  75         int swap = SWAP_NO;
  76         u32 *test = (u32 *)buf;
  77
  78         debug("%s: Let's check bitstream header\n", __func__);
  79
  80         /* Checking that passing bin is not a bitstream */
  81         for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  82                 pattern = load_word(&test[i], swap);
  83
  84                 /*
  85                  * Bitstreams in binary format are swapped
  86                  * compare to regular bistream.
  87                  * Do not swap dummy word but if swap is done assume
  88                  * that parsing buffer is binary format
  89                  */
  90                 if ((__swab32(pattern) != DUMMY_WORD) &&
  91                     (__swab32(pattern) == bin_format[i])) {
  92                         swap = SWAP_DONE;
  93                         debug("%s: data swapped - let's swap\n", __func__);
  94                 }
  95
  96                 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  97                       &test[i], pattern, bin_format[i]);
  98         }
  99         debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
 100               buf, swap == SWAP_NO ? "without" : "with");
 101
 102         return swap;
 103 }
 104
 105 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 106 {
 107         u32 word, p = 0; /* possition */
 108
 109         /* Because buf doesn't need to be aligned let's read it by chars */
 110         for (p = 0; p < bsize; p++) {
 111                 word = load_word(&buf[p], SWAP_NO);
 112                 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
 113
 114                 /* Find the first bitstream dummy word */
 115                 if (word == DUMMY_WORD) {
 116                         debug("%s: Found dummy word at position %x/%px\n",
 117                               __func__, p, &buf[p]);
 118                         *swap = check_header(&buf[p]);
 119                         if (*swap) {
 120                                 /* FIXME add full bitstream checking here */
 121                                 return &buf[p];
 122                         }
 123                 }
 124                 /* Loop can be huge - support CTRL + C */
 125                 if (ctrlc())
 126                         return NULL;
 127         }
 128         return NULL;
 129 }
 130
 131 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
 132 {
 133         u32 *new_buf;
 134         u32 i;
 135
 136         if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
 137                 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
 138
 139                 /*
 140                  * This might be dangerous but permits to flash if
 141                  * ARCH_DMA_MINALIGN is greater than header size
 142                  */
 143                 if (new_buf > (u32 *)buf) {
 144                         debug("%s: Aligned buffer is after buffer start\n",
 145                               __func__);
 146                         new_buf -= ARCH_DMA_MINALIGN;
 147                 }
 148                 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
 149                        buf, new_buf, swap);
 150
 151                 for (i = 0; i < (len/4); i++)
 152                         new_buf[i] = load_word(&buf[i], swap);
 153
 154                 buf = new_buf;
 155         } else if ((swap != SWAP_DONE) &&
 156                    (zynqmp_firmware_version() <= PMUFW_V1_0)) {
 157                 /* For bitstream which are aligned */
 158                 new_buf = buf;
 159
 160                 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
 161                        swap);
 162
 163                 for (i = 0; i < (len/4); i++)
 164                         new_buf[i] = load_word(&buf[i], swap);
 165         }
 166
 167         return (ulong)buf;
 168 }
 169
 170 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
 171                                    size_t bsize, u32 blocksize, u32 *swap)
 172 {
 173         ulong *buf_start;
 174         ulong diff;
 175
 176         buf_start = check_data((u8 *)buf, blocksize, swap);
 177
 178         if (!buf_start)
 179                 return FPGA_FAIL;
 180
 181         /* Check if data is postpone from start */
 182         diff = (ulong)buf_start - (ulong)buf;
 183         if (diff) {
 184                 printf("%s: Bitstream is not validated yet (diff %lx)\n",
 185                        __func__, diff);
 186                 return FPGA_FAIL;
 187         }
 188
 189         if ((ulong)buf < SZ_1M) {
 190                 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
 191                        __func__, buf);
 192                 return FPGA_FAIL;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 199                      bitstream_type bstype)
 200 {
 201         ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
 202         u32 swap = 0;
 203         ulong bin_buf;
 204         int ret;
 205         u32 buf_lo, buf_hi;
 206         u32 ret_payload[PAYLOAD_ARG_CNT];
 207         bool xilfpga_old = false;
 208
 209         if (zynqmp_firmware_version() <= PMUFW_V1_0) {
 210                 puts("WARN: PMUFW v1.0 or less is detected\n");
 211                 puts("WARN: Not all bitstream formats are supported\n");
 212                 puts("WARN: Please upgrade PMUFW\n");
 213                 xilfpga_old = true;
 214                 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
 215                         return FPGA_FAIL;
 216                 bsizeptr = (u32 *)&bsize;
 217                 flush_dcache_range((ulong)bsizeptr,
 218                                    (ulong)bsizeptr + sizeof(size_t));
 219                 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
 220         }
 221
 222         bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
 223
 224         debug("%s called!\n", __func__);
 225         flush_dcache_range(bin_buf, bin_buf + bsize);
 226
 227         buf_lo = (u32)bin_buf;
 228         buf_hi = upper_32_bits(bin_buf);
 229
 230         if (xilfpga_old)
 231                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 232                                         buf_hi, (u32)(uintptr_t)bsizeptr,
 233                                         bstype, ret_payload);
 234         else
 235                 ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 236                                         buf_hi, (u32)bsize, 0, ret_payload);
 237
 238         if (ret)
 239                 puts("PL FPGA LOAD fail\n");
 240
 241         return ret;
 242 }
 243
 244 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
 245 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
 246                         struct fpga_secure_info *fpga_sec_info)
 247 {
 248         int ret;
 249         u32 buf_lo, buf_hi;
 250         u32 ret_payload[PAYLOAD_ARG_CNT];
 251         u8 flag = 0;
 252
 253         flush_dcache_range((ulong)buf, (ulong)buf +
 254                            ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
 255
 256         if (!fpga_sec_info->encflag)
 257                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
 258
 259         if (fpga_sec_info->userkey_addr &&
 260             fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
 261                 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
 262                                    (ulong)fpga_sec_info->userkey_addr +
 263                                    ALIGN(KEY_PTR_LEN,
 264                                          CONFIG_SYS_CACHELINE_SIZE));
 265                 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
 266         }
 267
 268         if (!fpga_sec_info->authflag)
 269                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
 270
 271         if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
 272                 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
 273
 274         buf_lo = lower_32_bits((ulong)buf);
 275         buf_hi = upper_32_bits((ulong)buf);
 276
 277         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
 278                                 buf_hi,
 279                          (u32)(uintptr_t)fpga_sec_info->userkey_addr,
 280                          flag, ret_payload);
 281         if (ret)
 282                 puts("PL FPGA LOAD fail\n");
 283         else
 284                 puts("Bitstream successfully loaded\n");
 285
 286         return ret;
 287 }
 288 #endif
 289
 290 static int zynqmp_pcap_info(xilinx_desc *desc)
 291 {
 292         int ret;
 293         u32 ret_payload[PAYLOAD_ARG_CNT];
 294
 295         ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
 296                                 0, ret_payload);
 297         if (!ret)
 298                 printf("PCAP status\t0x%x\n", ret_payload[1]);
 299
 300         return ret;
 301 }
 302
 303 struct xilinx_fpga_op zynqmp_op = {
 304         .load = zynqmp_load,
 305 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
 306         .loads = zynqmp_loads,
 307 #endif
 308         .info = zynqmp_pcap_info,
 309 };