1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2015 - 2016, Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
11 #include <zynqmp_firmware.h>
12 #include <linux/sizes.h>
13 #include <asm/arch/sys_proto.h>
16 #define DUMMY_WORD 0xffffffff
18 /* Xilinx binary format header */
19 static const u32 bin_format[] = {
20 DUMMY_WORD, /* Dummy words */
36 0x000000bb, /* Sync word */
37 0x11220044, /* Sync word */
40 0xaa995566, /* Sync word */
47 * Load the whole word from unaligned buffer
48 * Keep in your mind that it is byte loading on little-endian system
50 static u32 load_word(const void *buf, u32 swap)
56 if (swap == SWAP_NO) {
57 for (p = 0; p < 4; p++) {
62 for (p = 3; p >= 0; p--) {
71 static u32 check_header(const void *buf)
75 u32 *test = (u32 *)buf;
77 debug("%s: Let's check bitstream header\n", __func__);
79 /* Checking that passing bin is not a bitstream */
80 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
81 pattern = load_word(&test[i], swap);
84 * Bitstreams in binary format are swapped
85 * compare to regular bistream.
86 * Do not swap dummy word but if swap is done assume
87 * that parsing buffer is binary format
89 if ((__swab32(pattern) != DUMMY_WORD) &&
90 (__swab32(pattern) == bin_format[i])) {
92 debug("%s: data swapped - let's swap\n", __func__);
95 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
96 &test[i], pattern, bin_format[i]);
98 debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
99 buf, swap == SWAP_NO ? "without" : "with");
104 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
106 u32 word, p = 0; /* possition */
108 /* Because buf doesn't need to be aligned let's read it by chars */
109 for (p = 0; p < bsize; p++) {
110 word = load_word(&buf[p], SWAP_NO);
111 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
113 /* Find the first bitstream dummy word */
114 if (word == DUMMY_WORD) {
115 debug("%s: Found dummy word at position %x/%px\n",
116 __func__, p, &buf[p]);
117 *swap = check_header(&buf[p]);
119 /* FIXME add full bitstream checking here */
123 /* Loop can be huge - support CTRL + C */
130 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
135 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
136 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
139 * This might be dangerous but permits to flash if
140 * ARCH_DMA_MINALIGN is greater than header size
142 if (new_buf > (u32 *)buf) {
143 debug("%s: Aligned buffer is after buffer start\n",
145 new_buf -= ARCH_DMA_MINALIGN;
147 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
150 for (i = 0; i < (len/4); i++)
151 new_buf[i] = load_word(&buf[i], swap);
154 } else if ((swap != SWAP_DONE) &&
155 (zynqmp_firmware_version() <= PMUFW_V1_0)) {
156 /* For bitstream which are aligned */
159 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
162 for (i = 0; i < (len/4); i++)
163 new_buf[i] = load_word(&buf[i], swap);
169 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
170 size_t bsize, u32 blocksize, u32 *swap)
175 buf_start = check_data((u8 *)buf, blocksize, swap);
180 /* Check if data is postpone from start */
181 diff = (ulong)buf_start - (ulong)buf;
183 printf("%s: Bitstream is not validated yet (diff %lx)\n",
188 if ((ulong)buf < SZ_1M) {
189 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
197 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
198 bitstream_type bstype)
200 ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
205 u32 ret_payload[PAYLOAD_ARG_CNT];
206 bool xilfpga_old = false;
208 if (zynqmp_firmware_version() <= PMUFW_V1_0) {
209 puts("WARN: PMUFW v1.0 or less is detected\n");
210 puts("WARN: Not all bitstream formats are supported\n");
211 puts("WARN: Please upgrade PMUFW\n");
213 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
215 bsizeptr = (u32 *)&bsize;
216 flush_dcache_range((ulong)bsizeptr,
217 (ulong)bsizeptr + sizeof(size_t));
218 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
221 bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
223 debug("%s called!\n", __func__);
224 flush_dcache_range(bin_buf, bin_buf + bsize);
226 buf_lo = (u32)bin_buf;
227 buf_hi = upper_32_bits(bin_buf);
230 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
231 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
233 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
234 (u32)bsize, 0, ret_payload);
237 puts("PL FPGA LOAD fail\n");
242 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
243 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
244 struct fpga_secure_info *fpga_sec_info)
248 u32 ret_payload[PAYLOAD_ARG_CNT];
251 flush_dcache_range((ulong)buf, (ulong)buf +
252 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
254 if (!fpga_sec_info->encflag)
255 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
257 if (fpga_sec_info->userkey_addr &&
258 fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
259 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
260 (ulong)fpga_sec_info->userkey_addr +
262 CONFIG_SYS_CACHELINE_SIZE));
263 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
266 if (!fpga_sec_info->authflag)
267 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
269 if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
270 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
272 buf_lo = lower_32_bits((ulong)buf);
273 buf_hi = upper_32_bits((ulong)buf);
275 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
276 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
279 puts("PL FPGA LOAD fail\n");
281 puts("Bitstream successfully loaded\n");
287 static int zynqmp_pcap_info(xilinx_desc *desc)
290 u32 ret_payload[PAYLOAD_ARG_CNT];
292 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
295 printf("PCAP status\t0x%x\n", ret_payload[1]);
300 struct xilinx_fpga_op zynqmp_op = {
302 #if defined CONFIG_CMD_FPGA_LOAD_SECURE
303 .loads = zynqmp_loads,
305 .info = zynqmp_pcap_info,