1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2019, Xilinx, Inc,
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
8 #include <asm/arch/sys_proto.h>
12 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
16 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
17 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
18 memcpy(new_buf, buf, len);
25 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
26 bitstream_type bstype)
33 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
35 debug("%s called!\n", __func__);
36 flush_dcache_range(bin_buf, bin_buf + bsize);
38 buf_lo = lower_32_bits(bin_buf);
39 buf_hi = upper_32_bits(bin_buf);
41 ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
42 buf_hi, 0, ret_payload);
44 puts("PL FPGA LOAD fail\n");
49 struct xilinx_fpga_op versal_op = {