1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2019, Xilinx, Inc,
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
8 #include <asm/arch/sys_proto.h>
11 #include <zynqmp_firmware.h>
13 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
17 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
18 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
19 memcpy(new_buf, buf, len);
26 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
27 bitstream_type bstype)
34 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
36 debug("%s called!\n", __func__);
37 flush_dcache_range(bin_buf, bin_buf + bsize);
39 buf_lo = lower_32_bits(bin_buf);
40 buf_hi = upper_32_bits(bin_buf);
42 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
43 buf_hi, 0, ret_payload);
45 puts("PL FPGA LOAD fail\n");
50 struct xilinx_fpga_op versal_op = {