1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 #include <linux/delay.h>
12 #include <linux/errno.h>
14 /* Write the RBF data to FPGA via SPI */
15 static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
16 unsigned long rbf_size)
18 struct spi_slave *slave;
21 debug("%s (%d): data=%p size=%ld\n",
22 __func__, __LINE__, rbf_data, rbf_size);
24 /* FIXME: How to get the max. SPI clock and SPI mode? */
25 slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
29 if (spi_claim_bus(slave))
32 ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
33 SPI_XFER_BEGIN | SPI_XFER_END);
35 spi_release_bus(slave);
41 * This is the interface used by FPGA driver.
42 * Return 0 for sucess, non-zero for error.
44 int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
46 altera_board_specific_func *pfns = desc->iface_fns;
47 int cookie = desc->cookie;
52 if ((u32)rbf_data & 0x3) {
53 puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
57 /* Run the pre configuration function if there is one */
61 /* Establish the initial state */
63 /* De-assert nCONFIG */
64 (pfns->config)(false, true, cookie);
66 /* nConfig minimum low pulse width is 2us */
70 (pfns->config)(true, true, cookie);
72 /* nCONFIG high to first rising clock on DCLK min 1506 us */
76 /* Write the RBF data to FPGA */
79 * Use board specific data function to write bitstream
82 ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
85 * Use common SPI functions to write bitstream into the
88 spi_bus = COOKIE2SPI_BUS(cookie);
89 spi_dev = COOKIE2SPI_DEV(cookie);
90 ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
97 ret = (pfns->done)(cookie);
100 printf("Error: DONE not set (ret=%d)!\n", ret);