drivers/fpga/socfpga_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
   4  */
   5 #include <image.h>
   6 #include <log.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/fpga_manager.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/misc.h>
  13 #include <altera.h>
  14 #include <asm/arch/pinmux.h>
  15 #include <common.h>
  16 #include <dm/ofnode.h>
  17 #include <errno.h>
  18 #include <fs_loader.h>
  19 #include <wait_bit.h>
  20 #include <watchdog.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23
  24 #define CFGWDTH_32      1
  25 #define MIN_BITSTREAM_SIZECHECK 230
  26 #define ENCRYPTION_OFFSET       69
  27 #define COMPRESSION_OFFSET      229
  28 #define FPGA_TIMEOUT_MSEC       1000  /* timeout in ms */
  29 #define FPGA_TIMEOUT_CNT        0x1000000
  30 #define DEFAULT_DDR_LOAD_ADDRESS        0x400
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static const struct socfpga_fpga_manager *fpga_manager_base =
  35                 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  36
  37 static void fpgamgr_set_cd_ratio(unsigned long ratio);
  38
  39 static uint32_t fpgamgr_get_msel(void)
  40 {
  41         u32 reg;
  42
  43         reg = readl(&fpga_manager_base->imgcfg_stat);
  44         reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  45                 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  46
  47         return reg;
  48 }
  49
  50 static void fpgamgr_set_cfgwdth(int width)
  51 {
  52         if (width)
  53                 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  54                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  55         else
  56                 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  57                         ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  58 }
  59
  60 int is_fpgamgr_user_mode(void)
  61 {
  62         return (readl(&fpga_manager_base->imgcfg_stat) &
  63                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  64 }
  65
  66 static int wait_for_user_mode(void)
  67 {
  68         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  69                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  70                 1, FPGA_TIMEOUT_MSEC, false);
  71 }
  72
  73 int is_fpgamgr_early_user_mode(void)
  74 {
  75         return (readl(&fpga_manager_base->imgcfg_stat) &
  76                 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  77 }
  78
  79 int fpgamgr_wait_early_user_mode(void)
  80 {
  81         u32 sync_data = 0xffffffff;
  82         u32 i = 0;
  83         unsigned start = get_timer(0);
  84         unsigned long cd_ratio;
  85
  86         /* Getting existing CDRATIO */
  87         cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  88                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  89                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  90
  91         /* Using CDRATIO_X1 for better compatibility */
  92         fpgamgr_set_cd_ratio(CDRATIO_x1);
  93
  94         while (!is_fpgamgr_early_user_mode()) {
  95                 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  96                         return -ETIMEDOUT;
  97                 fpgamgr_program_write((const long unsigned int *)&sync_data,
  98                                 sizeof(sync_data));
  99                 udelay(FPGA_TIMEOUT_MSEC);
 100                 i++;
 101         }
 102
 103         debug("FPGA: Additional %i sync word needed\n", i);
 104
 105         /* restoring original CDRATIO */
 106         fpgamgr_set_cd_ratio(cd_ratio);
 107
 108         return 0;
 109 }
 110
 111 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
 112 static int wait_for_nconfig_pin_and_nstatus_pin(void)
 113 {
 114         unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
 115                                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
 116
 117         /*
 118          * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
 119          * de-asserted, timeout at 1000ms
 120          */
 121         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
 122                                  true, FPGA_TIMEOUT_MSEC, false);
 123 }
 124
 125 static int wait_for_f2s_nstatus_pin(unsigned long value)
 126 {
 127         /* Poll until f2s to specific value, timeout at 1000ms */
 128         return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
 129                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
 130                 value, FPGA_TIMEOUT_MSEC, false);
 131 }
 132
 133 /* set CD ratio */
 134 static void fpgamgr_set_cd_ratio(unsigned long ratio)
 135 {
 136         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 137                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 138
 139         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 140                 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
 141                 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
 142 }
 143
 144 /* get the MSEL value, verify we are set for FPP configuration mode */
 145 static int fpgamgr_verify_msel(void)
 146 {
 147         u32 msel = fpgamgr_get_msel();
 148
 149         if (msel & ~BIT(0)) {
 150                 printf("Fail: read msel=%d\n", msel);
 151                 return -EPERM;
 152         }
 153
 154         return 0;
 155 }
 156
 157 /*
 158  * Write cdratio and cdwidth based on whether the bitstream is compressed
 159  * and/or encoded
 160  */
 161 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
 162                                        size_t rbf_size)
 163 {
 164         unsigned int cd_ratio;
 165         bool encrypt, compress;
 166
 167         /*
 168          * According to the bitstream specification,
 169          * both encryption and compression status are
 170          * in location before offset 230 of the buffer.
 171          */
 172         if (rbf_size < MIN_BITSTREAM_SIZECHECK)
 173                 return -EINVAL;
 174
 175         encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
 176         encrypt = encrypt != 0;
 177
 178         compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
 179         compress = !compress;
 180
 181         debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
 182         debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
 183         debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
 184              compress);
 185
 186         /*
 187          * from the register map description of cdratio in imgcfg_ctrl_02:
 188          *  Normal Configuration    : 32bit Passive Parallel
 189          *  Partial Reconfiguration : 16bit Passive Parallel
 190          */
 191
 192         /*
 193          * cd ratio is dependent on cfg width and whether the bitstream
 194          * is encrypted and/or compressed.
 195          *
 196          * | width | encr. | compr. | cd ratio |
 197          * |  16   |   0   |   0    |     1    |
 198          * |  16   |   0   |   1    |     4    |
 199          * |  16   |   1   |   0    |     2    |
 200          * |  16   |   1   |   1    |     4    |
 201          * |  32   |   0   |   0    |     1    |
 202          * |  32   |   0   |   1    |     8    |
 203          * |  32   |   1   |   0    |     4    |
 204          * |  32   |   1   |   1    |     8    |
 205          */
 206         if (!compress && !encrypt) {
 207                 cd_ratio = CDRATIO_x1;
 208         } else {
 209                 if (compress)
 210                         cd_ratio = CDRATIO_x4;
 211                 else
 212                         cd_ratio = CDRATIO_x2;
 213
 214                 /* if 32 bit, double the cd ratio (so register
 215                    field setting is incremented) */
 216                 if (cfg_width == CFGWDTH_32)
 217                         cd_ratio += 1;
 218         }
 219
 220         fpgamgr_set_cfgwdth(cfg_width);
 221         fpgamgr_set_cd_ratio(cd_ratio);
 222
 223         return 0;
 224 }
 225
 226 static int fpgamgr_reset(void)
 227 {
 228         unsigned long reg;
 229
 230         /* S2F_NCONFIG = 0 */
 231         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 232                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 233
 234         /* Wait for f2s_nstatus == 0 */
 235         if (wait_for_f2s_nstatus_pin(0))
 236                 return -ETIME;
 237
 238         /* S2F_NCONFIG = 1 */
 239         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 240                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 241
 242         /* Wait for f2s_nstatus == 1 */
 243         if (wait_for_f2s_nstatus_pin(1))
 244                 return -ETIME;
 245
 246         /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
 247         reg = readl(&fpga_manager_base->imgcfg_stat);
 248         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
 249                 return -EPERM;
 250
 251         if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
 252                 return -EPERM;
 253
 254         return 0;
 255 }
 256
 257 /* Start the FPGA programming by initialize the FPGA Manager */
 258 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
 259 {
 260         int ret;
 261
 262         /* Step 1 */
 263         if (fpgamgr_verify_msel())
 264                 return -EPERM;
 265
 266         /* Step 2 */
 267         if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
 268                 return -EPERM;
 269
 270         /*
 271          * Step 3:
 272          * Make sure no other external devices are trying to interfere with
 273          * programming:
 274          */
 275         if (wait_for_nconfig_pin_and_nstatus_pin())
 276                 return -ETIME;
 277
 278         /*
 279          * Step 4:
 280          * Deassert the signal drives from HPS
 281          *
 282          * S2F_NCE = 1
 283          * S2F_PR_REQUEST = 0
 284          * EN_CFG_CTRL = 0
 285          * EN_CFG_DATA = 0
 286          * S2F_NCONFIG = 1
 287          * S2F_NSTATUS_OE = 0
 288          * S2F_CONDONE_OE = 0
 289          */
 290         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 291                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 292
 293         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 294                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
 295
 296         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 297                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 298                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 299
 300         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 301                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
 302
 303         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 304                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
 305                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
 306
 307         /*
 308          * Step 5:
 309          * Enable overrides
 310          * S2F_NENABLE_CONFIG = 0
 311          * S2F_NENABLE_NCONFIG = 0
 312          */
 313         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 314                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 315         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 316                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 317
 318         /*
 319          * Disable driving signals that HPS doesn't need to drive.
 320          * S2F_NENABLE_NSTATUS = 1
 321          * S2F_NENABLE_CONDONE = 1
 322          */
 323         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 324                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
 325                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
 326
 327         /*
 328          * Step 6:
 329          * Drive chip select S2F_NCE = 0
 330          */
 331          clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 332                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 333
 334         /* Step 7 */
 335         if (wait_for_nconfig_pin_and_nstatus_pin())
 336                 return -ETIME;
 337
 338         /* Step 8 */
 339         ret = fpgamgr_reset();
 340
 341         if (ret)
 342                 return ret;
 343
 344         /*
 345          * Step 9:
 346          * EN_CFG_CTRL and EN_CFG_DATA = 1
 347          */
 348         setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 349                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 350                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 351
 352         return 0;
 353 }
 354
 355 /* Ensure the FPGA entering config done */
 356 static int fpgamgr_program_poll_cd(void)
 357 {
 358         unsigned long reg, i;
 359
 360         for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
 361                 reg = readl(&fpga_manager_base->imgcfg_stat);
 362                 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
 363                         return 0;
 364
 365                 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
 366                         printf("nstatus == 0 while waiting for condone\n");
 367                         return -EPERM;
 368                 }
 369                 WATCHDOG_RESET();
 370         }
 371
 372         if (i == FPGA_TIMEOUT_CNT)
 373                 return -ETIME;
 374
 375         return 0;
 376 }
 377
 378 /* Ensure the FPGA entering user mode */
 379 static int fpgamgr_program_poll_usermode(void)
 380 {
 381         unsigned long reg;
 382         int ret = 0;
 383
 384         if (fpgamgr_dclkcnt_set(0xf))
 385                 return -ETIME;
 386
 387         ret = wait_for_user_mode();
 388         if (ret < 0) {
 389                 printf("%s: Failed to enter user mode with ", __func__);
 390                 printf("error code %d\n", ret);
 391                 return ret;
 392         }
 393
 394         /*
 395          * Step 14:
 396          * Stop DATA path and Dclk
 397          * EN_CFG_CTRL and EN_CFG_DATA = 0
 398          */
 399         clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
 400                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
 401                 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
 402
 403         /*
 404          * Step 15:
 405          * Disable overrides
 406          * S2F_NENABLE_CONFIG = 1
 407          * S2F_NENABLE_NCONFIG = 1
 408          */
 409         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 410                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
 411         setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
 412                 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
 413
 414         /* Disable chip select S2F_NCE = 1 */
 415         setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
 416                 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
 417
 418         /*
 419          * Step 16:
 420          * Final check
 421          */
 422         reg = readl(&fpga_manager_base->imgcfg_stat);
 423         if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
 424                 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
 425             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
 426                 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
 427             ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
 428                 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
 429                 return -EPERM;
 430
 431         return 0;
 432 }
 433
 434 int fpgamgr_program_finish(void)
 435 {
 436         /* Ensure the FPGA entering config done */
 437         int status = fpgamgr_program_poll_cd();
 438
 439         if (status) {
 440                 printf("FPGA: Poll CD failed with error code %d\n", status);
 441                 return -EPERM;
 442         }
 443
 444         /* Ensure the FPGA entering user mode */
 445         status = fpgamgr_program_poll_usermode();
 446         if (status) {
 447                 printf("FPGA: Poll usermode failed with error code %d\n",
 448                         status);
 449                 return -EPERM;
 450         }
 451
 452         printf("Full Configuration Succeeded.\n");
 453
 454         return 0;
 455 }
 456
 457 ofnode get_fpga_mgr_ofnode(ofnode from)
 458 {
 459         return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
 460 }
 461
 462 const char *get_fpga_filename(void)
 463 {
 464         const char *fpga_filename = NULL;
 465
 466         ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
 467
 468         if (ofnode_valid(fpgamgr_node))
 469                 fpga_filename = ofnode_read_string(fpgamgr_node,
 470                                                 "altr,bitstream");
 471
 472         return fpga_filename;
 473 }
 474
 475 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
 476 {
 477         /*
 478          * Magic ID starting at:
 479          * -> 1st dword[15:0] in periph.rbf
 480          * -> 2nd dword[15:0] in core.rbf
 481          * Note: dword == 32 bits
 482          */
 483         u32 word_reading_max = 2;
 484         u32 i;
 485
 486         for (i = 0; i < word_reading_max; i++) {
 487                 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 488                         rbf->security = unencrypted;
 489                 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 490                         rbf->security = encrypted;
 491                 } else if (*(buffer + i + 1) ==
 492                                 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
 493                         rbf->security = unencrypted;
 494                 } else if (*(buffer + i + 1) ==
 495                                 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
 496                         rbf->security = encrypted;
 497                 } else {
 498                         rbf->security = invalid;
 499                         continue;
 500                 }
 501
 502                 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
 503                 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 504                         rbf->section = periph_section;
 505                         break;
 506                 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
 507                         rbf->section = core_section;
 508                         break;
 509                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
 510                         rbf->section = periph_section;
 511                         break;
 512                 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
 513                         rbf->section = core_section;
 514                         break;
 515                 }
 516
 517                 rbf->section = unknown;
 518                 break;
 519
 520                 WATCHDOG_RESET();
 521         }
 522 }
 523
 524 #ifdef CONFIG_FS_LOADER
 525 static int first_loading_rbf_to_buffer(struct udevice *dev,
 526                                 struct fpga_loadfs_info *fpga_loadfs,
 527                                 u32 *buffer, size_t *buffer_bsize)
 528 {
 529         u32 *buffer_p = (u32 *)*buffer;
 530         u32 *loadable = buffer_p;
 531         size_t buffer_size = *buffer_bsize;
 532         size_t fit_size;
 533         int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
 534         const char *fpga_node_name = NULL;
 535         const char *uname = NULL;
 536
 537         /* Load image header into buffer */
 538         ret = request_firmware_into_buf(dev,
 539                                         fpga_loadfs->fpga_fsinfo->filename,
 540                                         buffer_p, sizeof(struct image_header),
 541                                         0);
 542         if (ret < 0) {
 543                 debug("FPGA: Failed to read image header from flash.\n");
 544                 return -ENOENT;
 545         }
 546
 547         if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
 548                 debug("FPGA: No FDT magic was found.\n");
 549                 return -EBADF;
 550         }
 551
 552         fit_size = fdt_totalsize(buffer_p);
 553
 554         if (fit_size > buffer_size) {
 555                 debug("FPGA: FIT image is larger than available buffer.\n");
 556                 debug("Please use FIT external data or increasing buffer.\n");
 557                 return -ENOMEM;
 558         }
 559
 560         /* Load entire FIT into buffer */
 561         ret = request_firmware_into_buf(dev,
 562                                         fpga_loadfs->fpga_fsinfo->filename,
 563                                         buffer_p, fit_size, 0);
 564         if (ret < 0)
 565                 return ret;
 566
 567         ret = fit_check_format(buffer_p);
 568         if (!ret) {
 569                 debug("FPGA: No valid FIT image was found.\n");
 570                 return -EBADF;
 571         }
 572
 573         confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
 574         images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
 575         if (confs_noffset < 0 || images_noffset < 0) {
 576                 debug("FPGA: No Configurations or images nodes were found.\n");
 577                 return -ENOENT;
 578         }
 579
 580         /* Get default configuration unit name from default property */
 581         confs_noffset = fit_conf_get_node(buffer_p, NULL);
 582         if (confs_noffset < 0) {
 583                 debug("FPGA: No default configuration was found in config.\n");
 584                 return -ENOENT;
 585         }
 586
 587         count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
 588                                             FIT_FPGA_PROP);
 589         if (count < 0) {
 590                 debug("FPGA: Invalid configuration format for FPGA node.\n");
 591                 return count;
 592         }
 593         debug("FPGA: FPGA node count: %d\n", count);
 594
 595         for (i = 0; i < count; i++) {
 596                 images_noffset = fit_conf_get_prop_node_index(buffer_p,
 597                                                              confs_noffset,
 598                                                              FIT_FPGA_PROP, i);
 599                 uname = fit_get_name(buffer_p, images_noffset, NULL);
 600                 if (uname) {
 601                         debug("FPGA: %s\n", uname);
 602
 603                         if (strstr(uname, "fpga-periph") &&
 604                                 (!is_fpgamgr_early_user_mode() ||
 605                                 is_fpgamgr_user_mode())) {
 606                                 fpga_node_name = uname;
 607                                 printf("FPGA: Start to program ");
 608                                 printf("peripheral/full bitstream ...\n");
 609                                 break;
 610                         } else if (strstr(uname, "fpga-core") &&
 611                                         (is_fpgamgr_early_user_mode() &&
 612                                         !is_fpgamgr_user_mode())) {
 613                                 fpga_node_name = uname;
 614                                 printf("FPGA: Start to program core ");
 615                                 printf("bitstream ...\n");
 616                                 break;
 617                         }
 618                 }
 619                 WATCHDOG_RESET();
 620         }
 621
 622         if (!fpga_node_name) {
 623                 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
 624                 return 1;
 625         }
 626
 627         images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
 628         if (images_noffset < 0) {
 629                 debug("FPGA: No node '%s' was found in FIT.\n",
 630                      fpga_node_name);
 631                 return -ENOENT;
 632         }
 633
 634         if (!fit_image_get_data_position(buffer_p, images_noffset,
 635                                         &rbf_offset)) {
 636                 debug("FPGA: Data position was found.\n");
 637         } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
 638                   &rbf_offset)) {
 639                 /*
 640                  * For FIT with external data, figure out where
 641                  * the external images start. This is the base
 642                  * for the data-offset properties in each image.
 643                  */
 644                 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
 645                 debug("FPGA: Data offset was found.\n");
 646         } else {
 647                 debug("FPGA: No data position/offset was found.\n");
 648                 return -ENOENT;
 649         }
 650
 651         ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
 652         if (ret < 0) {
 653                 debug("FPGA: No data size was found (err=%d).\n", ret);
 654                 return -ENOENT;
 655         }
 656
 657         if (gd->ram_size < rbf_size) {
 658                 debug("FPGA: Using default OCRAM buffer and size.\n");
 659         } else {
 660                 ret = fit_image_get_load(buffer_p, images_noffset,
 661                                         (ulong *)loadable);
 662                 if (ret < 0) {
 663                         buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
 664                         debug("FPGA: No loadable was found.\n");
 665                         debug("FPGA: Using default DDR load address: 0x%x .\n",
 666                              DEFAULT_DDR_LOAD_ADDRESS);
 667                 } else {
 668                         buffer_p = (u32 *)*loadable;
 669                         debug("FPGA: Found loadable address = 0x%x.\n",
 670                              *loadable);
 671                 }
 672
 673                 buffer_size = rbf_size;
 674         }
 675
 676         debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
 677               rbf_offset, rbf_size);
 678
 679         fpga_loadfs->remaining = rbf_size;
 680
 681         /*
 682          * Determine buffer size vs bitstream size, and calculating number of
 683          * chunk by chunk transfer is required due to smaller buffer size
 684          * compare to bitstream
 685          */
 686         if (rbf_size <= buffer_size) {
 687                 /* Loading whole bitstream into buffer */
 688                 buffer_size = rbf_size;
 689                 fpga_loadfs->remaining = 0;
 690         } else {
 691                 fpga_loadfs->remaining -= buffer_size;
 692         }
 693
 694         fpga_loadfs->offset = rbf_offset;
 695         /* Loading bitstream into buffer */
 696         ret = request_firmware_into_buf(dev,
 697                                         fpga_loadfs->fpga_fsinfo->filename,
 698                                         buffer_p, buffer_size,
 699                                         fpga_loadfs->offset);
 700         if (ret < 0) {
 701                 debug("FPGA: Failed to read bitstream from flash.\n");
 702                 return -ENOENT;
 703         }
 704
 705         /* Getting info about bitstream types */
 706         get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
 707
 708         /* Update next reading bitstream offset */
 709         fpga_loadfs->offset += buffer_size;
 710
 711         /* Update the final addr for bitstream */
 712         *buffer = (u32)buffer_p;
 713
 714         /* Update the size of bitstream to be programmed into FPGA */
 715         *buffer_bsize = buffer_size;
 716
 717         return 0;
 718 }
 719
 720 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
 721                                         struct fpga_loadfs_info *fpga_loadfs,
 722                                         u32 *buffer, size_t *buffer_bsize)
 723 {
 724         int ret = 0;
 725         u32 *buffer_p = (u32 *)*buffer;
 726
 727         /* Read the bitstream chunk by chunk. */
 728         if (fpga_loadfs->remaining > *buffer_bsize) {
 729                 fpga_loadfs->remaining -= *buffer_bsize;
 730         } else {
 731                 *buffer_bsize = fpga_loadfs->remaining;
 732                 fpga_loadfs->remaining = 0;
 733         }
 734
 735         ret = request_firmware_into_buf(dev,
 736                                         fpga_loadfs->fpga_fsinfo->filename,
 737                                         buffer_p, *buffer_bsize,
 738                                         fpga_loadfs->offset);
 739         if (ret < 0) {
 740                 debug("FPGA: Failed to read bitstream from flash.\n");
 741                 return -ENOENT;
 742         }
 743
 744         /* Update next reading bitstream offset */
 745         fpga_loadfs->offset += *buffer_bsize;
 746
 747         return 0;
 748 }
 749
 750 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 751                         u32 offset)
 752 {
 753         struct fpga_loadfs_info fpga_loadfs;
 754         struct udevice *dev;
 755         int status, ret, size;
 756         u32 buffer = (uintptr_t)buf;
 757         size_t buffer_sizebytes = bsize;
 758         size_t buffer_sizebytes_ori = bsize;
 759         size_t total_sizeof_image = 0;
 760         ofnode node;
 761         const fdt32_t *phandle_p;
 762         u32 phandle;
 763
 764         node = get_fpga_mgr_ofnode(ofnode_null());
 765
 766         if (ofnode_valid(node)) {
 767                 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
 768                 if (!phandle_p) {
 769                         node = ofnode_path("/chosen");
 770                         if (!ofnode_valid(node)) {
 771                                 debug("FPGA: /chosen node was not found.\n");
 772                                 return -ENOENT;
 773                         }
 774
 775                         phandle_p = ofnode_get_property(node, "firmware-loader",
 776                                                        &size);
 777                         if (!phandle_p) {
 778                                 debug("FPGA: firmware-loader property was not");
 779                                 debug(" found.\n");
 780                                 return -ENOENT;
 781                         }
 782                 }
 783         } else {
 784                 debug("FPGA: FPGA manager node was not found.\n");
 785                 return -ENOENT;
 786         }
 787
 788         phandle = fdt32_to_cpu(*phandle_p);
 789         ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
 790                                              phandle, &dev);
 791         if (ret)
 792                 return ret;
 793
 794         memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
 795
 796         fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
 797         fpga_loadfs.offset = offset;
 798
 799         printf("FPGA: Checking FPGA configuration setting ...\n");
 800
 801         /*
 802          * Note: Both buffer and buffer_sizebytes values can be altered by
 803          * function below.
 804          */
 805         ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
 806                                            &buffer_sizebytes);
 807         if (ret == 1) {
 808                 printf("FPGA: Skipping configuration ...\n");
 809                 return 0;
 810         } else if (ret) {
 811                 return ret;
 812         }
 813
 814         if (fpga_loadfs.rbfinfo.section == core_section &&
 815                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 816                 debug("FPGA : Must be in Early Release mode to program ");
 817                 debug("core bitstream.\n");
 818                 return -EPERM;
 819         }
 820
 821         /* Disable all signals from HPS peripheral controller to FPGA */
 822         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 823
 824         /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 825         socfpga_bridges_reset();
 826
 827         if (fpga_loadfs.rbfinfo.section == periph_section) {
 828                 /* Initialize the FPGA Manager */
 829                 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
 830                 if (status) {
 831                         debug("FPGA: Init with peripheral bitstream failed.\n");
 832                         return -EPERM;
 833                 }
 834         }
 835
 836         /* Transfer bitstream to FPGA Manager */
 837         fpgamgr_program_write((void *)buffer, buffer_sizebytes);
 838
 839         total_sizeof_image += buffer_sizebytes;
 840
 841         while (fpga_loadfs.remaining) {
 842                 ret = subsequent_loading_rbf_to_buffer(dev,
 843                                                         &fpga_loadfs,
 844                                                         &buffer,
 845                                                         &buffer_sizebytes_ori);
 846
 847                 if (ret)
 848                         return ret;
 849
 850                 /* Transfer data to FPGA Manager */
 851                 fpgamgr_program_write((void *)buffer,
 852                                         buffer_sizebytes_ori);
 853
 854                 total_sizeof_image += buffer_sizebytes_ori;
 855
 856                 WATCHDOG_RESET();
 857         }
 858
 859         if (fpga_loadfs.rbfinfo.section == periph_section) {
 860                 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
 861                         config_pins(gd->fdt_blob, "shared");
 862                         puts("FPGA: Early Release Succeeded.\n");
 863                 } else {
 864                         debug("FPGA: Failed to see Early Release.\n");
 865                         return -EIO;
 866                 }
 867
 868                 /* For monolithic bitstream */
 869                 if (is_fpgamgr_user_mode()) {
 870                         /* Ensure the FPGA entering config done */
 871                         status = fpgamgr_program_finish();
 872                         if (status)
 873                                 return status;
 874
 875                         config_pins(gd->fdt_blob, "fpga");
 876                         puts("FPGA: Enter user mode.\n");
 877                 }
 878         } else if (fpga_loadfs.rbfinfo.section == core_section) {
 879                 /* Ensure the FPGA entering config done */
 880                 status = fpgamgr_program_finish();
 881                 if (status)
 882                         return status;
 883
 884                 config_pins(gd->fdt_blob, "fpga");
 885                 puts("FPGA: Enter user mode.\n");
 886         } else {
 887                 debug("FPGA: Config Error: Unsupported bitstream type.\n");
 888                 return -ENOEXEC;
 889         }
 890
 891         return (int)total_sizeof_image;
 892 }
 893
 894 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
 895 {
 896         fpga_fs_info fpga_fsinfo;
 897
 898         fpga_fsinfo.filename = get_fpga_filename();
 899
 900         if (fpga_fsinfo.filename)
 901                 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
 902 }
 903 #endif
 904
 905 /* This function is used to load the core bitstream from the OCRAM. */
 906 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 907 {
 908         unsigned long status;
 909         struct rbf_info rbfinfo;
 910
 911         memset(&rbfinfo, 0, sizeof(rbfinfo));
 912
 913         /* Disable all signals from hps peripheral controller to fpga */
 914         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 915
 916         /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 917         socfpga_bridges_reset();
 918
 919         /* Getting info about bitstream types */
 920         get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
 921
 922         if (rbfinfo.section == periph_section) {
 923                 /* Initialize the FPGA Manager */
 924                 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
 925                 if (status)
 926                         return status;
 927         }
 928
 929         if (rbfinfo.section == core_section &&
 930                 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
 931                 debug("FPGA : Must be in early release mode to program ");
 932                 debug("core bitstream.\n");
 933                 return -EPERM;
 934         }
 935
 936         /* Write the bitstream to FPGA Manager */
 937         fpgamgr_program_write(rbf_data, rbf_size);
 938
 939         status = fpgamgr_program_finish();
 940         if (status)
 941                 return status;
 942
 943         config_pins(gd->fdt_blob, "fpga");
 944         puts("FPGA: Enter user mode.\n");
 945
 946         return status;
 947 }