1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
6 #include <asm/arch/fpga_manager.h>
7 #include <asm/arch/reset_manager.h>
8 #include <asm/arch/system_manager.h>
9 #include <asm/arch/sdram.h>
10 #include <asm/arch/misc.h>
12 #include <asm/arch/pinmux.h>
14 #include <dm/ofnode.h>
16 #include <fs_loader.h>
21 #define MIN_BITSTREAM_SIZECHECK 230
22 #define ENCRYPTION_OFFSET 69
23 #define COMPRESSION_OFFSET 229
24 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
25 #define FPGA_TIMEOUT_CNT 0x1000000
26 #define DEFAULT_DDR_LOAD_ADDRESS 0x400
28 DECLARE_GLOBAL_DATA_PTR;
30 static const struct socfpga_fpga_manager *fpga_manager_base =
31 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
33 static void fpgamgr_set_cd_ratio(unsigned long ratio);
35 static uint32_t fpgamgr_get_msel(void)
39 reg = readl(&fpga_manager_base->imgcfg_stat);
40 reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
41 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
46 static void fpgamgr_set_cfgwdth(int width)
49 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
50 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
52 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
53 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
56 int is_fpgamgr_user_mode(void)
58 return (readl(&fpga_manager_base->imgcfg_stat) &
59 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
62 static int wait_for_user_mode(void)
64 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
65 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
66 1, FPGA_TIMEOUT_MSEC, false);
69 int is_fpgamgr_early_user_mode(void)
71 return (readl(&fpga_manager_base->imgcfg_stat) &
72 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
75 int fpgamgr_wait_early_user_mode(void)
77 u32 sync_data = 0xffffffff;
79 unsigned start = get_timer(0);
80 unsigned long cd_ratio;
82 /* Getting existing CDRATIO */
83 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
84 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
85 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
87 /* Using CDRATIO_X1 for better compatibility */
88 fpgamgr_set_cd_ratio(CDRATIO_x1);
90 while (!is_fpgamgr_early_user_mode()) {
91 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
93 fpgamgr_program_write((const long unsigned int *)&sync_data,
95 udelay(FPGA_TIMEOUT_MSEC);
99 debug("FPGA: Additional %i sync word needed\n", i);
101 /* restoring original CDRATIO */
102 fpgamgr_set_cd_ratio(cd_ratio);
107 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
108 static int wait_for_nconfig_pin_and_nstatus_pin(void)
110 unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
111 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
114 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
115 * de-asserted, timeout at 1000ms
117 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
118 true, FPGA_TIMEOUT_MSEC, false);
121 static int wait_for_f2s_nstatus_pin(unsigned long value)
123 /* Poll until f2s to specific value, timeout at 1000ms */
124 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
125 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
126 value, FPGA_TIMEOUT_MSEC, false);
130 static void fpgamgr_set_cd_ratio(unsigned long ratio)
132 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
133 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
135 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
136 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
137 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
140 /* get the MSEL value, verify we are set for FPP configuration mode */
141 static int fpgamgr_verify_msel(void)
143 u32 msel = fpgamgr_get_msel();
145 if (msel & ~BIT(0)) {
146 printf("Fail: read msel=%d\n", msel);
154 * Write cdratio and cdwidth based on whether the bitstream is compressed
157 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
160 unsigned int cd_ratio;
161 bool encrypt, compress;
164 * According to the bitstream specification,
165 * both encryption and compression status are
166 * in location before offset 230 of the buffer.
168 if (rbf_size < MIN_BITSTREAM_SIZECHECK)
171 encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
172 encrypt = encrypt != 0;
174 compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
175 compress = !compress;
177 debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
178 debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
179 debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
183 * from the register map description of cdratio in imgcfg_ctrl_02:
184 * Normal Configuration : 32bit Passive Parallel
185 * Partial Reconfiguration : 16bit Passive Parallel
189 * cd ratio is dependent on cfg width and whether the bitstream
190 * is encrypted and/or compressed.
192 * | width | encr. | compr. | cd ratio |
202 if (!compress && !encrypt) {
203 cd_ratio = CDRATIO_x1;
206 cd_ratio = CDRATIO_x4;
208 cd_ratio = CDRATIO_x2;
210 /* if 32 bit, double the cd ratio (so register
211 field setting is incremented) */
212 if (cfg_width == CFGWDTH_32)
216 fpgamgr_set_cfgwdth(cfg_width);
217 fpgamgr_set_cd_ratio(cd_ratio);
222 static int fpgamgr_reset(void)
226 /* S2F_NCONFIG = 0 */
227 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
228 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
230 /* Wait for f2s_nstatus == 0 */
231 if (wait_for_f2s_nstatus_pin(0))
234 /* S2F_NCONFIG = 1 */
235 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
236 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
238 /* Wait for f2s_nstatus == 1 */
239 if (wait_for_f2s_nstatus_pin(1))
242 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
243 reg = readl(&fpga_manager_base->imgcfg_stat);
244 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
247 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
253 /* Start the FPGA programming by initialize the FPGA Manager */
254 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
259 if (fpgamgr_verify_msel())
263 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
268 * Make sure no other external devices are trying to interfere with
271 if (wait_for_nconfig_pin_and_nstatus_pin())
276 * Deassert the signal drives from HPS
286 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
287 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
289 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
290 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
292 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
293 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
294 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
296 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
297 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
299 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
300 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
301 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
306 * S2F_NENABLE_CONFIG = 0
307 * S2F_NENABLE_NCONFIG = 0
309 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
310 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
311 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
312 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
315 * Disable driving signals that HPS doesn't need to drive.
316 * S2F_NENABLE_NSTATUS = 1
317 * S2F_NENABLE_CONDONE = 1
319 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
320 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
321 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
325 * Drive chip select S2F_NCE = 0
327 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
328 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
331 if (wait_for_nconfig_pin_and_nstatus_pin())
335 ret = fpgamgr_reset();
342 * EN_CFG_CTRL and EN_CFG_DATA = 1
344 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
345 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
346 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
351 /* Ensure the FPGA entering config done */
352 static int fpgamgr_program_poll_cd(void)
354 unsigned long reg, i;
356 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
357 reg = readl(&fpga_manager_base->imgcfg_stat);
358 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
361 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
362 printf("nstatus == 0 while waiting for condone\n");
368 if (i == FPGA_TIMEOUT_CNT)
374 /* Ensure the FPGA entering user mode */
375 static int fpgamgr_program_poll_usermode(void)
380 if (fpgamgr_dclkcnt_set(0xf))
383 ret = wait_for_user_mode();
385 printf("%s: Failed to enter user mode with ", __func__);
386 printf("error code %d\n", ret);
392 * Stop DATA path and Dclk
393 * EN_CFG_CTRL and EN_CFG_DATA = 0
395 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
396 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
397 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
402 * S2F_NENABLE_CONFIG = 1
403 * S2F_NENABLE_NCONFIG = 1
405 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
406 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
407 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
408 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
410 /* Disable chip select S2F_NCE = 1 */
411 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
412 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
418 reg = readl(&fpga_manager_base->imgcfg_stat);
419 if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
420 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
421 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
422 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
423 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
424 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
430 int fpgamgr_program_finish(void)
432 /* Ensure the FPGA entering config done */
433 int status = fpgamgr_program_poll_cd();
436 printf("FPGA: Poll CD failed with error code %d\n", status);
440 /* Ensure the FPGA entering user mode */
441 status = fpgamgr_program_poll_usermode();
443 printf("FPGA: Poll usermode failed with error code %d\n",
448 printf("Full Configuration Succeeded.\n");
453 ofnode get_fpga_mgr_ofnode(ofnode from)
455 return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
458 const char *get_fpga_filename(void)
460 const char *fpga_filename = NULL;
462 ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
464 if (ofnode_valid(fpgamgr_node))
465 fpga_filename = ofnode_read_string(fpgamgr_node,
468 return fpga_filename;
471 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
474 * Magic ID starting at:
475 * -> 1st dword[15:0] in periph.rbf
476 * -> 2nd dword[15:0] in core.rbf
477 * Note: dword == 32 bits
479 u32 word_reading_max = 2;
482 for (i = 0; i < word_reading_max; i++) {
483 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
484 rbf->security = unencrypted;
485 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
486 rbf->security = encrypted;
487 } else if (*(buffer + i + 1) ==
488 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
489 rbf->security = unencrypted;
490 } else if (*(buffer + i + 1) ==
491 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
492 rbf->security = encrypted;
494 rbf->security = invalid;
498 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
499 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
500 rbf->section = periph_section;
502 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
503 rbf->section = core_section;
505 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
506 rbf->section = periph_section;
508 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
509 rbf->section = core_section;
513 rbf->section = unknown;
520 #ifdef CONFIG_FS_LOADER
521 static int first_loading_rbf_to_buffer(struct udevice *dev,
522 struct fpga_loadfs_info *fpga_loadfs,
523 u32 *buffer, size_t *buffer_bsize)
525 u32 *buffer_p = (u32 *)*buffer;
526 u32 *loadable = buffer_p;
527 size_t buffer_size = *buffer_bsize;
529 int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
530 const char *fpga_node_name = NULL;
531 const char *uname = NULL;
533 /* Load image header into buffer */
534 ret = request_firmware_into_buf(dev,
535 fpga_loadfs->fpga_fsinfo->filename,
536 buffer_p, sizeof(struct image_header),
539 debug("FPGA: Failed to read image header from flash.\n");
543 if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
544 debug("FPGA: No FDT magic was found.\n");
548 fit_size = fdt_totalsize(buffer_p);
550 if (fit_size > buffer_size) {
551 debug("FPGA: FIT image is larger than available buffer.\n");
552 debug("Please use FIT external data or increasing buffer.\n");
556 /* Load entire FIT into buffer */
557 ret = request_firmware_into_buf(dev,
558 fpga_loadfs->fpga_fsinfo->filename,
559 buffer_p, fit_size, 0);
563 ret = fit_check_format(buffer_p);
565 debug("FPGA: No valid FIT image was found.\n");
569 confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
570 images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
571 if (confs_noffset < 0 || images_noffset < 0) {
572 debug("FPGA: No Configurations or images nodes were found.\n");
576 /* Get default configuration unit name from default property */
577 confs_noffset = fit_conf_get_node(buffer_p, NULL);
578 if (confs_noffset < 0) {
579 debug("FPGA: No default configuration was found in config.\n");
583 count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
586 debug("FPGA: Invalid configuration format for FPGA node.\n");
589 debug("FPGA: FPGA node count: %d\n", count);
591 for (i = 0; i < count; i++) {
592 images_noffset = fit_conf_get_prop_node_index(buffer_p,
595 uname = fit_get_name(buffer_p, images_noffset, NULL);
597 debug("FPGA: %s\n", uname);
599 if (strstr(uname, "fpga-periph") &&
600 (!is_fpgamgr_early_user_mode() ||
601 is_fpgamgr_user_mode())) {
602 fpga_node_name = uname;
603 printf("FPGA: Start to program ");
604 printf("peripheral/full bitstream ...\n");
606 } else if (strstr(uname, "fpga-core") &&
607 (is_fpgamgr_early_user_mode() &&
608 !is_fpgamgr_user_mode())) {
609 fpga_node_name = uname;
610 printf("FPGA: Start to program core ");
611 printf("bitstream ...\n");
618 if (!fpga_node_name) {
619 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
623 images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
624 if (images_noffset < 0) {
625 debug("FPGA: No node '%s' was found in FIT.\n",
630 if (!fit_image_get_data_position(buffer_p, images_noffset,
632 debug("FPGA: Data position was found.\n");
633 } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
636 * For FIT with external data, figure out where
637 * the external images start. This is the base
638 * for the data-offset properties in each image.
640 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
641 debug("FPGA: Data offset was found.\n");
643 debug("FPGA: No data position/offset was found.\n");
647 ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
649 debug("FPGA: No data size was found (err=%d).\n", ret);
653 if (gd->ram_size < rbf_size) {
654 debug("FPGA: Using default OCRAM buffer and size.\n");
656 ret = fit_image_get_load(buffer_p, images_noffset,
659 buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
660 debug("FPGA: No loadable was found.\n");
661 debug("FPGA: Using default DDR load address: 0x%x .\n",
662 DEFAULT_DDR_LOAD_ADDRESS);
664 buffer_p = (u32 *)*loadable;
665 debug("FPGA: Found loadable address = 0x%x.\n",
669 buffer_size = rbf_size;
672 debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
673 rbf_offset, rbf_size);
675 fpga_loadfs->remaining = rbf_size;
678 * Determine buffer size vs bitstream size, and calculating number of
679 * chunk by chunk transfer is required due to smaller buffer size
680 * compare to bitstream
682 if (rbf_size <= buffer_size) {
683 /* Loading whole bitstream into buffer */
684 buffer_size = rbf_size;
685 fpga_loadfs->remaining = 0;
687 fpga_loadfs->remaining -= buffer_size;
690 fpga_loadfs->offset = rbf_offset;
691 /* Loading bitstream into buffer */
692 ret = request_firmware_into_buf(dev,
693 fpga_loadfs->fpga_fsinfo->filename,
694 buffer_p, buffer_size,
695 fpga_loadfs->offset);
697 debug("FPGA: Failed to read bitstream from flash.\n");
701 /* Getting info about bitstream types */
702 get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
704 /* Update next reading bitstream offset */
705 fpga_loadfs->offset += buffer_size;
707 /* Update the final addr for bitstream */
708 *buffer = (u32)buffer_p;
710 /* Update the size of bitstream to be programmed into FPGA */
711 *buffer_bsize = buffer_size;
716 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
717 struct fpga_loadfs_info *fpga_loadfs,
718 u32 *buffer, size_t *buffer_bsize)
721 u32 *buffer_p = (u32 *)*buffer;
723 /* Read the bitstream chunk by chunk. */
724 if (fpga_loadfs->remaining > *buffer_bsize) {
725 fpga_loadfs->remaining -= *buffer_bsize;
727 *buffer_bsize = fpga_loadfs->remaining;
728 fpga_loadfs->remaining = 0;
731 ret = request_firmware_into_buf(dev,
732 fpga_loadfs->fpga_fsinfo->filename,
733 buffer_p, *buffer_bsize,
734 fpga_loadfs->offset);
736 debug("FPGA: Failed to read bitstream from flash.\n");
740 /* Update next reading bitstream offset */
741 fpga_loadfs->offset += *buffer_bsize;
746 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
749 struct fpga_loadfs_info fpga_loadfs;
751 int status, ret, size;
752 u32 buffer = (uintptr_t)buf;
753 size_t buffer_sizebytes = bsize;
754 size_t buffer_sizebytes_ori = bsize;
755 size_t total_sizeof_image = 0;
757 const fdt32_t *phandle_p;
760 node = get_fpga_mgr_ofnode(ofnode_null());
762 if (ofnode_valid(node)) {
763 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
765 node = ofnode_path("/chosen");
766 if (!ofnode_valid(node)) {
767 debug("FPGA: /chosen node was not found.\n");
771 phandle_p = ofnode_get_property(node, "firmware-loader",
774 debug("FPGA: firmware-loader property was not");
780 debug("FPGA: FPGA manager node was not found.\n");
784 phandle = fdt32_to_cpu(*phandle_p);
785 ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
790 memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
792 fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
793 fpga_loadfs.offset = offset;
795 printf("FPGA: Checking FPGA configuration setting ...\n");
798 * Note: Both buffer and buffer_sizebytes values can be altered by
801 ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
804 printf("FPGA: Skipping configuration ...\n");
810 if (fpga_loadfs.rbfinfo.section == core_section &&
811 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
812 debug("FPGA : Must be in Early Release mode to program ");
813 debug("core bitstream.\n");
817 /* Disable all signals from HPS peripheral controller to FPGA */
818 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
820 /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
821 socfpga_bridges_reset();
823 if (fpga_loadfs.rbfinfo.section == periph_section) {
824 /* Initialize the FPGA Manager */
825 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
827 debug("FPGA: Init with peripheral bitstream failed.\n");
832 /* Transfer bitstream to FPGA Manager */
833 fpgamgr_program_write((void *)buffer, buffer_sizebytes);
835 total_sizeof_image += buffer_sizebytes;
837 while (fpga_loadfs.remaining) {
838 ret = subsequent_loading_rbf_to_buffer(dev,
841 &buffer_sizebytes_ori);
846 /* Transfer data to FPGA Manager */
847 fpgamgr_program_write((void *)buffer,
848 buffer_sizebytes_ori);
850 total_sizeof_image += buffer_sizebytes_ori;
855 if (fpga_loadfs.rbfinfo.section == periph_section) {
856 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
857 config_pins(gd->fdt_blob, "shared");
858 puts("FPGA: Early Release Succeeded.\n");
860 debug("FPGA: Failed to see Early Release.\n");
864 /* For monolithic bitstream */
865 if (is_fpgamgr_user_mode()) {
866 /* Ensure the FPGA entering config done */
867 status = fpgamgr_program_finish();
871 config_pins(gd->fdt_blob, "fpga");
872 puts("FPGA: Enter user mode.\n");
874 } else if (fpga_loadfs.rbfinfo.section == core_section) {
875 /* Ensure the FPGA entering config done */
876 status = fpgamgr_program_finish();
880 config_pins(gd->fdt_blob, "fpga");
881 puts("FPGA: Enter user mode.\n");
883 debug("FPGA: Config Error: Unsupported bitstream type.\n");
887 return (int)total_sizeof_image;
890 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
892 fpga_fs_info fpga_fsinfo;
894 fpga_fsinfo.filename = get_fpga_filename();
896 if (fpga_fsinfo.filename)
897 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
901 /* This function is used to load the core bitstream from the OCRAM. */
902 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
904 unsigned long status;
905 struct rbf_info rbfinfo;
907 memset(&rbfinfo, 0, sizeof(rbfinfo));
909 /* Disable all signals from hps peripheral controller to fpga */
910 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
912 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
913 socfpga_bridges_reset();
915 /* Getting info about bitstream types */
916 get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
918 if (rbfinfo.section == periph_section) {
919 /* Initialize the FPGA Manager */
920 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
925 if (rbfinfo.section == core_section &&
926 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
927 debug("FPGA : Must be in early release mode to program ");
928 debug("core bitstream.\n");
932 /* Write the bitstream to FPGA Manager */
933 fpgamgr_program_write(rbf_data, rbf_size);
935 status = fpgamgr_program_finish();
939 config_pins(gd->fdt_blob, "fpga");
940 puts("FPGA: Enter user mode.\n");