1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Texas Instruments System Control Interface (TISCI) Protocol
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
10 * Based on drivers/firmware/ti_sci.h from Linux.
17 /* Generic Messages */
18 #define TI_SCI_MSG_ENABLE_WDT 0x0000
19 #define TI_SCI_MSG_WAKE_RESET 0x0001
20 #define TI_SCI_MSG_VERSION 0x0002
21 #define TI_SCI_MSG_WAKE_REASON 0x0003
22 #define TI_SCI_MSG_GOODBYE 0x0004
23 #define TI_SCI_MSG_SYS_RESET 0x0005
24 #define TI_SCI_MSG_BOARD_CONFIG 0x000b
25 #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c
26 #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d
27 #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e
28 #define TISCI_MSG_QUERY_MSMC 0x0020
31 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
32 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
33 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
36 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
37 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
38 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
39 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
40 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
41 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
42 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
43 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
45 /* Processor Control Messages */
46 #define TISCI_MSG_PROC_REQUEST 0xc000
47 #define TISCI_MSG_PROC_RELEASE 0xc001
48 #define TISCI_MSG_PROC_HANDOVER 0xc005
49 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
50 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
51 #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
52 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
53 #define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
55 /* Resource Management Requests */
56 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
58 /* NAVSS resource management */
59 /* Ringacc requests */
60 #define TI_SCI_MSG_RM_RING_CFG 0x1110
63 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
64 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
66 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
67 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
68 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
69 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
70 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
71 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
73 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
74 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
75 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
76 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
78 #define TISCI_MSG_FWL_SET 0x9000
79 #define TISCI_MSG_FWL_GET 0x9001
80 #define TISCI_MSG_FWL_CHANGE_OWNER 0x9002
83 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
84 * @type: Type of messages: One of TI_SCI_MSG* values
85 * @host: Host of the message
86 * @seq: Message identifier indicating a transfer sequence
87 * @flags: Flag for the message
89 struct ti_sci_msg_hdr {
93 #define TI_SCI_MSG_FLAG(val) (1 << (val))
94 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
95 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
96 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
97 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
98 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
99 /* Additional Flags */
104 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
105 * via secure transport.
106 * @checksum: crc16 checksum for the entire message
107 * @reserved: Reserved for future use.
109 struct ti_sci_secure_msg_hdr {
115 * struct ti_sci_msg_resp_version - Response for a message
116 * @hdr: Generic header
117 * @firmware_description: String describing the firmware
118 * @firmware_revision: Firmware revision
119 * @abi_major: Major version of the ABI that firmware supports
120 * @abi_minor: Minor version of the ABI that firmware supports
122 * In general, ABI version changes follow the rule that minor version increments
123 * are backward compatible. Major revision changes in ABI may not be
124 * backward compatible.
126 * Response to a generic message with message type TI_SCI_MSG_VERSION
128 struct ti_sci_msg_resp_version {
129 struct ti_sci_msg_hdr hdr;
130 char firmware_description[32];
131 u16 firmware_revision;
137 * struct ti_sci_msg_req_reboot - Reboot the SoC
138 * @hdr: Generic Header
140 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
143 struct ti_sci_msg_req_reboot {
144 struct ti_sci_msg_hdr hdr;
148 * struct ti_sci_msg_board_config - Board configuration message
149 * @hdr: Generic Header
150 * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board
152 * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board
154 * @boardcfg_size: Size of board configuration data object
155 * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic
158 struct ti_sci_msg_board_config {
159 struct ti_sci_msg_hdr hdr;
166 * struct ti_sci_msg_resp_query_msmc - Query msmc message response structure
167 * @hdr: Generic Header
168 * @msmc_start_low: Lower 32 bit of msmc start
169 * @msmc_start_high: Upper 32 bit of msmc start
170 * @msmc_end_low: Lower 32 bit of msmc end
171 * @msmc_end_high: Upper 32 bit of msmc end
173 * Response to a generic message with message type TISCI_MSG_QUERY_MSMC
175 struct ti_sci_msg_resp_query_msmc {
176 struct ti_sci_msg_hdr hdr;
184 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
185 * @hdr: Generic header
186 * @id: Indicates which device to modify
187 * @reserved: Reserved space in message, must be 0 for backward compatibility
188 * @state: The desired state of the device.
190 * Certain flags can also be set to alter the device state:
191 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
192 * The meaning of this flag will vary slightly from device to device and from
193 * SoC to SoC but it generally allows the device to wake the SoC out of deep
195 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
196 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
197 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
198 * If another host already has this device set to STATE_RETENTION or STATE_ON,
199 * the message will fail. Once successful, other hosts attempting to set
200 * STATE_RETENTION or STATE_ON will fail.
202 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
205 struct ti_sci_msg_req_set_device_state {
206 /* Additional hdr->flags options */
207 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
208 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
209 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
210 struct ti_sci_msg_hdr hdr;
214 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
215 #define MSG_DEVICE_SW_STATE_RETENTION 1
216 #define MSG_DEVICE_SW_STATE_ON 2
221 * struct ti_sci_msg_req_get_device_state - Request to get device.
222 * @hdr: Generic header
223 * @id: Device Identifier
225 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
228 struct ti_sci_msg_req_get_device_state {
229 struct ti_sci_msg_hdr hdr;
234 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
235 * @hdr: Generic header
236 * @context_loss_count: Indicates how many times the device has lost context. A
237 * driver can use this monotonic counter to determine if the device has
238 * lost context since the last time this message was exchanged.
239 * @resets: Programmed state of the reset lines.
240 * @programmed_state: The state as programmed by set_device.
241 * - Uses the MSG_DEVICE_SW_* macros
242 * @current_state: The actual state of the hardware.
244 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
246 struct ti_sci_msg_resp_get_device_state {
247 struct ti_sci_msg_hdr hdr;
248 u32 context_loss_count;
251 #define MSG_DEVICE_HW_STATE_OFF 0
252 #define MSG_DEVICE_HW_STATE_ON 1
253 #define MSG_DEVICE_HW_STATE_TRANS 2
258 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
259 * configuration of the device
260 * @hdr: Generic header
261 * @id: Indicates which device to modify
262 * @resets: A bit field of resets for the device. The meaning, behavior,
263 * and usage of the reset flags are device specific. 0 for a bit
264 * indicates releasing the reset represented by that bit while 1
265 * indicates keeping it held.
267 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
270 struct ti_sci_msg_req_set_device_resets {
271 struct ti_sci_msg_hdr hdr;
277 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
278 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
279 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
280 * via spread spectrum clocking.
281 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
282 * frequency to be changed while it is running so long as it
283 * is within the min/max limits.
284 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
285 * is only applicable to clock inputs on the SoC pseudo-device.
286 * @dev_id: Device identifier this request is for
287 * @clk_id: Clock identifier for the device for this request.
288 * Each device has it's own set of clock inputs. This indexes
289 * which clock input to modify.
290 * @request_state: Request the state for the clock to be set to.
291 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
292 * it can be disabled, regardless of the state of the device
293 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
294 * automatically manage the state of this clock. If the device
295 * is enabled, then the clock is enabled. If the device is set
296 * to off or retention, then the clock is internally set as not
297 * being required by the device.(default)
298 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
299 * regardless of the state of the device.
301 * Normally, all required clocks are managed by TISCI entity, this is used
302 * only for specific control *IF* required. Auto managed state is
303 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
304 * will explicitly control.
306 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
307 * ACK or NACK message.
309 struct ti_sci_msg_req_set_clock_state {
310 /* Additional hdr->flags options */
311 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
312 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
313 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
314 struct ti_sci_msg_hdr hdr;
317 #define MSG_CLOCK_SW_STATE_UNREQ 0
318 #define MSG_CLOCK_SW_STATE_AUTO 1
319 #define MSG_CLOCK_SW_STATE_REQ 2
324 * struct ti_sci_msg_req_get_clock_state - Request for clock state
325 * @hdr: Generic Header
326 * @dev_id: Device identifier this request is for
327 * @clk_id: Clock identifier for the device for this request.
328 * Each device has it's own set of clock inputs. This indexes
329 * which clock input to get state of.
331 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
334 struct ti_sci_msg_req_get_clock_state {
335 struct ti_sci_msg_hdr hdr;
341 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
342 * @hdr: Generic Header
343 * @programmed_state: Any programmed state of the clock. This is one of
344 * MSG_CLOCK_SW_STATE* values.
345 * @current_state: Current state of the clock. This is one of:
346 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
347 * MSG_CLOCK_HW_STATE_READY: Clock is ready
349 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
351 struct ti_sci_msg_resp_get_clock_state {
352 struct ti_sci_msg_hdr hdr;
354 #define MSG_CLOCK_HW_STATE_NOT_READY 0
355 #define MSG_CLOCK_HW_STATE_READY 1
360 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
361 * @hdr: Generic Header
362 * @dev_id: Device identifier this request is for
363 * @clk_id: Clock identifier for the device for this request.
364 * Each device has it's own set of clock inputs. This indexes
365 * which clock input to modify.
366 * @parent_id: The new clock parent is selectable by an index via this
369 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
370 * ACK / NACK message.
372 struct ti_sci_msg_req_set_clock_parent {
373 struct ti_sci_msg_hdr hdr;
380 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
381 * @hdr: Generic Header
382 * @dev_id: Device identifier this request is for
383 * @clk_id: Clock identifier for the device for this request.
384 * Each device has it's own set of clock inputs. This indexes
385 * which clock input to get the parent for.
387 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
389 struct ti_sci_msg_req_get_clock_parent {
390 struct ti_sci_msg_hdr hdr;
396 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
397 * @hdr: Generic Header
398 * @parent_id: The current clock parent
400 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
402 struct ti_sci_msg_resp_get_clock_parent {
403 struct ti_sci_msg_hdr hdr;
408 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
409 * @hdr: Generic header
410 * @dev_id: Device identifier this request is for
411 * @clk_id: Clock identifier for the device for this request.
413 * This request provides information about how many clock parent options
414 * are available for a given clock to a device. This is typically used
417 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
418 * message, or NACK in case of inability to satisfy request.
420 struct ti_sci_msg_req_get_clock_num_parents {
421 struct ti_sci_msg_hdr hdr;
427 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
428 * @hdr: Generic header
429 * @num_parents: Number of clock parents
431 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
433 struct ti_sci_msg_resp_get_clock_num_parents {
434 struct ti_sci_msg_hdr hdr;
439 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
440 * @hdr: Generic Header
441 * @dev_id: Device identifier this request is for
442 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
443 * allowable programmed frequency and does not account for clock
444 * tolerances and jitter.
445 * @target_freq_hz: The target clock frequency. A frequency will be found
446 * as close to this target frequency as possible.
447 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
448 * allowable programmed frequency and does not account for clock
449 * tolerances and jitter.
450 * @clk_id: Clock identifier for the device for this request.
452 * NOTE: Normally clock frequency management is automatically done by TISCI
453 * entity. In case of specific requests, TISCI evaluates capability to achieve
454 * requested frequency within provided range and responds with
457 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
458 * or NACK in case of inability to satisfy request.
460 struct ti_sci_msg_req_query_clock_freq {
461 struct ti_sci_msg_hdr hdr;
470 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
471 * @hdr: Generic Header
472 * @freq_hz: Frequency that is the best match in Hz.
474 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
475 * cannot be satisfied, the message will be of type NACK.
477 struct ti_sci_msg_resp_query_clock_freq {
478 struct ti_sci_msg_hdr hdr;
483 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
484 * @hdr: Generic Header
485 * @dev_id: Device identifier this request is for
486 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
487 * allowable programmed frequency and does not account for clock
488 * tolerances and jitter.
489 * @target_freq_hz: The target clock frequency. The clock will be programmed
490 * at a rate as close to this target frequency as possible.
491 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
492 * allowable programmed frequency and does not account for clock
493 * tolerances and jitter.
494 * @clk_id: Clock identifier for the device for this request.
496 * NOTE: Normally clock frequency management is automatically done by TISCI
497 * entity. In case of specific requests, TISCI evaluates capability to achieve
498 * requested range and responds with success/failure message.
500 * This sets the desired frequency for a clock within an allowable
501 * range. This message will fail on an enabled clock unless
502 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
503 * if other clocks have their frequency modified due to this message,
504 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
506 * Calling set frequency on a clock input to the SoC pseudo-device will
507 * inform the PMMC of that clock's frequency. Setting a frequency of
508 * zero will indicate the clock is disabled.
510 * Calling set frequency on clock outputs from the SoC pseudo-device will
511 * function similarly to setting the clock frequency on a device.
513 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
516 struct ti_sci_msg_req_set_clock_freq {
517 struct ti_sci_msg_hdr hdr;
526 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
527 * @hdr: Generic Header
528 * @dev_id: Device identifier this request is for
529 * @clk_id: Clock identifier for the device for this request.
531 * NOTE: Normally clock frequency management is automatically done by TISCI
532 * entity. In some cases, clock frequencies are configured by host.
534 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
535 * that the clock is currently at.
537 struct ti_sci_msg_req_get_clock_freq {
538 struct ti_sci_msg_hdr hdr;
544 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
545 * @hdr: Generic Header
546 * @freq_hz: Frequency that the clock is currently on, in Hz.
548 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
550 struct ti_sci_msg_resp_get_clock_freq {
551 struct ti_sci_msg_hdr hdr;
555 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
558 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
559 * range of resources.
560 * @hdr: Generic Header
561 * @type: Unique resource assignment type
562 * @subtype: Resource assignment subtype within the resource type.
563 * @secondary_host: Host processing entity to which the resources are
564 * allocated. This is required only when the destination
565 * host id id different from ti sci interface host id,
566 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
568 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
569 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
571 struct ti_sci_msg_req_get_resource_range {
572 struct ti_sci_msg_hdr hdr;
573 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
574 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
581 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
582 * @hdr: Generic Header
583 * @range_start: Start index of the resource range.
584 * @range_num: Number of resources in the range.
586 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
588 struct ti_sci_msg_resp_get_resource_range {
589 struct ti_sci_msg_hdr hdr;
594 #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
595 #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
596 #define TISCI_ADDR_HIGH_SHIFT 32
599 * struct ti_sci_msg_req_proc_request - Request a processor
601 * @hdr: Generic Header
602 * @processor_id: ID of processor
604 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
607 struct ti_sci_msg_req_proc_request {
608 struct ti_sci_msg_hdr hdr;
613 * struct ti_sci_msg_req_proc_release - Release a processor
615 * @hdr: Generic Header
616 * @processor_id: ID of processor
618 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
621 struct ti_sci_msg_req_proc_release {
622 struct ti_sci_msg_hdr hdr;
627 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
629 * @hdr: Generic Header
630 * @processor_id: ID of processor
631 * @host_id: New Host we want to give control to
633 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
636 struct ti_sci_msg_req_proc_handover {
637 struct ti_sci_msg_hdr hdr;
642 /* A53 Config Flags */
643 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
644 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
645 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
646 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
647 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
649 /* R5 Config Flags */
650 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
651 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
652 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
653 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
654 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
655 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
656 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
657 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
660 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
661 * @hdr: Generic Header
662 * @processor_id: ID of processor
663 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
664 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
665 * @config_flags_set: Optional Processor specific Config Flags to set.
666 * Setting a bit here implies required bit sets to 1.
667 * @config_flags_clear: Optional Processor specific Config Flags to clear.
668 * Setting a bit here implies required bit gets cleared.
670 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
673 struct ti_sci_msg_req_set_proc_boot_config {
674 struct ti_sci_msg_hdr hdr;
678 u32 config_flags_set;
679 u32 config_flags_clear;
682 /* R5 Control Flags */
683 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
686 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
687 * @hdr: Generic Header
688 * @processor_id: ID of processor
689 * @control_flags_set: Optional Processor specific Control Flags to set.
690 * Setting a bit here implies required bit sets to 1.
691 * @control_flags_clear:Optional Processor specific Control Flags to clear.
692 * Setting a bit here implies required bit gets cleared.
694 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
697 struct ti_sci_msg_req_set_proc_boot_ctrl {
698 struct ti_sci_msg_hdr hdr;
700 u32 control_flags_set;
701 u32 control_flags_clear;
705 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
706 * @hdr: Generic Header
707 * @cert_addr_low: Lower 32bit (Little Endian) of certificate
708 * @cert_addr_high: Higher 32bit (Little Endian) of certificate
710 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
713 struct ti_sci_msg_req_proc_auth_boot_image {
714 struct ti_sci_msg_hdr hdr;
719 struct ti_sci_msg_resp_proc_auth_boot_image {
720 struct ti_sci_msg_hdr hdr;
727 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
728 * @hdr: Generic Header
729 * @processor_id: ID of processor
731 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
732 * message, or NACK in case of inability to satisfy request.
734 struct ti_sci_msg_req_get_proc_boot_status {
735 struct ti_sci_msg_hdr hdr;
739 /* ARMv8 Status Flags */
740 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
741 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
743 /* R5 Status Flags */
744 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
745 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
746 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
747 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
750 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
751 * @hdr: Generic Header
752 * @processor_id: ID of processor
753 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
754 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
755 * @config_flags: Optional Processor specific Config Flags set.
756 * @control_flags: Optional Processor specific Control Flags.
757 * @status_flags: Optional Processor specific Status Flags set.
759 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
761 struct ti_sci_msg_resp_get_proc_boot_status {
762 struct ti_sci_msg_hdr hdr;
772 * struct ti_sci_msg_req_wait_proc_boot_status - Wait for a processor
774 * @hdr: Generic Header
775 * @processor_id: ID of processor
776 * @num_wait_iterations: Total number of iterations we will check before
777 * we will timeout and give up
778 * @num_match_iterations: How many iterations should we have continued
779 * status to account for status bits glitching.
780 * This is to make sure that match occurs for
781 * consecutive checks. This implies that the
782 * worst case should consider that the stable
783 * time should at the worst be num_wait_iterations
784 * num_match_iterations to prevent timeout.
785 * @delay_per_iteration_us: Specifies how long to wait (in micro seconds)
786 * between each status checks. This is the minimum
787 * duration, and overhead of register reads and
788 * checks are on top of this and can vary based on
790 * @delay_before_iterations_us: Specifies how long to wait (in micro seconds)
791 * before the very first check in the first
792 * iteration of status check loop. This is the
793 * minimum duration, and overhead of register
794 * reads and checks are.
795 * @status_flags_1_set_all_wait:If non-zero, Specifies that all bits of the
796 * status matching this field requested MUST be 1.
797 * @status_flags_1_set_any_wait:If non-zero, Specifies that at least one of the
798 * bits matching this field requested MUST be 1.
799 * @status_flags_1_clr_all_wait:If non-zero, Specifies that all bits of the
800 * status matching this field requested MUST be 0.
801 * @status_flags_1_clr_any_wait:If non-zero, Specifies that at least one of the
802 * bits matching this field requested MUST be 0.
804 * Request type is TISCI_MSG_WAIT_PROC_BOOT_STATUS, response is appropriate
805 * message, or NACK in case of inability to satisfy request.
807 struct ti_sci_msg_req_wait_proc_boot_status {
808 struct ti_sci_msg_hdr hdr;
810 u8 num_wait_iterations;
811 u8 num_match_iterations;
812 u8 delay_per_iteration_us;
813 u8 delay_before_iterations_us;
814 u32 status_flags_1_set_all_wait;
815 u32 status_flags_1_set_any_wait;
816 u32 status_flags_1_clr_all_wait;
817 u32 status_flags_1_clr_any_wait;
821 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
823 * Configures the non-real-time registers of a Navigator Subsystem ring.
824 * @hdr: Generic Header
825 * @valid_params: Bitfield defining validity of ring configuration parameters.
826 * The ring configuration fields are not valid, and will not be used for
827 * ring configuration, if their corresponding valid bit is zero.
829 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
830 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
831 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
832 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
833 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
834 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
835 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
836 * @index: ring index to be configured.
837 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
838 * RING_BA_LO register
839 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
840 * RING_BA_HI register.
841 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
843 * @mode: Specifies the mode the ring is to be configured.
844 * @size: Specifies encoded ring element size. To calculate the encoded size use
845 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
847 * @order_id: Specifies the ring's bus order ID.
849 struct ti_sci_msg_rm_ring_cfg_req {
850 struct ti_sci_msg_hdr hdr;
863 * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
865 * @hdr: Generic Header
867 struct ti_sci_msg_rm_ring_cfg_resp {
868 struct ti_sci_msg_hdr hdr;
872 * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
874 * Gets the configuration of the non-real-time register fields of a ring. The
875 * host, or a supervisor of the host, who owns the ring must be the requesting
876 * host. The values of the non-real-time registers are returned in
877 * @ti_sci_msg_rm_ring_get_cfg_resp.
879 * @hdr: Generic Header
880 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
881 * @index: ring index.
883 struct ti_sci_msg_rm_ring_get_cfg_req {
884 struct ti_sci_msg_hdr hdr;
890 * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
892 * Response received by host processor after RM has handled
893 * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
894 * non-real-time register values.
896 * @hdr: Generic Header
897 * @addr_lo: Ring 32 LSBs of base address
898 * @addr_hi: Ring 16 MSBs of base address.
899 * @count: Ring number of elements.
901 * @size: encoded Ring element size
902 * @order_id: ing order ID.
904 struct ti_sci_msg_rm_ring_get_cfg_resp {
905 struct ti_sci_msg_hdr hdr;
915 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
917 * @hdr: Generic Header
918 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
919 * used to pair the source and destination threads.
920 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
922 * UDMAP transmit channels mapped to source threads will have their
923 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
926 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
927 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
928 * the destination thread is not greater than or equal to 0x8000.
930 * UDMAP receive channels mapped to destination threads will have their
931 * RCHAN_THRD_ID register programmed with the source thread if the pairing
934 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
937 struct ti_sci_msg_psil_pair {
938 struct ti_sci_msg_hdr hdr;
945 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
947 * @hdr: Generic Header
948 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
949 * used to unpair the source and destination threads.
950 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
952 * UDMAP transmit channels mapped to source threads will have their
953 * TCHAN_THRD_ID register cleared if the unpairing is successful.
955 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
956 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
957 * the destination thread is not greater than or equal to 0x8000.
959 * UDMAP receive channels mapped to destination threads will have their
960 * RCHAN_THRD_ID register cleared if the unpairing is successful.
962 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
965 struct ti_sci_msg_psil_unpair {
966 struct ti_sci_msg_hdr hdr;
973 * Configures a Navigator Subsystem UDMAP transmit channel
975 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
976 * transmit channel. The channel index must be assigned to the host defined
977 * in the TISCI header via the RM board configuration resource assignment
980 * @hdr: Generic Header
982 * @valid_params: Bitfield defining validity of tx channel configuration
983 * parameters. The tx channel configuration fields are not valid, and will not
984 * be used for ch configuration, if their corresponding valid bit is zero.
986 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
987 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
988 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
989 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
990 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
991 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
992 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
993 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
994 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
995 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
996 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
997 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
998 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
999 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
1001 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
1003 * @index: UDMAP transmit channel index.
1005 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
1006 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
1009 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
1010 * configuration to be programmed into the tx_filt_einfo field of the
1011 * channel's TCHAN_TCFG register.
1013 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
1014 * configuration to be programmed into the tx_filt_pswords field of the
1015 * channel's TCHAN_TCFG register.
1017 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
1018 * interpretation configuration to be programmed into the tx_atype field of
1019 * the channel's TCHAN_TCFG register.
1021 * @tx_chan_type: UDMAP transmit channel functional channel type and work
1022 * passing mechanism configuration to be programmed into the tx_chan_type
1023 * field of the channel's TCHAN_TCFG register.
1025 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
1026 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
1027 * TCHAN_TCFG register.
1029 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
1030 * fetch configuration to be programmed into the tx_fetch_size field of the
1031 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
1032 * word count that can pass through the channel for any allowed descriptor type.
1034 * @tx_credit_count: UDMAP transmit channel transfer request credit count
1035 * configuration to be programmed into the count field of the TCHAN_TCREDIT
1036 * register. Specifies how many credits for complete TRs are available.
1038 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
1039 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
1040 * completion queue must be assigned to the host, or a subordinate of the host,
1041 * requesting configuration of the transmit channel.
1043 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
1044 * into the priority field of the channel's TCHAN_TPRI_CTRL register.
1046 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
1047 * qos field of the channel's TCHAN_TPRI_CTRL register.
1049 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
1050 * the orderid field of the channel's TCHAN_TPRI_CTRL register.
1052 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
1053 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
1054 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
1055 * section of the TRM for restrictions regarding this parameter.
1057 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
1058 * configuration to be programmed into the priority field of the channel's
1059 * TCHAN_TST_SCHED register.
1061 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
1062 struct ti_sci_msg_hdr hdr;
1079 u8 tx_sched_priority;
1083 * Response to configuring a UDMAP transmit channel.
1085 * @hdr: Standard TISCI header
1087 struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
1088 struct ti_sci_msg_hdr hdr;
1092 * Configures a Navigator Subsystem UDMAP receive channel
1094 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1095 * receive channel. The channel index must be assigned to the host defined
1096 * in the TISCI header via the RM board configuration resource assignment
1099 * @hdr: Generic Header
1101 * @valid_params: Bitfield defining validity of rx channel configuration
1103 * The rx channel configuration fields are not valid, and will not be used for
1104 * ch configuration, if their corresponding valid bit is zero.
1106 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1107 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1108 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1109 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1110 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1111 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1112 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1113 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1114 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1115 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1116 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1117 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1118 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1120 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1122 * @index: UDMAP receive channel index.
1124 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1125 * fetch configuration to be programmed into the rx_fetch_size field of the
1126 * channel's RCHAN_RCFG register.
1128 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1129 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1130 * The specified completion queue must be assigned to the host, or a subordinate
1131 * of the host, requesting configuration of the receive channel.
1133 * @rx_priority: UDMAP receive channel receive priority value to be programmed
1134 * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1136 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1137 * qos field of the channel's RCHAN_RPRI_CTRL register.
1139 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1140 * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1142 * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1143 * configuration to be programmed into the priority field of the channel's
1144 * RCHAN_RST_SCHED register.
1146 * @flowid_start: UDMAP receive channel additional flows starting index
1147 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1148 * register. Specifies the starting index for flow IDs the receive channel is to
1149 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1150 * set as valid and configured together. The starting flow ID set by
1151 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1152 * of flows beyond the default flows statically mapped to receive channels.
1153 * The additional flows must be assigned to the host, or a subordinate of the
1154 * host, requesting configuration of the receive channel.
1156 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1157 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1158 * This field specifies how many flow IDs are in the additional contiguous range
1159 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
1160 * set as valid and configured together. Disabling the valid_params field bit
1161 * for flowid_cnt indicates no flow IDs other than the default are to be
1162 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1163 * cannot be greater than the number of receive flows in the receive channel's
1164 * Navigator Subsystem. The additional flows must be assigned to the host, or a
1165 * subordinate of the host, requesting configuration of the receive channel.
1167 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1168 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1171 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1172 * interpretation configuration to be programmed into the rx_atype field of the
1173 * channel's RCHAN_RCFG register.
1175 * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1176 * mechanism configuration to be programmed into the rx_chan_type field of the
1177 * channel's RCHAN_RCFG register.
1179 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1180 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1182 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1183 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1185 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1186 struct ti_sci_msg_hdr hdr;
1195 u8 rx_sched_priority;
1206 * Response to configuring a UDMAP receive channel.
1208 * @hdr: Standard TISCI header
1210 struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
1211 struct ti_sci_msg_hdr hdr;
1215 * Configures a Navigator Subsystem UDMAP receive flow
1217 * Configures a Navigator Subsystem UDMAP receive flow's registers.
1218 * Configuration does not include the flow registers which handle size-based
1219 * free descriptor queue routing.
1221 * The flow index must be assigned to the host defined in the TISCI header via
1222 * the RM board configuration resource assignment range list.
1224 * @hdr: Standard TISCI header
1227 * Bitfield defining validity of rx flow configuration parameters. The
1228 * rx flow configuration fields are not valid, and will not be used for flow
1229 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1230 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1231 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1232 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1233 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1234 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1235 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1236 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1237 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1238 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1239 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1240 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1241 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1242 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1243 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1244 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1245 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1246 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1247 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1248 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1250 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1253 * @flow_index: UDMAP receive flow index for non-optional configuration.
1255 * @rx_einfo_present:
1256 * UDMAP receive flow extended packet info present configuration to be
1257 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1259 * @rx_psinfo_present:
1260 * UDMAP receive flow PS words present configuration to be programmed into the
1261 * rx_psinfo_present field of the flow's RFLOW_RFA register.
1263 * @rx_error_handling:
1264 * UDMAP receive flow error handling configuration to be programmed into the
1265 * rx_error_handling field of the flow's RFLOW_RFA register.
1268 * UDMAP receive flow descriptor type configuration to be programmed into the
1269 * rx_desc_type field field of the flow's RFLOW_RFA register.
1272 * UDMAP receive flow start of packet offset configuration to be programmed
1273 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
1274 * section of the TRM for more information on this setting. Valid values for
1275 * this field are 0-255 bytes.
1278 * UDMAP receive flow destination queue configuration to be programmed into the
1279 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
1280 * destination queue must be valid within the Navigator Subsystem and must be
1281 * owned by the host, or a subordinate of the host, requesting allocation and
1282 * configuration of the receive flow.
1285 * UDMAP receive flow source tag high byte constant configuration to be
1286 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1287 * See the UDMAP section of the TRM for more information on this setting.
1290 * UDMAP receive flow source tag low byte constant configuration to be
1291 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1292 * See the UDMAP section of the TRM for more information on this setting.
1295 * UDMAP receive flow destination tag high byte constant configuration to be
1296 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1297 * See the UDMAP section of the TRM for more information on this setting.
1300 * UDMAP receive flow destination tag low byte constant configuration to be
1301 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1302 * See the UDMAP section of the TRM for more information on this setting.
1304 * @rx_src_tag_hi_sel:
1305 * UDMAP receive flow source tag high byte selector configuration to be
1306 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
1307 * the UDMAP section of the TRM for more information on this setting.
1309 * @rx_src_tag_lo_sel:
1310 * UDMAP receive flow source tag low byte selector configuration to be
1311 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
1312 * the UDMAP section of the TRM for more information on this setting.
1314 * @rx_dest_tag_hi_sel:
1315 * UDMAP receive flow destination tag high byte selector configuration to be
1316 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
1317 * the UDMAP section of the TRM for more information on this setting.
1319 * @rx_dest_tag_lo_sel:
1320 * UDMAP receive flow destination tag low byte selector configuration to be
1321 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
1322 * the UDMAP section of the TRM for more information on this setting.
1324 * @rx_fdq0_sz0_qnum:
1325 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1326 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
1327 * UDMAP section of the TRM for more information on this setting. The specified
1328 * free queue must be valid within the Navigator Subsystem and must be owned
1329 * by the host, or a subordinate of the host, requesting allocation and
1330 * configuration of the receive flow.
1333 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1334 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
1335 * UDMAP section of the TRM for more information on this setting. The specified
1336 * free queue must be valid within the Navigator Subsystem and must be owned
1337 * by the host, or a subordinate of the host, requesting allocation and
1338 * configuration of the receive flow.
1341 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1342 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
1343 * UDMAP section of the TRM for more information on this setting. The specified
1344 * free queue must be valid within the Navigator Subsystem and must be owned
1345 * by the host, or a subordinate of the host, requesting allocation and
1346 * configuration of the receive flow.
1349 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1350 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
1351 * UDMAP section of the TRM for more information on this setting. The specified
1352 * free queue must be valid within the Navigator Subsystem and must be owned
1353 * by the host, or a subordinate of the host, requesting allocation and
1354 * configuration of the receive flow.
1357 * UDMAP receive flow PS words location configuration to be programmed into the
1358 * rx_ps_location field of the flow's RFLOW_RFA register.
1360 struct ti_sci_msg_rm_udmap_flow_cfg_req {
1361 struct ti_sci_msg_hdr hdr;
1365 u8 rx_einfo_present;
1366 u8 rx_psinfo_present;
1367 u8 rx_error_handling;
1375 u8 rx_src_tag_hi_sel;
1376 u8 rx_src_tag_lo_sel;
1377 u8 rx_dest_tag_hi_sel;
1378 u8 rx_dest_tag_lo_sel;
1379 u16 rx_fdq0_sz0_qnum;
1387 * Response to configuring a Navigator Subsystem UDMAP receive flow
1389 * @hdr: Standard TISCI header
1391 struct ti_sci_msg_rm_udmap_flow_cfg_resp {
1392 struct ti_sci_msg_hdr hdr;
1395 #define FWL_MAX_PRIVID_SLOTS 3U
1398 * struct ti_sci_msg_fwl_set_firewall_region_req - Request for configuring the firewall permissions.
1400 * @hdr: Generic Header
1402 * @fwl_id: Firewall ID in question
1403 * @region: Region or channel number to set config info
1404 * This field is unused in case of a simple firewall and must be initialized
1405 * to zero. In case of a region based firewall, this field indicates the
1406 * region in question. (index starting from 0) In case of a channel based
1407 * firewall, this field indicates the channel in question (index starting
1409 * @n_permission_regs: Number of permission registers to set
1410 * @control: Contents of the firewall CONTROL register to set
1411 * @permissions: Contents of the firewall PERMISSION register to set
1412 * @start_address: Contents of the firewall START_ADDRESS register to set
1413 * @end_address: Contents of the firewall END_ADDRESS register to set
1416 struct ti_sci_msg_fwl_set_firewall_region_req {
1417 struct ti_sci_msg_hdr hdr;
1420 u32 n_permission_regs;
1422 u32 permissions[FWL_MAX_PRIVID_SLOTS];
1428 * struct ti_sci_msg_fwl_get_firewall_region_req - Request for retrieving the firewall permissions
1430 * @hdr: Generic Header
1432 * @fwl_id: Firewall ID in question
1433 * @region: Region or channel number to get config info
1434 * This field is unused in case of a simple firewall and must be initialized
1435 * to zero. In case of a region based firewall, this field indicates the
1436 * region in question (index starting from 0). In case of a channel based
1437 * firewall, this field indicates the channel in question (index starting
1439 * @n_permission_regs: Number of permission registers to retrieve
1441 struct ti_sci_msg_fwl_get_firewall_region_req {
1442 struct ti_sci_msg_hdr hdr;
1445 u32 n_permission_regs;
1449 * struct ti_sci_msg_fwl_get_firewall_region_resp - Response for retrieving the firewall permissions
1451 * @hdr: Generic Header
1453 * @fwl_id: Firewall ID in question
1454 * @region: Region or channel number to set config info This field is
1455 * unused in case of a simple firewall and must be initialized to zero. In
1456 * case of a region based firewall, this field indicates the region in
1457 * question. (index starting from 0) In case of a channel based firewall, this
1458 * field indicates the channel in question (index starting from 0)
1459 * @n_permission_regs: Number of permission registers retrieved
1460 * @control: Contents of the firewall CONTROL register
1461 * @permissions: Contents of the firewall PERMISSION registers
1462 * @start_address: Contents of the firewall START_ADDRESS register This is not applicable for channelized firewalls.
1463 * @end_address: Contents of the firewall END_ADDRESS register This is not applicable for channelized firewalls.
1465 struct ti_sci_msg_fwl_get_firewall_region_resp {
1466 struct ti_sci_msg_hdr hdr;
1469 u32 n_permission_regs;
1471 u32 permissions[FWL_MAX_PRIVID_SLOTS];
1477 * struct ti_sci_msg_fwl_change_owner_info_req - Request for a firewall owner change
1479 * @hdr: Generic Header
1481 * @fwl_id: Firewall ID in question
1482 * @region: Region or channel number if applicable
1483 * @owner_index: New owner index to transfer ownership to
1485 struct ti_sci_msg_fwl_change_owner_info_req {
1486 struct ti_sci_msg_hdr hdr;
1493 * struct ti_sci_msg_fwl_change_owner_info_resp - Response for a firewall owner change
1495 * @hdr: Generic Header
1497 * @fwl_id: Firewall ID specified in request
1498 * @region: Region or channel number specified in request
1499 * @owner_index: Owner index specified in request
1500 * @owner_privid: New owner priv-ID returned by DMSC.
1501 * @owner_permission_bits: New owner permission bits returned by DMSC.
1503 struct ti_sci_msg_fwl_change_owner_info_resp {
1504 struct ti_sci_msg_hdr hdr;
1509 u16 owner_permission_bits;
1512 #endif /* __TI_SCI_H */