1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Texas Instruments System Control Interface (TISCI) Protocol
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
10 * Based on drivers/firmware/ti_sci.h from Linux.
17 /* Generic Messages */
18 #define TI_SCI_MSG_ENABLE_WDT 0x0000
19 #define TI_SCI_MSG_WAKE_RESET 0x0001
20 #define TI_SCI_MSG_VERSION 0x0002
21 #define TI_SCI_MSG_WAKE_REASON 0x0003
22 #define TI_SCI_MSG_GOODBYE 0x0004
23 #define TI_SCI_MSG_SYS_RESET 0x0005
24 #define TI_SCI_MSG_BOARD_CONFIG 0x000b
25 #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c
26 #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d
27 #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e
30 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
31 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
32 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
35 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
36 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
37 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
38 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
39 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
40 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
41 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
42 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
44 /* Processor Control Messages */
45 #define TISCI_MSG_PROC_REQUEST 0xc000
46 #define TISCI_MSG_PROC_RELEASE 0xc001
47 #define TISCI_MSG_PROC_HANDOVER 0xc005
48 #define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
49 #define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
50 #define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
51 #define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
53 /* Resource Management Requests */
54 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
56 /* NAVSS resource management */
57 /* Ringacc requests */
58 #define TI_SCI_MSG_RM_RING_CFG 0x1110
59 #define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
62 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
63 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
65 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
66 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
67 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
68 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
69 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
70 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
72 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
73 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
74 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
75 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
76 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
77 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
78 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
79 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
82 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
83 * @type: Type of messages: One of TI_SCI_MSG* values
84 * @host: Host of the message
85 * @seq: Message identifier indicating a transfer sequence
86 * @flags: Flag for the message
88 struct ti_sci_msg_hdr {
92 #define TI_SCI_MSG_FLAG(val) (1 << (val))
93 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
94 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
95 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
96 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
97 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
98 /* Additional Flags */
103 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
104 * via secure transport.
105 * @checksum: crc16 checksum for the entire message
106 * @reserved: Reserved for future use.
108 struct ti_sci_secure_msg_hdr {
114 * struct ti_sci_msg_resp_version - Response for a message
115 * @hdr: Generic header
116 * @firmware_description: String describing the firmware
117 * @firmware_revision: Firmware revision
118 * @abi_major: Major version of the ABI that firmware supports
119 * @abi_minor: Minor version of the ABI that firmware supports
121 * In general, ABI version changes follow the rule that minor version increments
122 * are backward compatible. Major revision changes in ABI may not be
123 * backward compatible.
125 * Response to a generic message with message type TI_SCI_MSG_VERSION
127 struct ti_sci_msg_resp_version {
128 struct ti_sci_msg_hdr hdr;
129 char firmware_description[32];
130 u16 firmware_revision;
136 * struct ti_sci_msg_req_reboot - Reboot the SoC
137 * @hdr: Generic Header
139 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
142 struct ti_sci_msg_req_reboot {
143 struct ti_sci_msg_hdr hdr;
147 * struct ti_sci_msg_board_config - Board configuration message
148 * @hdr: Generic Header
149 * @boardcfgp_low: Lower 32 bit of the pointer pointing to the board
151 * @boardcfgp_high: Upper 32 bit of the pointer pointing to the board
153 * @boardcfg_size: Size of board configuration data object
154 * Request type is TI_SCI_MSG_BOARD_CONFIG, responded with a generic
157 struct ti_sci_msg_board_config {
158 struct ti_sci_msg_hdr hdr;
165 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
166 * @hdr: Generic header
167 * @id: Indicates which device to modify
168 * @reserved: Reserved space in message, must be 0 for backward compatibility
169 * @state: The desired state of the device.
171 * Certain flags can also be set to alter the device state:
172 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
173 * The meaning of this flag will vary slightly from device to device and from
174 * SoC to SoC but it generally allows the device to wake the SoC out of deep
176 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
177 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
178 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
179 * If another host already has this device set to STATE_RETENTION or STATE_ON,
180 * the message will fail. Once successful, other hosts attempting to set
181 * STATE_RETENTION or STATE_ON will fail.
183 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
186 struct ti_sci_msg_req_set_device_state {
187 /* Additional hdr->flags options */
188 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
189 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
190 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
191 struct ti_sci_msg_hdr hdr;
195 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0
196 #define MSG_DEVICE_SW_STATE_RETENTION 1
197 #define MSG_DEVICE_SW_STATE_ON 2
202 * struct ti_sci_msg_req_get_device_state - Request to get device.
203 * @hdr: Generic header
204 * @id: Device Identifier
206 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
209 struct ti_sci_msg_req_get_device_state {
210 struct ti_sci_msg_hdr hdr;
215 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
216 * @hdr: Generic header
217 * @context_loss_count: Indicates how many times the device has lost context. A
218 * driver can use this monotonic counter to determine if the device has
219 * lost context since the last time this message was exchanged.
220 * @resets: Programmed state of the reset lines.
221 * @programmed_state: The state as programmed by set_device.
222 * - Uses the MSG_DEVICE_SW_* macros
223 * @current_state: The actual state of the hardware.
225 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
227 struct ti_sci_msg_resp_get_device_state {
228 struct ti_sci_msg_hdr hdr;
229 u32 context_loss_count;
232 #define MSG_DEVICE_HW_STATE_OFF 0
233 #define MSG_DEVICE_HW_STATE_ON 1
234 #define MSG_DEVICE_HW_STATE_TRANS 2
239 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
240 * configuration of the device
241 * @hdr: Generic header
242 * @id: Indicates which device to modify
243 * @resets: A bit field of resets for the device. The meaning, behavior,
244 * and usage of the reset flags are device specific. 0 for a bit
245 * indicates releasing the reset represented by that bit while 1
246 * indicates keeping it held.
248 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
251 struct ti_sci_msg_req_set_device_resets {
252 struct ti_sci_msg_hdr hdr;
258 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
259 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
260 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
261 * via spread spectrum clocking.
262 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
263 * frequency to be changed while it is running so long as it
264 * is within the min/max limits.
265 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
266 * is only applicable to clock inputs on the SoC pseudo-device.
267 * @dev_id: Device identifier this request is for
268 * @clk_id: Clock identifier for the device for this request.
269 * Each device has it's own set of clock inputs. This indexes
270 * which clock input to modify.
271 * @request_state: Request the state for the clock to be set to.
272 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
273 * it can be disabled, regardless of the state of the device
274 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
275 * automatically manage the state of this clock. If the device
276 * is enabled, then the clock is enabled. If the device is set
277 * to off or retention, then the clock is internally set as not
278 * being required by the device.(default)
279 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
280 * regardless of the state of the device.
282 * Normally, all required clocks are managed by TISCI entity, this is used
283 * only for specific control *IF* required. Auto managed state is
284 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
285 * will explicitly control.
287 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
288 * ACK or NACK message.
290 struct ti_sci_msg_req_set_clock_state {
291 /* Additional hdr->flags options */
292 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
293 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
294 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
295 struct ti_sci_msg_hdr hdr;
298 #define MSG_CLOCK_SW_STATE_UNREQ 0
299 #define MSG_CLOCK_SW_STATE_AUTO 1
300 #define MSG_CLOCK_SW_STATE_REQ 2
305 * struct ti_sci_msg_req_get_clock_state - Request for clock state
306 * @hdr: Generic Header
307 * @dev_id: Device identifier this request is for
308 * @clk_id: Clock identifier for the device for this request.
309 * Each device has it's own set of clock inputs. This indexes
310 * which clock input to get state of.
312 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
315 struct ti_sci_msg_req_get_clock_state {
316 struct ti_sci_msg_hdr hdr;
322 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
323 * @hdr: Generic Header
324 * @programmed_state: Any programmed state of the clock. This is one of
325 * MSG_CLOCK_SW_STATE* values.
326 * @current_state: Current state of the clock. This is one of:
327 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
328 * MSG_CLOCK_HW_STATE_READY: Clock is ready
330 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
332 struct ti_sci_msg_resp_get_clock_state {
333 struct ti_sci_msg_hdr hdr;
335 #define MSG_CLOCK_HW_STATE_NOT_READY 0
336 #define MSG_CLOCK_HW_STATE_READY 1
341 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
342 * @hdr: Generic Header
343 * @dev_id: Device identifier this request is for
344 * @clk_id: Clock identifier for the device for this request.
345 * Each device has it's own set of clock inputs. This indexes
346 * which clock input to modify.
347 * @parent_id: The new clock parent is selectable by an index via this
350 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
351 * ACK / NACK message.
353 struct ti_sci_msg_req_set_clock_parent {
354 struct ti_sci_msg_hdr hdr;
361 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
362 * @hdr: Generic Header
363 * @dev_id: Device identifier this request is for
364 * @clk_id: Clock identifier for the device for this request.
365 * Each device has it's own set of clock inputs. This indexes
366 * which clock input to get the parent for.
368 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
370 struct ti_sci_msg_req_get_clock_parent {
371 struct ti_sci_msg_hdr hdr;
377 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
378 * @hdr: Generic Header
379 * @parent_id: The current clock parent
381 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
383 struct ti_sci_msg_resp_get_clock_parent {
384 struct ti_sci_msg_hdr hdr;
389 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
390 * @hdr: Generic header
391 * @dev_id: Device identifier this request is for
392 * @clk_id: Clock identifier for the device for this request.
394 * This request provides information about how many clock parent options
395 * are available for a given clock to a device. This is typically used
398 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
399 * message, or NACK in case of inability to satisfy request.
401 struct ti_sci_msg_req_get_clock_num_parents {
402 struct ti_sci_msg_hdr hdr;
408 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
409 * @hdr: Generic header
410 * @num_parents: Number of clock parents
412 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
414 struct ti_sci_msg_resp_get_clock_num_parents {
415 struct ti_sci_msg_hdr hdr;
420 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
421 * @hdr: Generic Header
422 * @dev_id: Device identifier this request is for
423 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
424 * allowable programmed frequency and does not account for clock
425 * tolerances and jitter.
426 * @target_freq_hz: The target clock frequency. A frequency will be found
427 * as close to this target frequency as possible.
428 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
429 * allowable programmed frequency and does not account for clock
430 * tolerances and jitter.
431 * @clk_id: Clock identifier for the device for this request.
433 * NOTE: Normally clock frequency management is automatically done by TISCI
434 * entity. In case of specific requests, TISCI evaluates capability to achieve
435 * requested frequency within provided range and responds with
438 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
439 * or NACK in case of inability to satisfy request.
441 struct ti_sci_msg_req_query_clock_freq {
442 struct ti_sci_msg_hdr hdr;
451 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
452 * @hdr: Generic Header
453 * @freq_hz: Frequency that is the best match in Hz.
455 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
456 * cannot be satisfied, the message will be of type NACK.
458 struct ti_sci_msg_resp_query_clock_freq {
459 struct ti_sci_msg_hdr hdr;
464 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
465 * @hdr: Generic Header
466 * @dev_id: Device identifier this request is for
467 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
468 * allowable programmed frequency and does not account for clock
469 * tolerances and jitter.
470 * @target_freq_hz: The target clock frequency. The clock will be programmed
471 * at a rate as close to this target frequency as possible.
472 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
473 * allowable programmed frequency and does not account for clock
474 * tolerances and jitter.
475 * @clk_id: Clock identifier for the device for this request.
477 * NOTE: Normally clock frequency management is automatically done by TISCI
478 * entity. In case of specific requests, TISCI evaluates capability to achieve
479 * requested range and responds with success/failure message.
481 * This sets the desired frequency for a clock within an allowable
482 * range. This message will fail on an enabled clock unless
483 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
484 * if other clocks have their frequency modified due to this message,
485 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
487 * Calling set frequency on a clock input to the SoC pseudo-device will
488 * inform the PMMC of that clock's frequency. Setting a frequency of
489 * zero will indicate the clock is disabled.
491 * Calling set frequency on clock outputs from the SoC pseudo-device will
492 * function similarly to setting the clock frequency on a device.
494 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
497 struct ti_sci_msg_req_set_clock_freq {
498 struct ti_sci_msg_hdr hdr;
507 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
508 * @hdr: Generic Header
509 * @dev_id: Device identifier this request is for
510 * @clk_id: Clock identifier for the device for this request.
512 * NOTE: Normally clock frequency management is automatically done by TISCI
513 * entity. In some cases, clock frequencies are configured by host.
515 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
516 * that the clock is currently at.
518 struct ti_sci_msg_req_get_clock_freq {
519 struct ti_sci_msg_hdr hdr;
525 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
526 * @hdr: Generic Header
527 * @freq_hz: Frequency that the clock is currently on, in Hz.
529 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
531 struct ti_sci_msg_resp_get_clock_freq {
532 struct ti_sci_msg_hdr hdr;
536 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
539 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
540 * range of resources.
541 * @hdr: Generic Header
542 * @type: Unique resource assignment type
543 * @subtype: Resource assignment subtype within the resource type.
544 * @secondary_host: Host processing entity to which the resources are
545 * allocated. This is required only when the destination
546 * host id id different from ti sci interface host id,
547 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
549 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
550 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
552 struct ti_sci_msg_req_get_resource_range {
553 struct ti_sci_msg_hdr hdr;
554 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
555 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
562 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
563 * @hdr: Generic Header
564 * @range_start: Start index of the resource range.
565 * @range_num: Number of resources in the range.
567 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
569 struct ti_sci_msg_resp_get_resource_range {
570 struct ti_sci_msg_hdr hdr;
575 #define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
576 #define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
577 #define TISCI_ADDR_HIGH_SHIFT 32
580 * struct ti_sci_msg_req_proc_request - Request a processor
582 * @hdr: Generic Header
583 * @processor_id: ID of processor
585 * Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
588 struct ti_sci_msg_req_proc_request {
589 struct ti_sci_msg_hdr hdr;
594 * struct ti_sci_msg_req_proc_release - Release a processor
596 * @hdr: Generic Header
597 * @processor_id: ID of processor
599 * Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
602 struct ti_sci_msg_req_proc_release {
603 struct ti_sci_msg_hdr hdr;
608 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
610 * @hdr: Generic Header
611 * @processor_id: ID of processor
612 * @host_id: New Host we want to give control to
614 * Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
617 struct ti_sci_msg_req_proc_handover {
618 struct ti_sci_msg_hdr hdr;
623 /* A53 Config Flags */
624 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
625 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
626 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
627 #define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
628 #define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
630 /* R5 Config Flags */
631 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
632 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
633 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
634 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
635 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
636 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
637 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
638 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
641 * struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
642 * @hdr: Generic Header
643 * @processor_id: ID of processor
644 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
645 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
646 * @config_flags_set: Optional Processor specific Config Flags to set.
647 * Setting a bit here implies required bit sets to 1.
648 * @config_flags_clear: Optional Processor specific Config Flags to clear.
649 * Setting a bit here implies required bit gets cleared.
651 * Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
654 struct ti_sci_msg_req_set_proc_boot_config {
655 struct ti_sci_msg_hdr hdr;
659 u32 config_flags_set;
660 u32 config_flags_clear;
663 /* R5 Control Flags */
664 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
667 * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
668 * @hdr: Generic Header
669 * @processor_id: ID of processor
670 * @control_flags_set: Optional Processor specific Control Flags to set.
671 * Setting a bit here implies required bit sets to 1.
672 * @control_flags_clear:Optional Processor specific Control Flags to clear.
673 * Setting a bit here implies required bit gets cleared.
675 * Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
678 struct ti_sci_msg_req_set_proc_boot_ctrl {
679 struct ti_sci_msg_hdr hdr;
681 u32 control_flags_set;
682 u32 control_flags_clear;
686 * struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
687 * @hdr: Generic Header
688 * @processor_id: ID of processor
689 * @cert_addr_low: Lower 32bit (Little Endian) of certificate
690 * @cert_addr_high: Higher 32bit (Little Endian) of certificate
692 * Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
695 struct ti_sci_msg_req_proc_auth_boot_image {
696 struct ti_sci_msg_hdr hdr;
703 * struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
704 * @hdr: Generic Header
705 * @processor_id: ID of processor
707 * Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
708 * message, or NACK in case of inability to satisfy request.
710 struct ti_sci_msg_req_get_proc_boot_status {
711 struct ti_sci_msg_hdr hdr;
715 /* ARMv8 Status Flags */
716 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
717 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
719 /* R5 Status Flags */
720 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
721 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
722 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
723 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
726 * struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
727 * @hdr: Generic Header
728 * @processor_id: ID of processor
729 * @bootvector_low: Lower 32bit (Little Endian) of boot vector
730 * @bootvector_high: Higher 32bit (Little Endian) of boot vector
731 * @config_flags: Optional Processor specific Config Flags set.
732 * @control_flags: Optional Processor specific Control Flags.
733 * @status_flags: Optional Processor specific Status Flags set.
735 * Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
737 struct ti_sci_msg_resp_get_proc_boot_status {
738 struct ti_sci_msg_hdr hdr;
748 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
750 * Configures the non-real-time registers of a Navigator Subsystem ring.
751 * @hdr: Generic Header
752 * @valid_params: Bitfield defining validity of ring configuration parameters.
753 * The ring configuration fields are not valid, and will not be used for
754 * ring configuration, if their corresponding valid bit is zero.
756 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
757 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
758 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
759 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
760 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
761 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
762 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
763 * @index: ring index to be configured.
764 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
765 * RING_BA_LO register
766 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
767 * RING_BA_HI register.
768 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
770 * @mode: Specifies the mode the ring is to be configured.
771 * @size: Specifies encoded ring element size. To calculate the encoded size use
772 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
774 * @order_id: Specifies the ring's bus order ID.
776 struct ti_sci_msg_rm_ring_cfg_req {
777 struct ti_sci_msg_hdr hdr;
790 * struct ti_sci_msg_rm_ring_cfg_resp - Response to configuring a ring.
792 * @hdr: Generic Header
794 struct ti_sci_msg_rm_ring_cfg_resp {
795 struct ti_sci_msg_hdr hdr;
799 * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
801 * Gets the configuration of the non-real-time register fields of a ring. The
802 * host, or a supervisor of the host, who owns the ring must be the requesting
803 * host. The values of the non-real-time registers are returned in
804 * @ti_sci_msg_rm_ring_get_cfg_resp.
806 * @hdr: Generic Header
807 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
808 * @index: ring index.
810 struct ti_sci_msg_rm_ring_get_cfg_req {
811 struct ti_sci_msg_hdr hdr;
817 * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
819 * Response received by host processor after RM has handled
820 * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
821 * non-real-time register values.
823 * @hdr: Generic Header
824 * @addr_lo: Ring 32 LSBs of base address
825 * @addr_hi: Ring 16 MSBs of base address.
826 * @count: Ring number of elements.
828 * @size: encoded Ring element size
829 * @order_id: ing order ID.
831 struct ti_sci_msg_rm_ring_get_cfg_resp {
832 struct ti_sci_msg_hdr hdr;
842 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
844 * @hdr: Generic Header
845 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
846 * used to pair the source and destination threads.
847 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
849 * UDMAP transmit channels mapped to source threads will have their
850 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
853 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
854 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
855 * the destination thread is not greater than or equal to 0x8000.
857 * UDMAP receive channels mapped to destination threads will have their
858 * RCHAN_THRD_ID register programmed with the source thread if the pairing
861 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
864 struct ti_sci_msg_psil_pair {
865 struct ti_sci_msg_hdr hdr;
872 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
874 * @hdr: Generic Header
875 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
876 * used to unpair the source and destination threads.
877 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
879 * UDMAP transmit channels mapped to source threads will have their
880 * TCHAN_THRD_ID register cleared if the unpairing is successful.
882 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
883 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
884 * the destination thread is not greater than or equal to 0x8000.
886 * UDMAP receive channels mapped to destination threads will have their
887 * RCHAN_THRD_ID register cleared if the unpairing is successful.
889 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
892 struct ti_sci_msg_psil_unpair {
893 struct ti_sci_msg_hdr hdr;
900 * Configures a Navigator Subsystem UDMAP transmit channel
902 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
903 * transmit channel. The channel index must be assigned to the host defined
904 * in the TISCI header via the RM board configuration resource assignment
907 * @hdr: Generic Header
909 * @valid_params: Bitfield defining validity of tx channel configuration
910 * parameters. The tx channel configuration fields are not valid, and will not
911 * be used for ch configuration, if their corresponding valid bit is zero.
913 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
914 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
915 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
916 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
917 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
918 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
919 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
920 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
921 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
922 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
923 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
924 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
925 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
926 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
928 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
930 * @index: UDMAP transmit channel index.
932 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
933 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
936 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
937 * configuration to be programmed into the tx_filt_einfo field of the
938 * channel's TCHAN_TCFG register.
940 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
941 * configuration to be programmed into the tx_filt_pswords field of the
942 * channel's TCHAN_TCFG register.
944 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
945 * interpretation configuration to be programmed into the tx_atype field of
946 * the channel's TCHAN_TCFG register.
948 * @tx_chan_type: UDMAP transmit channel functional channel type and work
949 * passing mechanism configuration to be programmed into the tx_chan_type
950 * field of the channel's TCHAN_TCFG register.
952 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
953 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
954 * TCHAN_TCFG register.
956 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
957 * fetch configuration to be programmed into the tx_fetch_size field of the
958 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
959 * word count that can pass through the channel for any allowed descriptor type.
961 * @tx_credit_count: UDMAP transmit channel transfer request credit count
962 * configuration to be programmed into the count field of the TCHAN_TCREDIT
963 * register. Specifies how many credits for complete TRs are available.
965 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
966 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
967 * completion queue must be assigned to the host, or a subordinate of the host,
968 * requesting configuration of the transmit channel.
970 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
971 * into the priority field of the channel's TCHAN_TPRI_CTRL register.
973 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
974 * qos field of the channel's TCHAN_TPRI_CTRL register.
976 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
977 * the orderid field of the channel's TCHAN_TPRI_CTRL register.
979 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
980 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
981 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
982 * section of the TRM for restrictions regarding this parameter.
984 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
985 * configuration to be programmed into the priority field of the channel's
986 * TCHAN_TST_SCHED register.
988 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
989 struct ti_sci_msg_hdr hdr;
1006 u8 tx_sched_priority;
1010 * Response to configuring a UDMAP transmit channel.
1012 * @hdr: Standard TISCI header
1014 struct ti_sci_msg_rm_udmap_tx_ch_cfg_resp {
1015 struct ti_sci_msg_hdr hdr;
1019 * Configures a Navigator Subsystem UDMAP receive channel
1021 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1022 * receive channel. The channel index must be assigned to the host defined
1023 * in the TISCI header via the RM board configuration resource assignment
1026 * @hdr: Generic Header
1028 * @valid_params: Bitfield defining validity of rx channel configuration
1030 * The rx channel configuration fields are not valid, and will not be used for
1031 * ch configuration, if their corresponding valid bit is zero.
1033 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1034 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1035 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1036 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1037 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1038 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1039 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1040 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1041 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1042 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1043 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1044 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1045 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1047 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1049 * @index: UDMAP receive channel index.
1051 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1052 * fetch configuration to be programmed into the rx_fetch_size field of the
1053 * channel's RCHAN_RCFG register.
1055 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1056 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1057 * The specified completion queue must be assigned to the host, or a subordinate
1058 * of the host, requesting configuration of the receive channel.
1060 * @rx_priority: UDMAP receive channel receive priority value to be programmed
1061 * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1063 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1064 * qos field of the channel's RCHAN_RPRI_CTRL register.
1066 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1067 * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1069 * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1070 * configuration to be programmed into the priority field of the channel's
1071 * RCHAN_RST_SCHED register.
1073 * @flowid_start: UDMAP receive channel additional flows starting index
1074 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1075 * register. Specifies the starting index for flow IDs the receive channel is to
1076 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1077 * set as valid and configured together. The starting flow ID set by
1078 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1079 * of flows beyond the default flows statically mapped to receive channels.
1080 * The additional flows must be assigned to the host, or a subordinate of the
1081 * host, requesting configuration of the receive channel.
1083 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1084 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1085 * This field specifies how many flow IDs are in the additional contiguous range
1086 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
1087 * set as valid and configured together. Disabling the valid_params field bit
1088 * for flowid_cnt indicates no flow IDs other than the default are to be
1089 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1090 * cannot be greater than the number of receive flows in the receive channel's
1091 * Navigator Subsystem. The additional flows must be assigned to the host, or a
1092 * subordinate of the host, requesting configuration of the receive channel.
1094 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1095 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1098 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1099 * interpretation configuration to be programmed into the rx_atype field of the
1100 * channel's RCHAN_RCFG register.
1102 * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1103 * mechanism configuration to be programmed into the rx_chan_type field of the
1104 * channel's RCHAN_RCFG register.
1106 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1107 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1109 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1110 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1112 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1113 struct ti_sci_msg_hdr hdr;
1122 u8 rx_sched_priority;
1133 * Response to configuring a UDMAP receive channel.
1135 * @hdr: Standard TISCI header
1137 struct ti_sci_msg_rm_udmap_rx_ch_cfg_resp {
1138 struct ti_sci_msg_hdr hdr;
1142 * Configures a Navigator Subsystem UDMAP receive flow
1144 * Configures a Navigator Subsystem UDMAP receive flow's registers.
1145 * Configuration does not include the flow registers which handle size-based
1146 * free descriptor queue routing.
1148 * The flow index must be assigned to the host defined in the TISCI header via
1149 * the RM board configuration resource assignment range list.
1151 * @hdr: Standard TISCI header
1154 * Bitfield defining validity of rx flow configuration parameters. The
1155 * rx flow configuration fields are not valid, and will not be used for flow
1156 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1157 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1158 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1159 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1160 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1161 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1162 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1163 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1164 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1165 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1166 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1167 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1168 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1169 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1170 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1171 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1172 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1173 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1174 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1175 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1177 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1180 * @flow_index: UDMAP receive flow index for non-optional configuration.
1182 * @rx_einfo_present:
1183 * UDMAP receive flow extended packet info present configuration to be
1184 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1186 * @rx_psinfo_present:
1187 * UDMAP receive flow PS words present configuration to be programmed into the
1188 * rx_psinfo_present field of the flow's RFLOW_RFA register.
1190 * @rx_error_handling:
1191 * UDMAP receive flow error handling configuration to be programmed into the
1192 * rx_error_handling field of the flow's RFLOW_RFA register.
1195 * UDMAP receive flow descriptor type configuration to be programmed into the
1196 * rx_desc_type field field of the flow's RFLOW_RFA register.
1199 * UDMAP receive flow start of packet offset configuration to be programmed
1200 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
1201 * section of the TRM for more information on this setting. Valid values for
1202 * this field are 0-255 bytes.
1205 * UDMAP receive flow destination queue configuration to be programmed into the
1206 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
1207 * destination queue must be valid within the Navigator Subsystem and must be
1208 * owned by the host, or a subordinate of the host, requesting allocation and
1209 * configuration of the receive flow.
1212 * UDMAP receive flow source tag high byte constant configuration to be
1213 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1214 * See the UDMAP section of the TRM for more information on this setting.
1217 * UDMAP receive flow source tag low byte constant configuration to be
1218 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1219 * See the UDMAP section of the TRM for more information on this setting.
1222 * UDMAP receive flow destination tag high byte constant configuration to be
1223 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1224 * See the UDMAP section of the TRM for more information on this setting.
1227 * UDMAP receive flow destination tag low byte constant configuration to be
1228 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1229 * See the UDMAP section of the TRM for more information on this setting.
1231 * @rx_src_tag_hi_sel:
1232 * UDMAP receive flow source tag high byte selector configuration to be
1233 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
1234 * the UDMAP section of the TRM for more information on this setting.
1236 * @rx_src_tag_lo_sel:
1237 * UDMAP receive flow source tag low byte selector configuration to be
1238 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
1239 * the UDMAP section of the TRM for more information on this setting.
1241 * @rx_dest_tag_hi_sel:
1242 * UDMAP receive flow destination tag high byte selector configuration to be
1243 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
1244 * the UDMAP section of the TRM for more information on this setting.
1246 * @rx_dest_tag_lo_sel:
1247 * UDMAP receive flow destination tag low byte selector configuration to be
1248 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
1249 * the UDMAP section of the TRM for more information on this setting.
1251 * @rx_fdq0_sz0_qnum:
1252 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1253 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
1254 * UDMAP section of the TRM for more information on this setting. The specified
1255 * free queue must be valid within the Navigator Subsystem and must be owned
1256 * by the host, or a subordinate of the host, requesting allocation and
1257 * configuration of the receive flow.
1260 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1261 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
1262 * UDMAP section of the TRM for more information on this setting. The specified
1263 * free queue must be valid within the Navigator Subsystem and must be owned
1264 * by the host, or a subordinate of the host, requesting allocation and
1265 * configuration of the receive flow.
1268 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1269 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
1270 * UDMAP section of the TRM for more information on this setting. The specified
1271 * free queue must be valid within the Navigator Subsystem and must be owned
1272 * by the host, or a subordinate of the host, requesting allocation and
1273 * configuration of the receive flow.
1276 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1277 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
1278 * UDMAP section of the TRM for more information on this setting. The specified
1279 * free queue must be valid within the Navigator Subsystem and must be owned
1280 * by the host, or a subordinate of the host, requesting allocation and
1281 * configuration of the receive flow.
1284 * UDMAP receive flow PS words location configuration to be programmed into the
1285 * rx_ps_location field of the flow's RFLOW_RFA register.
1287 struct ti_sci_msg_rm_udmap_flow_cfg_req {
1288 struct ti_sci_msg_hdr hdr;
1292 u8 rx_einfo_present;
1293 u8 rx_psinfo_present;
1294 u8 rx_error_handling;
1302 u8 rx_src_tag_hi_sel;
1303 u8 rx_src_tag_lo_sel;
1304 u8 rx_dest_tag_hi_sel;
1305 u8 rx_dest_tag_lo_sel;
1306 u16 rx_fdq0_sz0_qnum;
1314 * Response to configuring a Navigator Subsystem UDMAP receive flow
1316 * @hdr: Standard TISCI header
1318 struct ti_sci_msg_rm_udmap_flow_cfg_resp {
1319 struct ti_sci_msg_hdr hdr;
1322 #endif /* __TI_SCI_H */