drivers/dma/ti/k3-udma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6 #define pr_fmt(fmt) "udma: " fmt
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/io.h>
  11 #include <asm/bitops.h>
  12 #include <malloc.h>
  13 #include <asm/dma-mapping.h>
  14 #include <dm.h>
  15 #include <dm/read.h>
  16 #include <dm/of_access.h>
  17 #include <dma.h>
  18 #include <dma-uclass.h>
  19 #include <linux/delay.h>
  20 #include <dt-bindings/dma/k3-udma.h>
  21 #include <linux/soc/ti/k3-navss-ringacc.h>
  22 #include <linux/soc/ti/cppi5.h>
  23 #include <linux/soc/ti/ti-udma.h>
  24 #include <linux/soc/ti/ti_sci_protocol.h>
  25
  26 #include "k3-udma-hwdef.h"
  27
  28 #if BITS_PER_LONG == 64
  29 #define RINGACC_RING_USE_PROXY  (0)
  30 #else
  31 #define RINGACC_RING_USE_PROXY  (1)
  32 #endif
  33
  34 struct udma_chan;
  35
  36 enum udma_mmr {
  37         MMR_GCFG = 0,
  38         MMR_RCHANRT,
  39         MMR_TCHANRT,
  40         MMR_LAST,
  41 };
  42
  43 static const char * const mmr_names[] = {
  44         "gcfg", "rchanrt", "tchanrt"
  45 };
  46
  47 struct udma_tchan {
  48         void __iomem *reg_rt;
  49
  50         int id;
  51         struct k3_nav_ring *t_ring; /* Transmit ring */
  52         struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
  53 };
  54
  55 struct udma_rchan {
  56         void __iomem *reg_rt;
  57
  58         int id;
  59         struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
  60         struct k3_nav_ring *r_ring; /* Receive ring*/
  61 };
  62
  63 struct udma_rflow {
  64         int id;
  65 };
  66
  67 struct udma_dev {
  68         struct device *dev;
  69         void __iomem *mmrs[MMR_LAST];
  70
  71         struct k3_nav_ringacc *ringacc;
  72
  73         u32 features;
  74
  75         int tchan_cnt;
  76         int echan_cnt;
  77         int rchan_cnt;
  78         int rflow_cnt;
  79         unsigned long *tchan_map;
  80         unsigned long *rchan_map;
  81         unsigned long *rflow_map;
  82
  83         struct udma_tchan *tchans;
  84         struct udma_rchan *rchans;
  85         struct udma_rflow *rflows;
  86
  87         struct udma_chan *channels;
  88         u32 psil_base;
  89
  90         u32 ch_count;
  91         const struct ti_sci_handle *tisci;
  92         const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
  93         const struct ti_sci_rm_psil_ops *tisci_psil_ops;
  94         u32  tisci_dev_id;
  95         u32  tisci_navss_dev_id;
  96         bool is_coherent;
  97 };
  98
  99 struct udma_chan {
 100         struct udma_dev *ud;
 101         char name[20];
 102
 103         struct udma_tchan *tchan;
 104         struct udma_rchan *rchan;
 105         struct udma_rflow *rflow;
 106
 107         u32 bcnt; /* number of bytes completed since the start of the channel */
 108
 109         bool pkt_mode; /* TR or packet */
 110         bool needs_epib; /* EPIB is needed for the communication or not */
 111         u32 psd_size; /* size of Protocol Specific Data */
 112         u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
 113         int slave_thread_id;
 114         u32 src_thread;
 115         u32 dst_thread;
 116         u32 static_tr_type;
 117
 118         u32 id;
 119         enum dma_direction dir;
 120
 121         struct cppi5_host_desc_t *desc_tx;
 122         u32 hdesc_size;
 123         bool in_use;
 124         void    *desc_rx;
 125         u32     num_rx_bufs;
 126         u32     desc_rx_cur;
 127
 128 };
 129
 130 #define UDMA_CH_1000(ch)                (ch * 0x1000)
 131 #define UDMA_CH_100(ch)                 (ch * 0x100)
 132 #define UDMA_CH_40(ch)                  (ch * 0x40)
 133
 134 #ifdef PKTBUFSRX
 135 #define UDMA_RX_DESC_NUM PKTBUFSRX
 136 #else
 137 #define UDMA_RX_DESC_NUM 4
 138 #endif
 139
 140 /* Generic register access functions */
 141 static inline u32 udma_read(void __iomem *base, int reg)
 142 {
 143         u32 v;
 144
 145         v = __raw_readl(base + reg);
 146         pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, base + reg);
 147         return v;
 148 }
 149
 150 static inline void udma_write(void __iomem *base, int reg, u32 val)
 151 {
 152         pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val, base + reg);
 153         __raw_writel(val, base + reg);
 154 }
 155
 156 static inline void udma_update_bits(void __iomem *base, int reg,
 157                                     u32 mask, u32 val)
 158 {
 159         u32 tmp, orig;
 160
 161         orig = udma_read(base, reg);
 162         tmp = orig & ~mask;
 163         tmp |= (val & mask);
 164
 165         if (tmp != orig)
 166                 udma_write(base, reg, tmp);
 167 }
 168
 169 /* TCHANRT */
 170 static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
 171 {
 172         if (!tchan)
 173                 return 0;
 174         return udma_read(tchan->reg_rt, reg);
 175 }
 176
 177 static inline void udma_tchanrt_write(struct udma_tchan *tchan,
 178                                       int reg, u32 val)
 179 {
 180         if (!tchan)
 181                 return;
 182         udma_write(tchan->reg_rt, reg, val);
 183 }
 184
 185 /* RCHANRT */
 186 static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
 187 {
 188         if (!rchan)
 189                 return 0;
 190         return udma_read(rchan->reg_rt, reg);
 191 }
 192
 193 static inline void udma_rchanrt_write(struct udma_rchan *rchan,
 194                                       int reg, u32 val)
 195 {
 196         if (!rchan)
 197                 return;
 198         udma_write(rchan->reg_rt, reg, val);
 199 }
 200
 201 static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
 202                                        u32 dst_thread)
 203 {
 204         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 205         return ud->tisci_psil_ops->pair(ud->tisci,
 206                                         ud->tisci_navss_dev_id,
 207                                         src_thread, dst_thread);
 208 }
 209
 210 static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
 211                                          u32 dst_thread)
 212 {
 213         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 214         return ud->tisci_psil_ops->unpair(ud->tisci,
 215                                           ud->tisci_navss_dev_id,
 216                                           src_thread, dst_thread);
 217 }
 218
 219 static inline char *udma_get_dir_text(enum dma_direction dir)
 220 {
 221         switch (dir) {
 222         case DMA_DEV_TO_MEM:
 223                 return "DEV_TO_MEM";
 224         case DMA_MEM_TO_DEV:
 225                 return "MEM_TO_DEV";
 226         case DMA_MEM_TO_MEM:
 227                 return "MEM_TO_MEM";
 228         case DMA_DEV_TO_DEV:
 229                 return "DEV_TO_DEV";
 230         default:
 231                 break;
 232         }
 233
 234         return "invalid";
 235 }
 236
 237 static inline bool udma_is_chan_running(struct udma_chan *uc)
 238 {
 239         u32 trt_ctl = 0;
 240         u32 rrt_ctl = 0;
 241
 242         switch (uc->dir) {
 243         case DMA_DEV_TO_MEM:
 244                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 245                 pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
 246                          __func__, rrt_ctl,
 247                          udma_rchanrt_read(uc->rchan,
 248                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 249                 break;
 250         case DMA_MEM_TO_DEV:
 251                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 252                 pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
 253                          __func__, trt_ctl,
 254                          udma_tchanrt_read(uc->tchan,
 255                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 256                 break;
 257         case DMA_MEM_TO_MEM:
 258                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 259                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 260                 break;
 261         default:
 262                 break;
 263         }
 264
 265         if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
 266                 return true;
 267
 268         return false;
 269 }
 270
 271 static int udma_is_coherent(struct udma_chan *uc)
 272 {
 273         return uc->ud->is_coherent;
 274 }
 275
 276 static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
 277 {
 278         struct k3_nav_ring *ring = NULL;
 279         int ret = -ENOENT;
 280
 281         switch (uc->dir) {
 282         case DMA_DEV_TO_MEM:
 283                 ring = uc->rchan->r_ring;
 284                 break;
 285         case DMA_MEM_TO_DEV:
 286                 ring = uc->tchan->tc_ring;
 287                 break;
 288         case DMA_MEM_TO_MEM:
 289                 ring = uc->tchan->tc_ring;
 290                 break;
 291         default:
 292                 break;
 293         }
 294
 295         if (ring && k3_nav_ringacc_ring_get_occ(ring))
 296                 ret = k3_nav_ringacc_ring_pop(ring, addr);
 297
 298         return ret;
 299 }
 300
 301 static void udma_reset_rings(struct udma_chan *uc)
 302 {
 303         struct k3_nav_ring *ring1 = NULL;
 304         struct k3_nav_ring *ring2 = NULL;
 305
 306         switch (uc->dir) {
 307         case DMA_DEV_TO_MEM:
 308                 ring1 = uc->rchan->fd_ring;
 309                 ring2 = uc->rchan->r_ring;
 310                 break;
 311         case DMA_MEM_TO_DEV:
 312                 ring1 = uc->tchan->t_ring;
 313                 ring2 = uc->tchan->tc_ring;
 314                 break;
 315         case DMA_MEM_TO_MEM:
 316                 ring1 = uc->tchan->t_ring;
 317                 ring2 = uc->tchan->tc_ring;
 318                 break;
 319         default:
 320                 break;
 321         }
 322
 323         if (ring1)
 324                 k3_nav_ringacc_ring_reset_dma(ring1, 0);
 325         if (ring2)
 326                 k3_nav_ringacc_ring_reset(ring2);
 327 }
 328
 329 static void udma_reset_counters(struct udma_chan *uc)
 330 {
 331         u32 val;
 332
 333         if (uc->tchan) {
 334                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
 335                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
 336
 337                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
 338                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
 339
 340                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
 341                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
 342
 343                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
 344                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
 345         }
 346
 347         if (uc->rchan) {
 348                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
 349                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
 350
 351                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
 352                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
 353
 354                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
 355                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
 356
 357                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
 358                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
 359         }
 360
 361         uc->bcnt = 0;
 362 }
 363
 364 static inline int udma_stop_hard(struct udma_chan *uc)
 365 {
 366         pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
 367
 368         switch (uc->dir) {
 369         case DMA_DEV_TO_MEM:
 370                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
 371                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 372                 break;
 373         case DMA_MEM_TO_DEV:
 374                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 375                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
 376                 break;
 377         case DMA_MEM_TO_MEM:
 378                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 379                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 380                 break;
 381         default:
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int udma_start(struct udma_chan *uc)
 389 {
 390         /* Channel is already running, no need to proceed further */
 391         if (udma_is_chan_running(uc))
 392                 goto out;
 393
 394         pr_debug("%s: chan:%d dir:%s (static_tr_type: %d)\n",
 395                  __func__, uc->id, udma_get_dir_text(uc->dir),
 396                  uc->static_tr_type);
 397
 398         /* Make sure that we clear the teardown bit, if it is set */
 399         udma_stop_hard(uc);
 400
 401         /* Reset all counters */
 402         udma_reset_counters(uc);
 403
 404         switch (uc->dir) {
 405         case DMA_DEV_TO_MEM:
 406                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 407                                    UDMA_CHAN_RT_CTL_EN);
 408
 409                 /* Enable remote */
 410                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 411                                    UDMA_PEER_RT_EN_ENABLE);
 412
 413                 pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 414                          __func__,
 415                          udma_rchanrt_read(uc->rchan,
 416                                            UDMA_RCHAN_RT_CTL_REG),
 417                          udma_rchanrt_read(uc->rchan,
 418                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 419                 break;
 420         case DMA_MEM_TO_DEV:
 421                 /* Enable remote */
 422                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
 423                                    UDMA_PEER_RT_EN_ENABLE);
 424
 425                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 426                                    UDMA_CHAN_RT_CTL_EN);
 427
 428                 pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 429                          __func__,
 430                          udma_rchanrt_read(uc->rchan,
 431                                            UDMA_TCHAN_RT_CTL_REG),
 432                          udma_rchanrt_read(uc->rchan,
 433                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 434                 break;
 435         case DMA_MEM_TO_MEM:
 436                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 437                                    UDMA_CHAN_RT_CTL_EN);
 438                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 439                                    UDMA_CHAN_RT_CTL_EN);
 440
 441                 break;
 442         default:
 443                 return -EINVAL;
 444         }
 445
 446         pr_debug("%s: DONE chan:%d\n", __func__, uc->id);
 447 out:
 448         return 0;
 449 }
 450
 451 static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
 452 {
 453         int i = 0;
 454         u32 val;
 455
 456         udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 457                            UDMA_CHAN_RT_CTL_EN |
 458                            UDMA_CHAN_RT_CTL_TDOWN);
 459
 460         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 461
 462         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 463                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 464                 udelay(1);
 465                 if (i > 1000) {
 466                         printf(" %s TIMEOUT !\n", __func__);
 467                         break;
 468                 }
 469                 i++;
 470         }
 471
 472         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
 473         if (val & UDMA_PEER_RT_EN_ENABLE)
 474                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 475 }
 476
 477 static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
 478 {
 479         int i = 0;
 480         u32 val;
 481
 482         udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 483                            UDMA_PEER_RT_EN_ENABLE |
 484                            UDMA_PEER_RT_EN_TEARDOWN);
 485
 486         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 487
 488         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 489                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 490                 udelay(1);
 491                 if (i > 1000) {
 492                         printf("%s TIMEOUT !\n", __func__);
 493                         break;
 494                 }
 495                 i++;
 496         }
 497
 498         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
 499         if (val & UDMA_PEER_RT_EN_ENABLE)
 500                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 501 }
 502
 503 static inline int udma_stop(struct udma_chan *uc)
 504 {
 505         pr_debug("%s: chan:%d dir:%s\n",
 506                  __func__, uc->id, udma_get_dir_text(uc->dir));
 507
 508         udma_reset_counters(uc);
 509         switch (uc->dir) {
 510         case DMA_DEV_TO_MEM:
 511                 udma_stop_dev2mem(uc, true);
 512                 break;
 513         case DMA_MEM_TO_DEV:
 514                 udma_stop_mem2dev(uc, true);
 515                 break;
 516         case DMA_MEM_TO_MEM:
 517                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 518                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 519                 break;
 520         default:
 521                 return -EINVAL;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
 528 {
 529         int i = 1;
 530
 531         while (udma_pop_from_ring(uc, paddr)) {
 532                 udelay(1);
 533                 if (!(i % 1000000))
 534                         printf(".");
 535                 i++;
 536         }
 537 }
 538
 539 #define UDMA_RESERVE_RESOURCE(res)                                      \
 540 static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,     \
 541                                                int id)                  \
 542 {                                                                       \
 543         if (id >= 0) {                                                  \
 544                 if (test_bit(id, ud->res##_map)) {                      \
 545                         dev_err(ud->dev, "res##%d is in use\n", id);    \
 546                         return ERR_PTR(-ENOENT);                        \
 547                 }                                                       \
 548         } else {                                                        \
 549                 id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
 550                 if (id == ud->res##_cnt) {                              \
 551                         return ERR_PTR(-ENOENT);                        \
 552                 }                                                       \
 553         }                                                               \
 554                                                                         \
 555         __set_bit(id, ud->res##_map);                                   \
 556         return &ud->res##s[id];                                         \
 557 }
 558
 559 UDMA_RESERVE_RESOURCE(tchan);
 560 UDMA_RESERVE_RESOURCE(rchan);
 561 UDMA_RESERVE_RESOURCE(rflow);
 562
 563 static int udma_get_tchan(struct udma_chan *uc)
 564 {
 565         struct udma_dev *ud = uc->ud;
 566
 567         if (uc->tchan) {
 568                 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
 569                         uc->id, uc->tchan->id);
 570                 return 0;
 571         }
 572
 573         uc->tchan = __udma_reserve_tchan(ud, -1);
 574         if (IS_ERR(uc->tchan))
 575                 return PTR_ERR(uc->tchan);
 576
 577         pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
 578
 579         return 0;
 580 }
 581
 582 static int udma_get_rchan(struct udma_chan *uc)
 583 {
 584         struct udma_dev *ud = uc->ud;
 585
 586         if (uc->rchan) {
 587                 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
 588                         uc->id, uc->rchan->id);
 589                 return 0;
 590         }
 591
 592         uc->rchan = __udma_reserve_rchan(ud, -1);
 593         if (IS_ERR(uc->rchan))
 594                 return PTR_ERR(uc->rchan);
 595
 596         pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
 597
 598         return 0;
 599 }
 600
 601 static int udma_get_chan_pair(struct udma_chan *uc)
 602 {
 603         struct udma_dev *ud = uc->ud;
 604         int chan_id, end;
 605
 606         if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
 607                 dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
 608                          uc->id, uc->tchan->id);
 609                 return 0;
 610         }
 611
 612         if (uc->tchan) {
 613                 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
 614                         uc->id, uc->tchan->id);
 615                 return -EBUSY;
 616         } else if (uc->rchan) {
 617                 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
 618                         uc->id, uc->rchan->id);
 619                 return -EBUSY;
 620         }
 621
 622         /* Can be optimized, but let's have it like this for now */
 623         end = min(ud->tchan_cnt, ud->rchan_cnt);
 624         for (chan_id = 0; chan_id < end; chan_id++) {
 625                 if (!test_bit(chan_id, ud->tchan_map) &&
 626                     !test_bit(chan_id, ud->rchan_map))
 627                         break;
 628         }
 629
 630         if (chan_id == end)
 631                 return -ENOENT;
 632
 633         __set_bit(chan_id, ud->tchan_map);
 634         __set_bit(chan_id, ud->rchan_map);
 635         uc->tchan = &ud->tchans[chan_id];
 636         uc->rchan = &ud->rchans[chan_id];
 637
 638         pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
 639
 640         return 0;
 641 }
 642
 643 static int udma_get_rflow(struct udma_chan *uc, int flow_id)
 644 {
 645         struct udma_dev *ud = uc->ud;
 646
 647         if (uc->rflow) {
 648                 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
 649                         uc->id, uc->rflow->id);
 650                 return 0;
 651         }
 652
 653         if (!uc->rchan)
 654                 dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
 655
 656         uc->rflow = __udma_reserve_rflow(ud, flow_id);
 657         if (IS_ERR(uc->rflow))
 658                 return PTR_ERR(uc->rflow);
 659
 660         pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
 661         return 0;
 662 }
 663
 664 static void udma_put_rchan(struct udma_chan *uc)
 665 {
 666         struct udma_dev *ud = uc->ud;
 667
 668         if (uc->rchan) {
 669                 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
 670                         uc->rchan->id);
 671                 __clear_bit(uc->rchan->id, ud->rchan_map);
 672                 uc->rchan = NULL;
 673         }
 674 }
 675
 676 static void udma_put_tchan(struct udma_chan *uc)
 677 {
 678         struct udma_dev *ud = uc->ud;
 679
 680         if (uc->tchan) {
 681                 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
 682                         uc->tchan->id);
 683                 __clear_bit(uc->tchan->id, ud->tchan_map);
 684                 uc->tchan = NULL;
 685         }
 686 }
 687
 688 static void udma_put_rflow(struct udma_chan *uc)
 689 {
 690         struct udma_dev *ud = uc->ud;
 691
 692         if (uc->rflow) {
 693                 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
 694                         uc->rflow->id);
 695                 __clear_bit(uc->rflow->id, ud->rflow_map);
 696                 uc->rflow = NULL;
 697         }
 698 }
 699
 700 static void udma_free_tx_resources(struct udma_chan *uc)
 701 {
 702         if (!uc->tchan)
 703                 return;
 704
 705         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 706         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 707         uc->tchan->t_ring = NULL;
 708         uc->tchan->tc_ring = NULL;
 709
 710         udma_put_tchan(uc);
 711 }
 712
 713 static int udma_alloc_tx_resources(struct udma_chan *uc)
 714 {
 715         struct k3_nav_ring_cfg ring_cfg;
 716         struct udma_dev *ud = uc->ud;
 717         int ret;
 718
 719         ret = udma_get_tchan(uc);
 720         if (ret)
 721                 return ret;
 722
 723         uc->tchan->t_ring = k3_nav_ringacc_request_ring(
 724                                 ud->ringacc, uc->tchan->id,
 725                                 RINGACC_RING_USE_PROXY);
 726         if (!uc->tchan->t_ring) {
 727                 ret = -EBUSY;
 728                 goto err_tx_ring;
 729         }
 730
 731         uc->tchan->tc_ring = k3_nav_ringacc_request_ring(
 732                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 733         if (!uc->tchan->tc_ring) {
 734                 ret = -EBUSY;
 735                 goto err_txc_ring;
 736         }
 737
 738         memset(&ring_cfg, 0, sizeof(ring_cfg));
 739         ring_cfg.size = 16;
 740         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 741         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
 742
 743         ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
 744         ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
 745
 746         if (ret)
 747                 goto err_ringcfg;
 748
 749         return 0;
 750
 751 err_ringcfg:
 752         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 753         uc->tchan->tc_ring = NULL;
 754 err_txc_ring:
 755         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 756         uc->tchan->t_ring = NULL;
 757 err_tx_ring:
 758         udma_put_tchan(uc);
 759
 760         return ret;
 761 }
 762
 763 static void udma_free_rx_resources(struct udma_chan *uc)
 764 {
 765         if (!uc->rchan)
 766                 return;
 767
 768         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 769         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 770         uc->rchan->fd_ring = NULL;
 771         uc->rchan->r_ring = NULL;
 772
 773         udma_put_rflow(uc);
 774         udma_put_rchan(uc);
 775 }
 776
 777 static int udma_alloc_rx_resources(struct udma_chan *uc)
 778 {
 779         struct k3_nav_ring_cfg ring_cfg;
 780         struct udma_dev *ud = uc->ud;
 781         int fd_ring_id;
 782         int ret;
 783
 784         ret = udma_get_rchan(uc);
 785         if (ret)
 786                 return ret;
 787
 788         /* For MEM_TO_MEM we don't need rflow or rings */
 789         if (uc->dir == DMA_MEM_TO_MEM)
 790                 return 0;
 791
 792         ret = udma_get_rflow(uc, uc->rchan->id);
 793         if (ret) {
 794                 ret = -EBUSY;
 795                 goto err_rflow;
 796         }
 797
 798         fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
 799
 800         uc->rchan->fd_ring = k3_nav_ringacc_request_ring(
 801                                 ud->ringacc, fd_ring_id,
 802                                 RINGACC_RING_USE_PROXY);
 803         if (!uc->rchan->fd_ring) {
 804                 ret = -EBUSY;
 805                 goto err_rx_ring;
 806         }
 807
 808         uc->rchan->r_ring = k3_nav_ringacc_request_ring(
 809                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 810         if (!uc->rchan->r_ring) {
 811                 ret = -EBUSY;
 812                 goto err_rxc_ring;
 813         }
 814
 815         memset(&ring_cfg, 0, sizeof(ring_cfg));
 816         ring_cfg.size = 16;
 817         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 818         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
 819
 820         ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg);
 821         ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
 822
 823         if (ret)
 824                 goto err_ringcfg;
 825
 826         return 0;
 827
 828 err_ringcfg:
 829         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 830         uc->rchan->r_ring = NULL;
 831 err_rxc_ring:
 832         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 833         uc->rchan->fd_ring = NULL;
 834 err_rx_ring:
 835         udma_put_rflow(uc);
 836 err_rflow:
 837         udma_put_rchan(uc);
 838
 839         return ret;
 840 }
 841
 842 static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
 843 {
 844         struct udma_dev *ud = uc->ud;
 845         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 846         struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
 847         u32 mode;
 848         int ret;
 849
 850         if (uc->pkt_mode)
 851                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 852         else
 853                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 854
 855         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
 856                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 857                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
 858         req.nav_id = ud->tisci_dev_id;
 859         req.index = uc->tchan->id;
 860         req.tx_chan_type = mode;
 861         if (uc->dir == DMA_MEM_TO_MEM)
 862                 req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 863         else
 864                 req.tx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 865                                                           uc->psd_size,
 866                                                           0) >> 2;
 867         req.txcq_qnum = tc_ring;
 868
 869         ret = ud->tisci_udmap_ops->tx_ch_cfg(ud->tisci, &req);
 870         if (ret)
 871                 dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
 872
 873         return ret;
 874 }
 875
 876 static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 877 {
 878         struct udma_dev *ud = uc->ud;
 879         int fd_ring = k3_nav_ringacc_get_ring_id(uc->rchan->fd_ring);
 880         int rx_ring = k3_nav_ringacc_get_ring_id(uc->rchan->r_ring);
 881         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 882         struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
 883         struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
 884         u32 mode;
 885         int ret;
 886
 887         if (uc->pkt_mode)
 888                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 889         else
 890                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 891
 892         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 893                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
 894                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
 895         req.nav_id = ud->tisci_dev_id;
 896         req.index = uc->rchan->id;
 897         req.rx_chan_type = mode;
 898         if (uc->dir == DMA_MEM_TO_MEM) {
 899                 req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 900                 req.rxcq_qnum = tc_ring;
 901         } else {
 902                 req.rx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 903                                                           uc->psd_size,
 904                                                           0) >> 2;
 905                 req.rxcq_qnum = rx_ring;
 906         }
 907         if (uc->rflow->id != uc->rchan->id && uc->dir != DMA_MEM_TO_MEM) {
 908                 req.flowid_start = uc->rflow->id;
 909                 req.flowid_cnt = 1;
 910                 req.valid_params |=
 911                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
 912                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
 913         }
 914
 915         ret = ud->tisci_udmap_ops->rx_ch_cfg(ud->tisci, &req);
 916         if (ret) {
 917                 dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
 918                         uc->rchan->id, ret);
 919                 return ret;
 920         }
 921         if (uc->dir == DMA_MEM_TO_MEM)
 922                 return ret;
 923
 924         flow_req.valid_params =
 925                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
 926                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
 927                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
 928                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
 929                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
 930                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
 931                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
 932                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
 933                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
 934                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
 935                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
 936                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
 937                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
 938                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
 939
 940         flow_req.nav_id = ud->tisci_dev_id;
 941         flow_req.flow_index = uc->rflow->id;
 942
 943         if (uc->needs_epib)
 944                 flow_req.rx_einfo_present = 1;
 945         else
 946                 flow_req.rx_einfo_present = 0;
 947
 948         if (uc->psd_size)
 949                 flow_req.rx_psinfo_present = 1;
 950         else
 951                 flow_req.rx_psinfo_present = 0;
 952
 953         flow_req.rx_error_handling = 0;
 954         flow_req.rx_desc_type = 0;
 955         flow_req.rx_dest_qnum = rx_ring;
 956         flow_req.rx_src_tag_hi_sel = 2;
 957         flow_req.rx_src_tag_lo_sel = 4;
 958         flow_req.rx_dest_tag_hi_sel = 5;
 959         flow_req.rx_dest_tag_lo_sel = 4;
 960         flow_req.rx_fdq0_sz0_qnum = fd_ring;
 961         flow_req.rx_fdq1_qnum = fd_ring;
 962         flow_req.rx_fdq2_qnum = fd_ring;
 963         flow_req.rx_fdq3_qnum = fd_ring;
 964         flow_req.rx_ps_location = 0;
 965
 966         ret = ud->tisci_udmap_ops->rx_flow_cfg(ud->tisci, &flow_req);
 967         if (ret)
 968                 dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
 969                         uc->rchan->id, uc->rflow->id, ret);
 970
 971         return ret;
 972 }
 973
 974 static int udma_alloc_chan_resources(struct udma_chan *uc)
 975 {
 976         struct udma_dev *ud = uc->ud;
 977         int ret;
 978
 979         pr_debug("%s: chan:%d as %s\n",
 980                  __func__, uc->id, udma_get_dir_text(uc->dir));
 981
 982         switch (uc->dir) {
 983         case DMA_MEM_TO_MEM:
 984                 /* Non synchronized - mem to mem type of transfer */
 985                 ret = udma_get_chan_pair(uc);
 986                 if (ret)
 987                         return ret;
 988
 989                 ret = udma_alloc_tx_resources(uc);
 990                 if (ret)
 991                         goto err_free_res;
 992
 993                 ret = udma_alloc_rx_resources(uc);
 994                 if (ret)
 995                         goto err_free_res;
 996
 997                 uc->src_thread = ud->psil_base + uc->tchan->id;
 998                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
 999                 break;
1000         case DMA_MEM_TO_DEV:
1001                 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
1002                 ret = udma_alloc_tx_resources(uc);
1003                 if (ret)
1004                         goto err_free_res;
1005
1006                 uc->src_thread = ud->psil_base + uc->tchan->id;
1007                 uc->dst_thread = uc->slave_thread_id;
1008                 if (!(uc->dst_thread & 0x8000))
1009                         uc->dst_thread |= 0x8000;
1010
1011                 break;
1012         case DMA_DEV_TO_MEM:
1013                 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
1014                 ret = udma_alloc_rx_resources(uc);
1015                 if (ret)
1016                         goto err_free_res;
1017
1018                 uc->src_thread = uc->slave_thread_id;
1019                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
1020
1021                 break;
1022         default:
1023                 /* Can not happen */
1024                 pr_debug("%s: chan:%d invalid direction (%u)\n",
1025                          __func__, uc->id, uc->dir);
1026                 return -EINVAL;
1027         }
1028
1029         /* We have channel indexes and rings */
1030         if (uc->dir == DMA_MEM_TO_MEM) {
1031                 ret = udma_alloc_tchan_sci_req(uc);
1032                 if (ret)
1033                         goto err_free_res;
1034
1035                 ret = udma_alloc_rchan_sci_req(uc);
1036                 if (ret)
1037                         goto err_free_res;
1038         } else {
1039                 /* Slave transfer */
1040                 if (uc->dir == DMA_MEM_TO_DEV) {
1041                         ret = udma_alloc_tchan_sci_req(uc);
1042                         if (ret)
1043                                 goto err_free_res;
1044                 } else {
1045                         ret = udma_alloc_rchan_sci_req(uc);
1046                         if (ret)
1047                                 goto err_free_res;
1048                 }
1049         }
1050
1051         if (udma_is_chan_running(uc)) {
1052                 dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
1053                 udma_stop(uc);
1054                 if (udma_is_chan_running(uc)) {
1055                         dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
1056                         goto err_free_res;
1057                 }
1058         }
1059
1060         /* PSI-L pairing */
1061         ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
1062         if (ret) {
1063                 dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
1064                 goto err_free_res;
1065         }
1066
1067         return 0;
1068
1069 err_free_res:
1070         udma_free_tx_resources(uc);
1071         udma_free_rx_resources(uc);
1072         uc->slave_thread_id = -1;
1073         return ret;
1074 }
1075
1076 static void udma_free_chan_resources(struct udma_chan *uc)
1077 {
1078         /* Some configuration to UDMA-P channel: disable, reset, whatever */
1079
1080         /* Release PSI-L pairing */
1081         udma_navss_psil_unpair(uc->ud, uc->src_thread, uc->dst_thread);
1082
1083         /* Reset the rings for a new start */
1084         udma_reset_rings(uc);
1085         udma_free_tx_resources(uc);
1086         udma_free_rx_resources(uc);
1087
1088         uc->slave_thread_id = -1;
1089         uc->dir = DMA_MEM_TO_MEM;
1090 }
1091
1092 static int udma_get_mmrs(struct udevice *dev)
1093 {
1094         struct udma_dev *ud = dev_get_priv(dev);
1095         int i;
1096
1097         for (i = 0; i < MMR_LAST; i++) {
1098                 ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
1099                                 mmr_names[i]);
1100                 if (!ud->mmrs[i])
1101                         return -EINVAL;
1102         }
1103
1104         return 0;
1105 }
1106
1107 #define UDMA_MAX_CHANNELS       192
1108
1109 static int udma_probe(struct udevice *dev)
1110 {
1111         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
1112         struct udma_dev *ud = dev_get_priv(dev);
1113         int i, ret;
1114         u32 cap2, cap3;
1115         struct udevice *tmp;
1116         struct udevice *tisci_dev = NULL;
1117
1118         ret = udma_get_mmrs(dev);
1119         if (ret)
1120                 return ret;
1121
1122         ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
1123                                            "ti,ringacc", &tmp);
1124         ud->ringacc = dev_get_priv(tmp);
1125         if (IS_ERR(ud->ringacc))
1126                 return PTR_ERR(ud->ringacc);
1127
1128         ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0);
1129         if (!ud->psil_base) {
1130                 dev_info(dev,
1131                          "Missing ti,psil-base property, using %d.\n", ret);
1132                 return -EINVAL;
1133         }
1134
1135         ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
1136         if (ret) {
1137                 debug("TISCI RA RM get failed (%d)\n", ret);
1138                 ud->tisci = NULL;
1139                 return 0;
1140         }
1141         ud->tisci = (struct ti_sci_handle *)
1142                          (ti_sci_get_handle_from_sysfw(tisci_dev));
1143
1144         ret = dev_read_u32_default(dev, "ti,sci", 0);
1145         if (!ret) {
1146                 dev_err(dev, "TISCI RA RM disabled\n");
1147                 ud->tisci = NULL;
1148         }
1149
1150         if (ud->tisci) {
1151                 ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
1152
1153                 ud->tisci_dev_id = -1;
1154                 ret = dev_read_u32(dev, "ti,sci-dev-id", &ud->tisci_dev_id);
1155                 if (ret) {
1156                         dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
1157                         return ret;
1158                 }
1159
1160                 ud->tisci_navss_dev_id = -1;
1161                 ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
1162                                       &ud->tisci_navss_dev_id);
1163                 if (ret) {
1164                         dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
1165                         return ret;
1166                 }
1167
1168                 ud->tisci_udmap_ops = &ud->tisci->ops.rm_udmap_ops;
1169                 ud->tisci_psil_ops = &ud->tisci->ops.rm_psil_ops;
1170         }
1171
1172         ud->is_coherent = dev_read_bool(dev, "dma-coherent");
1173
1174         cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
1175         cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
1176
1177         ud->rflow_cnt = cap3 & 0x3fff;
1178         ud->tchan_cnt = cap2 & 0x1ff;
1179         ud->echan_cnt = (cap2 >> 9) & 0x1ff;
1180         ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
1181         ud->ch_count  = ud->tchan_cnt + ud->rchan_cnt;
1182
1183         dev_info(dev,
1184                  "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
1185                  ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
1186                  ud->tisci_dev_id);
1187         dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
1188
1189         ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels),
1190                                     GFP_KERNEL);
1191         ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt),
1192                                      sizeof(unsigned long), GFP_KERNEL);
1193         ud->tchans = devm_kcalloc(dev, ud->tchan_cnt,
1194                                   sizeof(*ud->tchans), GFP_KERNEL);
1195         ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
1196                                      sizeof(unsigned long), GFP_KERNEL);
1197         ud->rchans = devm_kcalloc(dev, ud->rchan_cnt,
1198                                   sizeof(*ud->rchans), GFP_KERNEL);
1199         ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
1200                                      sizeof(unsigned long), GFP_KERNEL);
1201         ud->rflows = devm_kcalloc(dev, ud->rflow_cnt,
1202                                   sizeof(*ud->rflows), GFP_KERNEL);
1203
1204         if (!ud->channels || !ud->tchan_map || !ud->rchan_map ||
1205             !ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows)
1206                 return -ENOMEM;
1207
1208         for (i = 0; i < ud->tchan_cnt; i++) {
1209                 struct udma_tchan *tchan = &ud->tchans[i];
1210
1211                 tchan->id = i;
1212                 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
1213         }
1214
1215         for (i = 0; i < ud->rchan_cnt; i++) {
1216                 struct udma_rchan *rchan = &ud->rchans[i];
1217
1218                 rchan->id = i;
1219                 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
1220         }
1221
1222         for (i = 0; i < ud->rflow_cnt; i++) {
1223                 struct udma_rflow *rflow = &ud->rflows[i];
1224
1225                 rflow->id = i;
1226         }
1227
1228         for (i = 0; i < ud->ch_count; i++) {
1229                 struct udma_chan *uc = &ud->channels[i];
1230
1231                 uc->ud = ud;
1232                 uc->id = i;
1233                 uc->slave_thread_id = -1;
1234                 uc->tchan = NULL;
1235                 uc->rchan = NULL;
1236                 uc->dir = DMA_MEM_TO_MEM;
1237                 sprintf(uc->name, "UDMA chan%d\n", i);
1238                 if (!i)
1239                         uc->in_use = true;
1240         }
1241
1242         pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1243                  udma_read(ud->mmrs[MMR_GCFG], 0),
1244                  udma_read(ud->mmrs[MMR_GCFG], 0x20),
1245                  udma_read(ud->mmrs[MMR_GCFG], 0x24),
1246                  udma_read(ud->mmrs[MMR_GCFG], 0x28),
1247                  udma_read(ud->mmrs[MMR_GCFG], 0x2c));
1248
1249         uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
1250
1251         return ret;
1252 }
1253
1254 static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
1255                                  dma_addr_t src, size_t len)
1256 {
1257         u32 tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1258         struct cppi5_tr_type15_t *tr_req;
1259         int num_tr;
1260         size_t tr_size = sizeof(struct cppi5_tr_type15_t);
1261         u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
1262         unsigned long dummy;
1263         void *tr_desc;
1264         size_t desc_size;
1265
1266         if (len < SZ_64K) {
1267                 num_tr = 1;
1268                 tr0_cnt0 = len;
1269                 tr0_cnt1 = 1;
1270         } else {
1271                 unsigned long align_to = __ffs(src | dest);
1272
1273                 if (align_to > 3)
1274                         align_to = 3;
1275                 /*
1276                  * Keep simple: tr0: SZ_64K-alignment blocks,
1277                  *              tr1: the remaining
1278                  */
1279                 num_tr = 2;
1280                 tr0_cnt0 = (SZ_64K - BIT(align_to));
1281                 if (len / tr0_cnt0 >= SZ_64K) {
1282                         dev_err(uc->ud->dev, "size %zu is not supported\n",
1283                                 len);
1284                         return NULL;
1285                 }
1286
1287                 tr0_cnt1 = len / tr0_cnt0;
1288                 tr1_cnt0 = len % tr0_cnt0;
1289         }
1290
1291         desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
1292         tr_desc = dma_alloc_coherent(desc_size, &dummy);
1293         if (!tr_desc)
1294                 return NULL;
1295         memset(tr_desc, 0, desc_size);
1296
1297         cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
1298         cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
1299         cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
1300
1301         tr_req = tr_desc + tr_size;
1302
1303         cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
1304                       CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
1305         cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
1306
1307         tr_req[0].addr = src;
1308         tr_req[0].icnt0 = tr0_cnt0;
1309         tr_req[0].icnt1 = tr0_cnt1;
1310         tr_req[0].icnt2 = 1;
1311         tr_req[0].icnt3 = 1;
1312         tr_req[0].dim1 = tr0_cnt0;
1313
1314         tr_req[0].daddr = dest;
1315         tr_req[0].dicnt0 = tr0_cnt0;
1316         tr_req[0].dicnt1 = tr0_cnt1;
1317         tr_req[0].dicnt2 = 1;
1318         tr_req[0].dicnt3 = 1;
1319         tr_req[0].ddim1 = tr0_cnt0;
1320
1321         if (num_tr == 2) {
1322                 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
1323                               CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
1324                 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
1325
1326                 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
1327                 tr_req[1].icnt0 = tr1_cnt0;
1328                 tr_req[1].icnt1 = 1;
1329                 tr_req[1].icnt2 = 1;
1330                 tr_req[1].icnt3 = 1;
1331
1332                 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
1333                 tr_req[1].dicnt0 = tr1_cnt0;
1334                 tr_req[1].dicnt1 = 1;
1335                 tr_req[1].dicnt2 = 1;
1336                 tr_req[1].dicnt3 = 1;
1337         }
1338
1339         cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
1340
1341         if (!udma_is_coherent(uc)) {
1342                 flush_dcache_range((u64)tr_desc,
1343                                    ALIGN((u64)tr_desc + desc_size,
1344                                          ARCH_DMA_MINALIGN));
1345         }
1346
1347         k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc);
1348
1349         return 0;
1350 }
1351
1352 static int udma_transfer(struct udevice *dev, int direction,
1353                          void *dst, void *src, size_t len)
1354 {
1355         struct udma_dev *ud = dev_get_priv(dev);
1356         /* Channel0 is reserved for memcpy */
1357         struct udma_chan *uc = &ud->channels[0];
1358         dma_addr_t paddr = 0;
1359         int ret;
1360
1361         ret = udma_alloc_chan_resources(uc);
1362         if (ret)
1363                 return ret;
1364
1365         udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
1366         udma_start(uc);
1367         udma_poll_completion(uc, &paddr);
1368         udma_stop(uc);
1369
1370         udma_free_chan_resources(uc);
1371         return 0;
1372 }
1373
1374 static int udma_request(struct dma *dma)
1375 {
1376         struct udma_dev *ud = dev_get_priv(dma->dev);
1377         struct udma_chan *uc;
1378         unsigned long dummy;
1379         int ret;
1380
1381         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1382                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1383                 return -EINVAL;
1384         }
1385
1386         uc = &ud->channels[dma->id];
1387         ret = udma_alloc_chan_resources(uc);
1388         if (ret) {
1389                 dev_err(dma->dev, "alloc dma res failed %d\n", ret);
1390                 return -EINVAL;
1391         }
1392
1393         uc->hdesc_size = cppi5_hdesc_calc_size(uc->needs_epib,
1394                                                uc->psd_size, 0);
1395         uc->hdesc_size = ALIGN(uc->hdesc_size, ARCH_DMA_MINALIGN);
1396
1397         if (uc->dir == DMA_MEM_TO_DEV) {
1398                 uc->desc_tx = dma_alloc_coherent(uc->hdesc_size, &dummy);
1399                 memset(uc->desc_tx, 0, uc->hdesc_size);
1400         } else {
1401                 uc->desc_rx = dma_alloc_coherent(
1402                                 uc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
1403                 memset(uc->desc_rx, 0, uc->hdesc_size * UDMA_RX_DESC_NUM);
1404         }
1405
1406         uc->in_use = true;
1407         uc->desc_rx_cur = 0;
1408         uc->num_rx_bufs = 0;
1409
1410         return 0;
1411 }
1412
1413 static int udma_free(struct dma *dma)
1414 {
1415         struct udma_dev *ud = dev_get_priv(dma->dev);
1416         struct udma_chan *uc;
1417
1418         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1419                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1420                 return -EINVAL;
1421         }
1422         uc = &ud->channels[dma->id];
1423
1424         if (udma_is_chan_running(uc))
1425                 udma_stop(uc);
1426         udma_free_chan_resources(uc);
1427
1428         uc->in_use = false;
1429
1430         return 0;
1431 }
1432
1433 static int udma_enable(struct dma *dma)
1434 {
1435         struct udma_dev *ud = dev_get_priv(dma->dev);
1436         struct udma_chan *uc;
1437         int ret;
1438
1439         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1440                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1441                 return -EINVAL;
1442         }
1443         uc = &ud->channels[dma->id];
1444
1445         ret = udma_start(uc);
1446
1447         return ret;
1448 }
1449
1450 static int udma_disable(struct dma *dma)
1451 {
1452         struct udma_dev *ud = dev_get_priv(dma->dev);
1453         struct udma_chan *uc;
1454         int ret = 0;
1455
1456         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1457                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1458                 return -EINVAL;
1459         }
1460         uc = &ud->channels[dma->id];
1461
1462         if (udma_is_chan_running(uc))
1463                 ret = udma_stop(uc);
1464         else
1465                 dev_err(dma->dev, "%s not running\n", __func__);
1466
1467         return ret;
1468 }
1469
1470 static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
1471 {
1472         struct udma_dev *ud = dev_get_priv(dma->dev);
1473         struct cppi5_host_desc_t *desc_tx;
1474         dma_addr_t dma_src = (dma_addr_t)src;
1475         struct ti_udma_drv_packet_data packet_data = { 0 };
1476         dma_addr_t paddr;
1477         struct udma_chan *uc;
1478         u32 tc_ring_id;
1479         int ret;
1480
1481         if (metadata)
1482                 packet_data = *((struct ti_udma_drv_packet_data *)metadata);
1483
1484         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1485                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1486                 return -EINVAL;
1487         }
1488         uc = &ud->channels[dma->id];
1489
1490         if (uc->dir != DMA_MEM_TO_DEV)
1491                 return -EINVAL;
1492
1493         tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1494
1495         desc_tx = uc->desc_tx;
1496
1497         cppi5_hdesc_reset_hbdesc(desc_tx);
1498
1499         cppi5_hdesc_init(desc_tx,
1500                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1501                          uc->psd_size);
1502         cppi5_hdesc_set_pktlen(desc_tx, len);
1503         cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
1504         cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
1505         cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
1506         /* pass below information from caller */
1507         cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
1508         cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
1509
1510         if (!udma_is_coherent(uc)) {
1511                 flush_dcache_range((u64)dma_src,
1512                                    ALIGN((u64)dma_src + len,
1513                                          ARCH_DMA_MINALIGN));
1514                 flush_dcache_range((u64)desc_tx,
1515                                    ALIGN((u64)desc_tx + uc->hdesc_size,
1516                                          ARCH_DMA_MINALIGN));
1517         }
1518
1519         ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx);
1520         if (ret) {
1521                 dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
1522                         dma->id, ret);
1523                 return ret;
1524         }
1525
1526         udma_poll_completion(uc, &paddr);
1527
1528         return 0;
1529 }
1530
1531 static int udma_receive(struct dma *dma, void **dst, void *metadata)
1532 {
1533         struct udma_dev *ud = dev_get_priv(dma->dev);
1534         struct cppi5_host_desc_t *desc_rx;
1535         dma_addr_t buf_dma;
1536         struct udma_chan *uc;
1537         u32 buf_dma_len, pkt_len;
1538         u32 port_id = 0;
1539         int ret;
1540
1541         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1542                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1543                 return -EINVAL;
1544         }
1545         uc = &ud->channels[dma->id];
1546
1547         if (uc->dir != DMA_DEV_TO_MEM)
1548                 return -EINVAL;
1549         if (!uc->num_rx_bufs)
1550                 return -EINVAL;
1551
1552         ret = k3_nav_ringacc_ring_pop(uc->rchan->r_ring, &desc_rx);
1553         if (ret && ret != -ENODATA) {
1554                 dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
1555                 return ret;
1556         } else if (ret == -ENODATA) {
1557                 return 0;
1558         }
1559
1560         /* invalidate cache data */
1561         if (!udma_is_coherent(uc)) {
1562                 invalidate_dcache_range((ulong)desc_rx,
1563                                         (ulong)(desc_rx + uc->hdesc_size));
1564         }
1565
1566         cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
1567         pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
1568
1569         /* invalidate cache data */
1570         if (!udma_is_coherent(uc)) {
1571                 invalidate_dcache_range((ulong)buf_dma,
1572                                         (ulong)(buf_dma + buf_dma_len));
1573         }
1574
1575         cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
1576
1577         *dst = (void *)buf_dma;
1578         uc->num_rx_bufs--;
1579
1580         return pkt_len;
1581 }
1582
1583 static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
1584 {
1585         struct udma_dev *ud = dev_get_priv(dma->dev);
1586         struct udma_chan *uc = &ud->channels[0];
1587         ofnode chconf_node, slave_node;
1588         char prop[50];
1589         u32 val;
1590
1591         for (val = 0; val < ud->ch_count; val++) {
1592                 uc = &ud->channels[val];
1593                 if (!uc->in_use)
1594                         break;
1595         }
1596
1597         if (val == ud->ch_count)
1598                 return -EBUSY;
1599
1600         uc->dir = DMA_DEV_TO_MEM;
1601         if (args->args[2] == UDMA_DIR_TX)
1602                 uc->dir = DMA_MEM_TO_DEV;
1603
1604         slave_node = ofnode_get_by_phandle(args->args[0]);
1605         if (!ofnode_valid(slave_node)) {
1606                 dev_err(ud->dev, "slave node is missing\n");
1607                 return -EINVAL;
1608         }
1609
1610         snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]);
1611         chconf_node = ofnode_find_subnode(slave_node, prop);
1612         if (!ofnode_valid(chconf_node)) {
1613                 dev_err(ud->dev, "Channel configuration node is missing\n");
1614                 return -EINVAL;
1615         }
1616
1617         if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) {
1618                 if (val == UDMA_PKT_MODE)
1619                         uc->pkt_mode = true;
1620         }
1621
1622         if (!ofnode_read_u32(chconf_node, "statictr-type", &val))
1623                 uc->static_tr_type = val;
1624
1625         uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib");
1626         if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val))
1627                 uc->psd_size = val;
1628         uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size;
1629
1630         if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) {
1631                 dev_err(ud->dev, "ti,psil-base is missing\n");
1632                 return -EINVAL;
1633         }
1634
1635         uc->slave_thread_id = val + args->args[1];
1636
1637         dma->id = uc->id;
1638         pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
1639                  dma->id, uc->needs_epib,
1640                  uc->psd_size, uc->metadata_size,
1641                  uc->slave_thread_id);
1642
1643         return 0;
1644 }
1645
1646 int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
1647 {
1648         struct udma_dev *ud = dev_get_priv(dma->dev);
1649         struct cppi5_host_desc_t *desc_rx;
1650         dma_addr_t dma_dst;
1651         struct udma_chan *uc;
1652         u32 desc_num;
1653
1654         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1655                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1656                 return -EINVAL;
1657         }
1658         uc = &ud->channels[dma->id];
1659
1660         if (uc->dir != DMA_DEV_TO_MEM)
1661                 return -EINVAL;
1662
1663         if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
1664                 return -EINVAL;
1665
1666         desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
1667         desc_rx = uc->desc_rx + (desc_num * uc->hdesc_size);
1668         dma_dst = (dma_addr_t)dst;
1669
1670         cppi5_hdesc_reset_hbdesc(desc_rx);
1671
1672         cppi5_hdesc_init(desc_rx,
1673                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1674                          uc->psd_size);
1675         cppi5_hdesc_set_pktlen(desc_rx, size);
1676         cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
1677
1678         if (!udma_is_coherent(uc)) {
1679                 flush_dcache_range((u64)desc_rx,
1680                                    ALIGN((u64)desc_rx + uc->hdesc_size,
1681                                          ARCH_DMA_MINALIGN));
1682         }
1683
1684         k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);
1685
1686         uc->num_rx_bufs++;
1687         uc->desc_rx_cur++;
1688
1689         return 0;
1690 }
1691
1692 static const struct dma_ops udma_ops = {
1693         .transfer       = udma_transfer,
1694         .of_xlate       = udma_of_xlate,
1695         .request        = udma_request,
1696         .free           = udma_free,
1697         .enable         = udma_enable,
1698         .disable        = udma_disable,
1699         .send           = udma_send,
1700         .receive        = udma_receive,
1701         .prepare_rcv_buf = udma_prepare_rcv_buf,
1702 };
1703
1704 static const struct udevice_id udma_ids[] = {
1705         { .compatible = "ti,k3-navss-udmap" },
1706         { }
1707 };
1708
1709 U_BOOT_DRIVER(ti_edma3) = {
1710         .name   = "ti-udma",
1711         .id     = UCLASS_DMA,
1712         .of_match = udma_ids,
1713         .ops    = &udma_ops,
1714         .probe  = udma_probe,
1715         .priv_auto_alloc_size = sizeof(struct udma_dev),
1716 };