drivers/dma/ti/k3-udma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6 #define pr_fmt(fmt) "udma: " fmt
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/bitops.h>
  11 #include <malloc.h>
  12 #include <asm/dma-mapping.h>
  13 #include <dm.h>
  14 #include <dm/read.h>
  15 #include <dm/of_access.h>
  16 #include <dma.h>
  17 #include <dma-uclass.h>
  18 #include <linux/delay.h>
  19 #include <dt-bindings/dma/k3-udma.h>
  20 #include <linux/soc/ti/k3-navss-ringacc.h>
  21 #include <linux/soc/ti/cppi5.h>
  22 #include <linux/soc/ti/ti-udma.h>
  23 #include <linux/soc/ti/ti_sci_protocol.h>
  24
  25 #include "k3-udma-hwdef.h"
  26
  27 #if BITS_PER_LONG == 64
  28 #define RINGACC_RING_USE_PROXY  (0)
  29 #else
  30 #define RINGACC_RING_USE_PROXY  (1)
  31 #endif
  32
  33 struct udma_chan;
  34
  35 enum udma_mmr {
  36         MMR_GCFG = 0,
  37         MMR_RCHANRT,
  38         MMR_TCHANRT,
  39         MMR_LAST,
  40 };
  41
  42 static const char * const mmr_names[] = {
  43         "gcfg", "rchanrt", "tchanrt"
  44 };
  45
  46 struct udma_tchan {
  47         void __iomem *reg_rt;
  48
  49         int id;
  50         struct k3_nav_ring *t_ring; /* Transmit ring */
  51         struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
  52 };
  53
  54 struct udma_rchan {
  55         void __iomem *reg_rt;
  56
  57         int id;
  58         struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
  59         struct k3_nav_ring *r_ring; /* Receive ring*/
  60 };
  61
  62 struct udma_rflow {
  63         int id;
  64 };
  65
  66 struct udma_dev {
  67         struct device *dev;
  68         void __iomem *mmrs[MMR_LAST];
  69
  70         struct k3_nav_ringacc *ringacc;
  71
  72         u32 features;
  73
  74         int tchan_cnt;
  75         int echan_cnt;
  76         int rchan_cnt;
  77         int rflow_cnt;
  78         unsigned long *tchan_map;
  79         unsigned long *rchan_map;
  80         unsigned long *rflow_map;
  81
  82         struct udma_tchan *tchans;
  83         struct udma_rchan *rchans;
  84         struct udma_rflow *rflows;
  85
  86         struct udma_chan *channels;
  87         u32 psil_base;
  88
  89         u32 ch_count;
  90         const struct ti_sci_handle *tisci;
  91         const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
  92         const struct ti_sci_rm_psil_ops *tisci_psil_ops;
  93         u32  tisci_dev_id;
  94         u32  tisci_navss_dev_id;
  95         bool is_coherent;
  96 };
  97
  98 struct udma_chan {
  99         struct udma_dev *ud;
 100         char name[20];
 101
 102         struct udma_tchan *tchan;
 103         struct udma_rchan *rchan;
 104         struct udma_rflow *rflow;
 105
 106         u32 bcnt; /* number of bytes completed since the start of the channel */
 107
 108         bool pkt_mode; /* TR or packet */
 109         bool needs_epib; /* EPIB is needed for the communication or not */
 110         u32 psd_size; /* size of Protocol Specific Data */
 111         u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
 112         int slave_thread_id;
 113         u32 src_thread;
 114         u32 dst_thread;
 115         u32 static_tr_type;
 116
 117         u32 id;
 118         enum dma_direction dir;
 119
 120         struct cppi5_host_desc_t *desc_tx;
 121         u32 hdesc_size;
 122         bool in_use;
 123         void    *desc_rx;
 124         u32     num_rx_bufs;
 125         u32     desc_rx_cur;
 126
 127 };
 128
 129 #define UDMA_CH_1000(ch)                (ch * 0x1000)
 130 #define UDMA_CH_100(ch)                 (ch * 0x100)
 131 #define UDMA_CH_40(ch)                  (ch * 0x40)
 132
 133 #ifdef PKTBUFSRX
 134 #define UDMA_RX_DESC_NUM PKTBUFSRX
 135 #else
 136 #define UDMA_RX_DESC_NUM 4
 137 #endif
 138
 139 /* Generic register access functions */
 140 static inline u32 udma_read(void __iomem *base, int reg)
 141 {
 142         u32 v;
 143
 144         v = __raw_readl(base + reg);
 145         pr_debug("READL(32): v(%08X)<--reg(%p)\n", v, base + reg);
 146         return v;
 147 }
 148
 149 static inline void udma_write(void __iomem *base, int reg, u32 val)
 150 {
 151         pr_debug("WRITEL(32): v(%08X)-->reg(%p)\n", val, base + reg);
 152         __raw_writel(val, base + reg);
 153 }
 154
 155 static inline void udma_update_bits(void __iomem *base, int reg,
 156                                     u32 mask, u32 val)
 157 {
 158         u32 tmp, orig;
 159
 160         orig = udma_read(base, reg);
 161         tmp = orig & ~mask;
 162         tmp |= (val & mask);
 163
 164         if (tmp != orig)
 165                 udma_write(base, reg, tmp);
 166 }
 167
 168 /* TCHANRT */
 169 static inline u32 udma_tchanrt_read(struct udma_tchan *tchan, int reg)
 170 {
 171         if (!tchan)
 172                 return 0;
 173         return udma_read(tchan->reg_rt, reg);
 174 }
 175
 176 static inline void udma_tchanrt_write(struct udma_tchan *tchan,
 177                                       int reg, u32 val)
 178 {
 179         if (!tchan)
 180                 return;
 181         udma_write(tchan->reg_rt, reg, val);
 182 }
 183
 184 /* RCHANRT */
 185 static inline u32 udma_rchanrt_read(struct udma_rchan *rchan, int reg)
 186 {
 187         if (!rchan)
 188                 return 0;
 189         return udma_read(rchan->reg_rt, reg);
 190 }
 191
 192 static inline void udma_rchanrt_write(struct udma_rchan *rchan,
 193                                       int reg, u32 val)
 194 {
 195         if (!rchan)
 196                 return;
 197         udma_write(rchan->reg_rt, reg, val);
 198 }
 199
 200 static inline int udma_navss_psil_pair(struct udma_dev *ud, u32 src_thread,
 201                                        u32 dst_thread)
 202 {
 203         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 204         return ud->tisci_psil_ops->pair(ud->tisci,
 205                                         ud->tisci_navss_dev_id,
 206                                         src_thread, dst_thread);
 207 }
 208
 209 static inline int udma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
 210                                          u32 dst_thread)
 211 {
 212         dst_thread |= UDMA_PSIL_DST_THREAD_ID_OFFSET;
 213         return ud->tisci_psil_ops->unpair(ud->tisci,
 214                                           ud->tisci_navss_dev_id,
 215                                           src_thread, dst_thread);
 216 }
 217
 218 static inline char *udma_get_dir_text(enum dma_direction dir)
 219 {
 220         switch (dir) {
 221         case DMA_DEV_TO_MEM:
 222                 return "DEV_TO_MEM";
 223         case DMA_MEM_TO_DEV:
 224                 return "MEM_TO_DEV";
 225         case DMA_MEM_TO_MEM:
 226                 return "MEM_TO_MEM";
 227         case DMA_DEV_TO_DEV:
 228                 return "DEV_TO_DEV";
 229         default:
 230                 break;
 231         }
 232
 233         return "invalid";
 234 }
 235
 236 static inline bool udma_is_chan_running(struct udma_chan *uc)
 237 {
 238         u32 trt_ctl = 0;
 239         u32 rrt_ctl = 0;
 240
 241         switch (uc->dir) {
 242         case DMA_DEV_TO_MEM:
 243                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 244                 pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
 245                          __func__, rrt_ctl,
 246                          udma_rchanrt_read(uc->rchan,
 247                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 248                 break;
 249         case DMA_MEM_TO_DEV:
 250                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 251                 pr_debug("%s: trt_ctl: 0x%08x (peer: 0x%08x)\n",
 252                          __func__, trt_ctl,
 253                          udma_tchanrt_read(uc->tchan,
 254                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 255                 break;
 256         case DMA_MEM_TO_MEM:
 257                 trt_ctl = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 258                 rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 259                 break;
 260         default:
 261                 break;
 262         }
 263
 264         if (trt_ctl & UDMA_CHAN_RT_CTL_EN || rrt_ctl & UDMA_CHAN_RT_CTL_EN)
 265                 return true;
 266
 267         return false;
 268 }
 269
 270 static int udma_is_coherent(struct udma_chan *uc)
 271 {
 272         return uc->ud->is_coherent;
 273 }
 274
 275 static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
 276 {
 277         struct k3_nav_ring *ring = NULL;
 278         int ret = -ENOENT;
 279
 280         switch (uc->dir) {
 281         case DMA_DEV_TO_MEM:
 282                 ring = uc->rchan->r_ring;
 283                 break;
 284         case DMA_MEM_TO_DEV:
 285                 ring = uc->tchan->tc_ring;
 286                 break;
 287         case DMA_MEM_TO_MEM:
 288                 ring = uc->tchan->tc_ring;
 289                 break;
 290         default:
 291                 break;
 292         }
 293
 294         if (ring && k3_nav_ringacc_ring_get_occ(ring))
 295                 ret = k3_nav_ringacc_ring_pop(ring, addr);
 296
 297         return ret;
 298 }
 299
 300 static void udma_reset_rings(struct udma_chan *uc)
 301 {
 302         struct k3_nav_ring *ring1 = NULL;
 303         struct k3_nav_ring *ring2 = NULL;
 304
 305         switch (uc->dir) {
 306         case DMA_DEV_TO_MEM:
 307                 ring1 = uc->rchan->fd_ring;
 308                 ring2 = uc->rchan->r_ring;
 309                 break;
 310         case DMA_MEM_TO_DEV:
 311                 ring1 = uc->tchan->t_ring;
 312                 ring2 = uc->tchan->tc_ring;
 313                 break;
 314         case DMA_MEM_TO_MEM:
 315                 ring1 = uc->tchan->t_ring;
 316                 ring2 = uc->tchan->tc_ring;
 317                 break;
 318         default:
 319                 break;
 320         }
 321
 322         if (ring1)
 323                 k3_nav_ringacc_ring_reset_dma(ring1, 0);
 324         if (ring2)
 325                 k3_nav_ringacc_ring_reset(ring2);
 326 }
 327
 328 static void udma_reset_counters(struct udma_chan *uc)
 329 {
 330         u32 val;
 331
 332         if (uc->tchan) {
 333                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_BCNT_REG);
 334                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_BCNT_REG, val);
 335
 336                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG);
 337                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_SBCNT_REG, val);
 338
 339                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
 340                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
 341
 342                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
 343                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
 344         }
 345
 346         if (uc->rchan) {
 347                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_BCNT_REG);
 348                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_BCNT_REG, val);
 349
 350                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG);
 351                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_SBCNT_REG, val);
 352
 353                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PCNT_REG);
 354                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PCNT_REG, val);
 355
 356                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG);
 357                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_BCNT_REG, val);
 358         }
 359
 360         uc->bcnt = 0;
 361 }
 362
 363 static inline int udma_stop_hard(struct udma_chan *uc)
 364 {
 365         pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
 366
 367         switch (uc->dir) {
 368         case DMA_DEV_TO_MEM:
 369                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
 370                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 371                 break;
 372         case DMA_MEM_TO_DEV:
 373                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 374                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG, 0);
 375                 break;
 376         case DMA_MEM_TO_MEM:
 377                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 378                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 379                 break;
 380         default:
 381                 return -EINVAL;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int udma_start(struct udma_chan *uc)
 388 {
 389         /* Channel is already running, no need to proceed further */
 390         if (udma_is_chan_running(uc))
 391                 goto out;
 392
 393         pr_debug("%s: chan:%d dir:%s (static_tr_type: %d)\n",
 394                  __func__, uc->id, udma_get_dir_text(uc->dir),
 395                  uc->static_tr_type);
 396
 397         /* Make sure that we clear the teardown bit, if it is set */
 398         udma_stop_hard(uc);
 399
 400         /* Reset all counters */
 401         udma_reset_counters(uc);
 402
 403         switch (uc->dir) {
 404         case DMA_DEV_TO_MEM:
 405                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 406                                    UDMA_CHAN_RT_CTL_EN);
 407
 408                 /* Enable remote */
 409                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 410                                    UDMA_PEER_RT_EN_ENABLE);
 411
 412                 pr_debug("%s(rx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 413                          __func__,
 414                          udma_rchanrt_read(uc->rchan,
 415                                            UDMA_RCHAN_RT_CTL_REG),
 416                          udma_rchanrt_read(uc->rchan,
 417                                            UDMA_RCHAN_RT_PEER_RT_EN_REG));
 418                 break;
 419         case DMA_MEM_TO_DEV:
 420                 /* Enable remote */
 421                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG,
 422                                    UDMA_PEER_RT_EN_ENABLE);
 423
 424                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 425                                    UDMA_CHAN_RT_CTL_EN);
 426
 427                 pr_debug("%s(tx): RT_CTL:0x%08x PEER RT_ENABLE:0x%08x\n",
 428                          __func__,
 429                          udma_rchanrt_read(uc->rchan,
 430                                            UDMA_TCHAN_RT_CTL_REG),
 431                          udma_rchanrt_read(uc->rchan,
 432                                            UDMA_TCHAN_RT_PEER_RT_EN_REG));
 433                 break;
 434         case DMA_MEM_TO_MEM:
 435                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
 436                                    UDMA_CHAN_RT_CTL_EN);
 437                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 438                                    UDMA_CHAN_RT_CTL_EN);
 439
 440                 break;
 441         default:
 442                 return -EINVAL;
 443         }
 444
 445         pr_debug("%s: DONE chan:%d\n", __func__, uc->id);
 446 out:
 447         return 0;
 448 }
 449
 450 static inline void udma_stop_mem2dev(struct udma_chan *uc, bool sync)
 451 {
 452         int i = 0;
 453         u32 val;
 454
 455         udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG,
 456                            UDMA_CHAN_RT_CTL_EN |
 457                            UDMA_CHAN_RT_CTL_TDOWN);
 458
 459         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 460
 461         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 462                 val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_CTL_REG);
 463                 udelay(1);
 464                 if (i > 1000) {
 465                         printf(" %s TIMEOUT !\n", __func__);
 466                         break;
 467                 }
 468                 i++;
 469         }
 470
 471         val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_RT_EN_REG);
 472         if (val & UDMA_PEER_RT_EN_ENABLE)
 473                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 474 }
 475
 476 static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
 477 {
 478         int i = 0;
 479         u32 val;
 480
 481         udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG,
 482                            UDMA_PEER_RT_EN_ENABLE |
 483                            UDMA_PEER_RT_EN_TEARDOWN);
 484
 485         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 486
 487         while (sync && (val & UDMA_CHAN_RT_CTL_EN)) {
 488                 val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
 489                 udelay(1);
 490                 if (i > 1000) {
 491                         printf("%s TIMEOUT !\n", __func__);
 492                         break;
 493                 }
 494                 i++;
 495         }
 496
 497         val = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG);
 498         if (val & UDMA_PEER_RT_EN_ENABLE)
 499                 printf("%s: peer not stopped TIMEOUT !\n", __func__);
 500 }
 501
 502 static inline int udma_stop(struct udma_chan *uc)
 503 {
 504         pr_debug("%s: chan:%d dir:%s\n",
 505                  __func__, uc->id, udma_get_dir_text(uc->dir));
 506
 507         udma_reset_counters(uc);
 508         switch (uc->dir) {
 509         case DMA_DEV_TO_MEM:
 510                 udma_stop_dev2mem(uc, true);
 511                 break;
 512         case DMA_MEM_TO_DEV:
 513                 udma_stop_mem2dev(uc, true);
 514                 break;
 515         case DMA_MEM_TO_MEM:
 516                 udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
 517                 udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_CTL_REG, 0);
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         return 0;
 524 }
 525
 526 static void udma_poll_completion(struct udma_chan *uc, dma_addr_t *paddr)
 527 {
 528         int i = 1;
 529
 530         while (udma_pop_from_ring(uc, paddr)) {
 531                 udelay(1);
 532                 if (!(i % 1000000))
 533                         printf(".");
 534                 i++;
 535         }
 536 }
 537
 538 #define UDMA_RESERVE_RESOURCE(res)                                      \
 539 static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,     \
 540                                                int id)                  \
 541 {                                                                       \
 542         if (id >= 0) {                                                  \
 543                 if (test_bit(id, ud->res##_map)) {                      \
 544                         dev_err(ud->dev, "res##%d is in use\n", id);    \
 545                         return ERR_PTR(-ENOENT);                        \
 546                 }                                                       \
 547         } else {                                                        \
 548                 id = find_first_zero_bit(ud->res##_map, ud->res##_cnt); \
 549                 if (id == ud->res##_cnt) {                              \
 550                         return ERR_PTR(-ENOENT);                        \
 551                 }                                                       \
 552         }                                                               \
 553                                                                         \
 554         __set_bit(id, ud->res##_map);                                   \
 555         return &ud->res##s[id];                                         \
 556 }
 557
 558 UDMA_RESERVE_RESOURCE(tchan);
 559 UDMA_RESERVE_RESOURCE(rchan);
 560 UDMA_RESERVE_RESOURCE(rflow);
 561
 562 static int udma_get_tchan(struct udma_chan *uc)
 563 {
 564         struct udma_dev *ud = uc->ud;
 565
 566         if (uc->tchan) {
 567                 dev_dbg(ud->dev, "chan%d: already have tchan%d allocated\n",
 568                         uc->id, uc->tchan->id);
 569                 return 0;
 570         }
 571
 572         uc->tchan = __udma_reserve_tchan(ud, -1);
 573         if (IS_ERR(uc->tchan))
 574                 return PTR_ERR(uc->tchan);
 575
 576         pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
 577
 578         if (udma_is_chan_running(uc)) {
 579                 dev_warn(ud->dev, "chan%d: tchan%d is running!\n", uc->id,
 580                          uc->tchan->id);
 581                 udma_stop(uc);
 582                 if (udma_is_chan_running(uc))
 583                         dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static int udma_get_rchan(struct udma_chan *uc)
 590 {
 591         struct udma_dev *ud = uc->ud;
 592
 593         if (uc->rchan) {
 594                 dev_dbg(ud->dev, "chan%d: already have rchan%d allocated\n",
 595                         uc->id, uc->rchan->id);
 596                 return 0;
 597         }
 598
 599         uc->rchan = __udma_reserve_rchan(ud, -1);
 600         if (IS_ERR(uc->rchan))
 601                 return PTR_ERR(uc->rchan);
 602
 603         pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id);
 604
 605         if (udma_is_chan_running(uc)) {
 606                 dev_warn(ud->dev, "chan%d: rchan%d is running!\n", uc->id,
 607                          uc->rchan->id);
 608                 udma_stop(uc);
 609                 if (udma_is_chan_running(uc))
 610                         dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
 611         }
 612
 613         return 0;
 614 }
 615
 616 static int udma_get_chan_pair(struct udma_chan *uc)
 617 {
 618         struct udma_dev *ud = uc->ud;
 619         int chan_id, end;
 620
 621         if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
 622                 dev_info(ud->dev, "chan%d: already have %d pair allocated\n",
 623                          uc->id, uc->tchan->id);
 624                 return 0;
 625         }
 626
 627         if (uc->tchan) {
 628                 dev_err(ud->dev, "chan%d: already have tchan%d allocated\n",
 629                         uc->id, uc->tchan->id);
 630                 return -EBUSY;
 631         } else if (uc->rchan) {
 632                 dev_err(ud->dev, "chan%d: already have rchan%d allocated\n",
 633                         uc->id, uc->rchan->id);
 634                 return -EBUSY;
 635         }
 636
 637         /* Can be optimized, but let's have it like this for now */
 638         end = min(ud->tchan_cnt, ud->rchan_cnt);
 639         for (chan_id = 0; chan_id < end; chan_id++) {
 640                 if (!test_bit(chan_id, ud->tchan_map) &&
 641                     !test_bit(chan_id, ud->rchan_map))
 642                         break;
 643         }
 644
 645         if (chan_id == end)
 646                 return -ENOENT;
 647
 648         __set_bit(chan_id, ud->tchan_map);
 649         __set_bit(chan_id, ud->rchan_map);
 650         uc->tchan = &ud->tchans[chan_id];
 651         uc->rchan = &ud->rchans[chan_id];
 652
 653         pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id);
 654
 655         if (udma_is_chan_running(uc)) {
 656                 dev_warn(ud->dev, "chan%d: t/rchan%d pair is running!\n",
 657                          uc->id, chan_id);
 658                 udma_stop(uc);
 659                 if (udma_is_chan_running(uc))
 660                         dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
 661         }
 662
 663         return 0;
 664 }
 665
 666 static int udma_get_rflow(struct udma_chan *uc, int flow_id)
 667 {
 668         struct udma_dev *ud = uc->ud;
 669
 670         if (uc->rflow) {
 671                 dev_dbg(ud->dev, "chan%d: already have rflow%d allocated\n",
 672                         uc->id, uc->rflow->id);
 673                 return 0;
 674         }
 675
 676         if (!uc->rchan)
 677                 dev_warn(ud->dev, "chan%d: does not have rchan??\n", uc->id);
 678
 679         uc->rflow = __udma_reserve_rflow(ud, flow_id);
 680         if (IS_ERR(uc->rflow))
 681                 return PTR_ERR(uc->rflow);
 682
 683         pr_debug("chan%d: got rflow%d\n", uc->id, uc->rflow->id);
 684         return 0;
 685 }
 686
 687 static void udma_put_rchan(struct udma_chan *uc)
 688 {
 689         struct udma_dev *ud = uc->ud;
 690
 691         if (uc->rchan) {
 692                 dev_dbg(ud->dev, "chan%d: put rchan%d\n", uc->id,
 693                         uc->rchan->id);
 694                 __clear_bit(uc->rchan->id, ud->rchan_map);
 695                 uc->rchan = NULL;
 696         }
 697 }
 698
 699 static void udma_put_tchan(struct udma_chan *uc)
 700 {
 701         struct udma_dev *ud = uc->ud;
 702
 703         if (uc->tchan) {
 704                 dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
 705                         uc->tchan->id);
 706                 __clear_bit(uc->tchan->id, ud->tchan_map);
 707                 uc->tchan = NULL;
 708         }
 709 }
 710
 711 static void udma_put_rflow(struct udma_chan *uc)
 712 {
 713         struct udma_dev *ud = uc->ud;
 714
 715         if (uc->rflow) {
 716                 dev_dbg(ud->dev, "chan%d: put rflow%d\n", uc->id,
 717                         uc->rflow->id);
 718                 __clear_bit(uc->rflow->id, ud->rflow_map);
 719                 uc->rflow = NULL;
 720         }
 721 }
 722
 723 static void udma_free_tx_resources(struct udma_chan *uc)
 724 {
 725         if (!uc->tchan)
 726                 return;
 727
 728         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 729         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 730         uc->tchan->t_ring = NULL;
 731         uc->tchan->tc_ring = NULL;
 732
 733         udma_put_tchan(uc);
 734 }
 735
 736 static int udma_alloc_tx_resources(struct udma_chan *uc)
 737 {
 738         struct k3_nav_ring_cfg ring_cfg;
 739         struct udma_dev *ud = uc->ud;
 740         int ret;
 741
 742         ret = udma_get_tchan(uc);
 743         if (ret)
 744                 return ret;
 745
 746         uc->tchan->t_ring = k3_nav_ringacc_request_ring(
 747                                 ud->ringacc, uc->tchan->id,
 748                                 RINGACC_RING_USE_PROXY);
 749         if (!uc->tchan->t_ring) {
 750                 ret = -EBUSY;
 751                 goto err_tx_ring;
 752         }
 753
 754         uc->tchan->tc_ring = k3_nav_ringacc_request_ring(
 755                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 756         if (!uc->tchan->tc_ring) {
 757                 ret = -EBUSY;
 758                 goto err_txc_ring;
 759         }
 760
 761         memset(&ring_cfg, 0, sizeof(ring_cfg));
 762         ring_cfg.size = 16;
 763         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 764         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
 765
 766         ret = k3_nav_ringacc_ring_cfg(uc->tchan->t_ring, &ring_cfg);
 767         ret |= k3_nav_ringacc_ring_cfg(uc->tchan->tc_ring, &ring_cfg);
 768
 769         if (ret)
 770                 goto err_ringcfg;
 771
 772         return 0;
 773
 774 err_ringcfg:
 775         k3_nav_ringacc_ring_free(uc->tchan->tc_ring);
 776         uc->tchan->tc_ring = NULL;
 777 err_txc_ring:
 778         k3_nav_ringacc_ring_free(uc->tchan->t_ring);
 779         uc->tchan->t_ring = NULL;
 780 err_tx_ring:
 781         udma_put_tchan(uc);
 782
 783         return ret;
 784 }
 785
 786 static void udma_free_rx_resources(struct udma_chan *uc)
 787 {
 788         if (!uc->rchan)
 789                 return;
 790
 791         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 792         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 793         uc->rchan->fd_ring = NULL;
 794         uc->rchan->r_ring = NULL;
 795
 796         udma_put_rflow(uc);
 797         udma_put_rchan(uc);
 798 }
 799
 800 static int udma_alloc_rx_resources(struct udma_chan *uc)
 801 {
 802         struct k3_nav_ring_cfg ring_cfg;
 803         struct udma_dev *ud = uc->ud;
 804         int fd_ring_id;
 805         int ret;
 806
 807         ret = udma_get_rchan(uc);
 808         if (ret)
 809                 return ret;
 810
 811         /* For MEM_TO_MEM we don't need rflow or rings */
 812         if (uc->dir == DMA_MEM_TO_MEM)
 813                 return 0;
 814
 815         ret = udma_get_rflow(uc, uc->rchan->id);
 816         if (ret) {
 817                 ret = -EBUSY;
 818                 goto err_rflow;
 819         }
 820
 821         fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
 822
 823         uc->rchan->fd_ring = k3_nav_ringacc_request_ring(
 824                                 ud->ringacc, fd_ring_id,
 825                                 RINGACC_RING_USE_PROXY);
 826         if (!uc->rchan->fd_ring) {
 827                 ret = -EBUSY;
 828                 goto err_rx_ring;
 829         }
 830
 831         uc->rchan->r_ring = k3_nav_ringacc_request_ring(
 832                                 ud->ringacc, -1, RINGACC_RING_USE_PROXY);
 833         if (!uc->rchan->r_ring) {
 834                 ret = -EBUSY;
 835                 goto err_rxc_ring;
 836         }
 837
 838         memset(&ring_cfg, 0, sizeof(ring_cfg));
 839         ring_cfg.size = 16;
 840         ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
 841         ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_MESSAGE;
 842
 843         ret = k3_nav_ringacc_ring_cfg(uc->rchan->fd_ring, &ring_cfg);
 844         ret |= k3_nav_ringacc_ring_cfg(uc->rchan->r_ring, &ring_cfg);
 845
 846         if (ret)
 847                 goto err_ringcfg;
 848
 849         return 0;
 850
 851 err_ringcfg:
 852         k3_nav_ringacc_ring_free(uc->rchan->r_ring);
 853         uc->rchan->r_ring = NULL;
 854 err_rxc_ring:
 855         k3_nav_ringacc_ring_free(uc->rchan->fd_ring);
 856         uc->rchan->fd_ring = NULL;
 857 err_rx_ring:
 858         udma_put_rflow(uc);
 859 err_rflow:
 860         udma_put_rchan(uc);
 861
 862         return ret;
 863 }
 864
 865 static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
 866 {
 867         struct udma_dev *ud = uc->ud;
 868         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 869         struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
 870         u32 mode;
 871         int ret;
 872
 873         if (uc->pkt_mode)
 874                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 875         else
 876                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 877
 878         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
 879                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 880                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID;
 881         req.nav_id = ud->tisci_dev_id;
 882         req.index = uc->tchan->id;
 883         req.tx_chan_type = mode;
 884         if (uc->dir == DMA_MEM_TO_MEM)
 885                 req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 886         else
 887                 req.tx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 888                                                           uc->psd_size,
 889                                                           0) >> 2;
 890         req.txcq_qnum = tc_ring;
 891
 892         ret = ud->tisci_udmap_ops->tx_ch_cfg(ud->tisci, &req);
 893         if (ret)
 894                 dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
 895
 896         return ret;
 897 }
 898
 899 static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 900 {
 901         struct udma_dev *ud = uc->ud;
 902         int fd_ring = k3_nav_ringacc_get_ring_id(uc->rchan->fd_ring);
 903         int rx_ring = k3_nav_ringacc_get_ring_id(uc->rchan->r_ring);
 904         int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
 905         struct ti_sci_msg_rm_udmap_rx_ch_cfg req = { 0 };
 906         struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
 907         u32 mode;
 908         int ret;
 909
 910         if (uc->pkt_mode)
 911                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
 912         else
 913                 mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
 914
 915         req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 916                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
 917                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
 918         req.nav_id = ud->tisci_dev_id;
 919         req.index = uc->rchan->id;
 920         req.rx_chan_type = mode;
 921         if (uc->dir == DMA_MEM_TO_MEM) {
 922                 req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
 923                 req.rxcq_qnum = tc_ring;
 924         } else {
 925                 req.rx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
 926                                                           uc->psd_size,
 927                                                           0) >> 2;
 928                 req.rxcq_qnum = rx_ring;
 929         }
 930         if (uc->rflow->id != uc->rchan->id && uc->dir != DMA_MEM_TO_MEM) {
 931                 req.flowid_start = uc->rflow->id;
 932                 req.flowid_cnt = 1;
 933                 req.valid_params |=
 934                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
 935                         TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
 936         }
 937
 938         ret = ud->tisci_udmap_ops->rx_ch_cfg(ud->tisci, &req);
 939         if (ret) {
 940                 dev_err(ud->dev, "tisci rx %u cfg failed %d\n",
 941                         uc->rchan->id, ret);
 942                 return ret;
 943         }
 944         if (uc->dir == DMA_MEM_TO_MEM)
 945                 return ret;
 946
 947         flow_req.valid_params =
 948                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
 949                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
 950                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID |
 951                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID |
 952                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
 953                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID |
 954                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID |
 955                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID |
 956                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID |
 957                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID |
 958                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID |
 959                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID |
 960                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID |
 961                         TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID;
 962
 963         flow_req.nav_id = ud->tisci_dev_id;
 964         flow_req.flow_index = uc->rflow->id;
 965
 966         if (uc->needs_epib)
 967                 flow_req.rx_einfo_present = 1;
 968         else
 969                 flow_req.rx_einfo_present = 0;
 970
 971         if (uc->psd_size)
 972                 flow_req.rx_psinfo_present = 1;
 973         else
 974                 flow_req.rx_psinfo_present = 0;
 975
 976         flow_req.rx_error_handling = 0;
 977         flow_req.rx_desc_type = 0;
 978         flow_req.rx_dest_qnum = rx_ring;
 979         flow_req.rx_src_tag_hi_sel = 2;
 980         flow_req.rx_src_tag_lo_sel = 4;
 981         flow_req.rx_dest_tag_hi_sel = 5;
 982         flow_req.rx_dest_tag_lo_sel = 4;
 983         flow_req.rx_fdq0_sz0_qnum = fd_ring;
 984         flow_req.rx_fdq1_qnum = fd_ring;
 985         flow_req.rx_fdq2_qnum = fd_ring;
 986         flow_req.rx_fdq3_qnum = fd_ring;
 987         flow_req.rx_ps_location = 0;
 988
 989         ret = ud->tisci_udmap_ops->rx_flow_cfg(ud->tisci, &flow_req);
 990         if (ret)
 991                 dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
 992                         uc->rchan->id, uc->rflow->id, ret);
 993
 994         return ret;
 995 }
 996
 997 static int udma_alloc_chan_resources(struct udma_chan *uc)
 998 {
 999         struct udma_dev *ud = uc->ud;
1000         int ret;
1001
1002         pr_debug("%s: chan:%d as %s\n",
1003                  __func__, uc->id, udma_get_dir_text(uc->dir));
1004
1005         switch (uc->dir) {
1006         case DMA_MEM_TO_MEM:
1007                 /* Non synchronized - mem to mem type of transfer */
1008                 ret = udma_get_chan_pair(uc);
1009                 if (ret)
1010                         return ret;
1011
1012                 ret = udma_alloc_tx_resources(uc);
1013                 if (ret)
1014                         goto err_free_res;
1015
1016                 ret = udma_alloc_rx_resources(uc);
1017                 if (ret)
1018                         goto err_free_res;
1019
1020                 uc->src_thread = ud->psil_base + uc->tchan->id;
1021                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
1022                 break;
1023         case DMA_MEM_TO_DEV:
1024                 /* Slave transfer synchronized - mem to dev (TX) trasnfer */
1025                 ret = udma_alloc_tx_resources(uc);
1026                 if (ret)
1027                         goto err_free_res;
1028
1029                 uc->src_thread = ud->psil_base + uc->tchan->id;
1030                 uc->dst_thread = uc->slave_thread_id;
1031                 if (!(uc->dst_thread & 0x8000))
1032                         uc->dst_thread |= 0x8000;
1033
1034                 break;
1035         case DMA_DEV_TO_MEM:
1036                 /* Slave transfer synchronized - dev to mem (RX) trasnfer */
1037                 ret = udma_alloc_rx_resources(uc);
1038                 if (ret)
1039                         goto err_free_res;
1040
1041                 uc->src_thread = uc->slave_thread_id;
1042                 uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
1043
1044                 break;
1045         default:
1046                 /* Can not happen */
1047                 pr_debug("%s: chan:%d invalid direction (%u)\n",
1048                          __func__, uc->id, uc->dir);
1049                 return -EINVAL;
1050         }
1051
1052         /* We have channel indexes and rings */
1053         if (uc->dir == DMA_MEM_TO_MEM) {
1054                 ret = udma_alloc_tchan_sci_req(uc);
1055                 if (ret)
1056                         goto err_free_res;
1057
1058                 ret = udma_alloc_rchan_sci_req(uc);
1059                 if (ret)
1060                         goto err_free_res;
1061         } else {
1062                 /* Slave transfer */
1063                 if (uc->dir == DMA_MEM_TO_DEV) {
1064                         ret = udma_alloc_tchan_sci_req(uc);
1065                         if (ret)
1066                                 goto err_free_res;
1067                 } else {
1068                         ret = udma_alloc_rchan_sci_req(uc);
1069                         if (ret)
1070                                 goto err_free_res;
1071                 }
1072         }
1073
1074         /* PSI-L pairing */
1075         ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
1076         if (ret) {
1077                 dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
1078                 goto err_free_res;
1079         }
1080
1081         return 0;
1082
1083 err_free_res:
1084         udma_free_tx_resources(uc);
1085         udma_free_rx_resources(uc);
1086         uc->slave_thread_id = -1;
1087         return ret;
1088 }
1089
1090 static void udma_free_chan_resources(struct udma_chan *uc)
1091 {
1092         /* Some configuration to UDMA-P channel: disable, reset, whatever */
1093
1094         /* Release PSI-L pairing */
1095         udma_navss_psil_unpair(uc->ud, uc->src_thread, uc->dst_thread);
1096
1097         /* Reset the rings for a new start */
1098         udma_reset_rings(uc);
1099         udma_free_tx_resources(uc);
1100         udma_free_rx_resources(uc);
1101
1102         uc->slave_thread_id = -1;
1103         uc->dir = DMA_MEM_TO_MEM;
1104 }
1105
1106 static int udma_get_mmrs(struct udevice *dev)
1107 {
1108         struct udma_dev *ud = dev_get_priv(dev);
1109         int i;
1110
1111         for (i = 0; i < MMR_LAST; i++) {
1112                 ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
1113                                 mmr_names[i]);
1114                 if (!ud->mmrs[i])
1115                         return -EINVAL;
1116         }
1117
1118         return 0;
1119 }
1120
1121 #define UDMA_MAX_CHANNELS       192
1122
1123 static int udma_probe(struct udevice *dev)
1124 {
1125         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
1126         struct udma_dev *ud = dev_get_priv(dev);
1127         int i, ret;
1128         u32 cap2, cap3;
1129         struct udevice *tmp;
1130         struct udevice *tisci_dev = NULL;
1131
1132         ret = udma_get_mmrs(dev);
1133         if (ret)
1134                 return ret;
1135
1136         ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
1137                                            "ti,ringacc", &tmp);
1138         ud->ringacc = dev_get_priv(tmp);
1139         if (IS_ERR(ud->ringacc))
1140                 return PTR_ERR(ud->ringacc);
1141
1142         ud->psil_base = dev_read_u32_default(dev, "ti,psil-base", 0);
1143         if (!ud->psil_base) {
1144                 dev_info(dev,
1145                          "Missing ti,psil-base property, using %d.\n", ret);
1146                 return -EINVAL;
1147         }
1148
1149         ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &tisci_dev);
1150         if (ret) {
1151                 debug("TISCI RA RM get failed (%d)\n", ret);
1152                 ud->tisci = NULL;
1153                 return 0;
1154         }
1155         ud->tisci = (struct ti_sci_handle *)
1156                          (ti_sci_get_handle_from_sysfw(tisci_dev));
1157
1158         ret = dev_read_u32_default(dev, "ti,sci", 0);
1159         if (!ret) {
1160                 dev_err(dev, "TISCI RA RM disabled\n");
1161                 ud->tisci = NULL;
1162         }
1163
1164         if (ud->tisci) {
1165                 ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
1166
1167                 ud->tisci_dev_id = -1;
1168                 ret = dev_read_u32(dev, "ti,sci-dev-id", &ud->tisci_dev_id);
1169                 if (ret) {
1170                         dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
1171                         return ret;
1172                 }
1173
1174                 ud->tisci_navss_dev_id = -1;
1175                 ret = ofnode_read_u32(navss_ofnode, "ti,sci-dev-id",
1176                                       &ud->tisci_navss_dev_id);
1177                 if (ret) {
1178                         dev_err(dev, "navss sci-dev-id read failure %d\n", ret);
1179                         return ret;
1180                 }
1181
1182                 ud->tisci_udmap_ops = &ud->tisci->ops.rm_udmap_ops;
1183                 ud->tisci_psil_ops = &ud->tisci->ops.rm_psil_ops;
1184         }
1185
1186         ud->is_coherent = dev_read_bool(dev, "dma-coherent");
1187
1188         cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
1189         cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
1190
1191         ud->rflow_cnt = cap3 & 0x3fff;
1192         ud->tchan_cnt = cap2 & 0x1ff;
1193         ud->echan_cnt = (cap2 >> 9) & 0x1ff;
1194         ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
1195         ud->ch_count  = ud->tchan_cnt + ud->rchan_cnt;
1196
1197         dev_info(dev,
1198                  "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
1199                  ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
1200                  ud->tisci_dev_id);
1201         dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
1202
1203         ud->channels = devm_kcalloc(dev, ud->ch_count, sizeof(*ud->channels),
1204                                     GFP_KERNEL);
1205         ud->tchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->tchan_cnt),
1206                                      sizeof(unsigned long), GFP_KERNEL);
1207         ud->tchans = devm_kcalloc(dev, ud->tchan_cnt,
1208                                   sizeof(*ud->tchans), GFP_KERNEL);
1209         ud->rchan_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
1210                                      sizeof(unsigned long), GFP_KERNEL);
1211         ud->rchans = devm_kcalloc(dev, ud->rchan_cnt,
1212                                   sizeof(*ud->rchans), GFP_KERNEL);
1213         ud->rflow_map = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
1214                                      sizeof(unsigned long), GFP_KERNEL);
1215         ud->rflows = devm_kcalloc(dev, ud->rflow_cnt,
1216                                   sizeof(*ud->rflows), GFP_KERNEL);
1217
1218         if (!ud->channels || !ud->tchan_map || !ud->rchan_map ||
1219             !ud->rflow_map || !ud->tchans || !ud->rchans || !ud->rflows)
1220                 return -ENOMEM;
1221
1222         for (i = 0; i < ud->tchan_cnt; i++) {
1223                 struct udma_tchan *tchan = &ud->tchans[i];
1224
1225                 tchan->id = i;
1226                 tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
1227         }
1228
1229         for (i = 0; i < ud->rchan_cnt; i++) {
1230                 struct udma_rchan *rchan = &ud->rchans[i];
1231
1232                 rchan->id = i;
1233                 rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
1234         }
1235
1236         for (i = 0; i < ud->rflow_cnt; i++) {
1237                 struct udma_rflow *rflow = &ud->rflows[i];
1238
1239                 rflow->id = i;
1240         }
1241
1242         for (i = 0; i < ud->ch_count; i++) {
1243                 struct udma_chan *uc = &ud->channels[i];
1244
1245                 uc->ud = ud;
1246                 uc->id = i;
1247                 uc->slave_thread_id = -1;
1248                 uc->tchan = NULL;
1249                 uc->rchan = NULL;
1250                 uc->dir = DMA_MEM_TO_MEM;
1251                 sprintf(uc->name, "UDMA chan%d\n", i);
1252                 if (!i)
1253                         uc->in_use = true;
1254         }
1255
1256         pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1257                  udma_read(ud->mmrs[MMR_GCFG], 0),
1258                  udma_read(ud->mmrs[MMR_GCFG], 0x20),
1259                  udma_read(ud->mmrs[MMR_GCFG], 0x24),
1260                  udma_read(ud->mmrs[MMR_GCFG], 0x28),
1261                  udma_read(ud->mmrs[MMR_GCFG], 0x2c));
1262
1263         uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM | DMA_SUPPORTS_MEM_TO_DEV;
1264
1265         return ret;
1266 }
1267
1268 static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
1269                                  dma_addr_t src, size_t len)
1270 {
1271         u32 tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1272         struct cppi5_tr_type15_t *tr_req;
1273         int num_tr;
1274         size_t tr_size = sizeof(struct cppi5_tr_type15_t);
1275         u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
1276         unsigned long dummy;
1277         void *tr_desc;
1278         size_t desc_size;
1279
1280         if (len < SZ_64K) {
1281                 num_tr = 1;
1282                 tr0_cnt0 = len;
1283                 tr0_cnt1 = 1;
1284         } else {
1285                 unsigned long align_to = __ffs(src | dest);
1286
1287                 if (align_to > 3)
1288                         align_to = 3;
1289                 /*
1290                  * Keep simple: tr0: SZ_64K-alignment blocks,
1291                  *              tr1: the remaining
1292                  */
1293                 num_tr = 2;
1294                 tr0_cnt0 = (SZ_64K - BIT(align_to));
1295                 if (len / tr0_cnt0 >= SZ_64K) {
1296                         dev_err(uc->ud->dev, "size %zu is not supported\n",
1297                                 len);
1298                         return NULL;
1299                 }
1300
1301                 tr0_cnt1 = len / tr0_cnt0;
1302                 tr1_cnt0 = len % tr0_cnt0;
1303         }
1304
1305         desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
1306         tr_desc = dma_alloc_coherent(desc_size, &dummy);
1307         if (!tr_desc)
1308                 return NULL;
1309         memset(tr_desc, 0, desc_size);
1310
1311         cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
1312         cppi5_desc_set_pktids(tr_desc, uc->id, 0x3fff);
1313         cppi5_desc_set_retpolicy(tr_desc, 0, tc_ring_id);
1314
1315         tr_req = tr_desc + tr_size;
1316
1317         cppi5_tr_init(&tr_req[0].flags, CPPI5_TR_TYPE15, false, true,
1318                       CPPI5_TR_EVENT_SIZE_COMPLETION, 1);
1319         cppi5_tr_csf_set(&tr_req[0].flags, CPPI5_TR_CSF_SUPR_EVT);
1320
1321         tr_req[0].addr = src;
1322         tr_req[0].icnt0 = tr0_cnt0;
1323         tr_req[0].icnt1 = tr0_cnt1;
1324         tr_req[0].icnt2 = 1;
1325         tr_req[0].icnt3 = 1;
1326         tr_req[0].dim1 = tr0_cnt0;
1327
1328         tr_req[0].daddr = dest;
1329         tr_req[0].dicnt0 = tr0_cnt0;
1330         tr_req[0].dicnt1 = tr0_cnt1;
1331         tr_req[0].dicnt2 = 1;
1332         tr_req[0].dicnt3 = 1;
1333         tr_req[0].ddim1 = tr0_cnt0;
1334
1335         if (num_tr == 2) {
1336                 cppi5_tr_init(&tr_req[1].flags, CPPI5_TR_TYPE15, false, true,
1337                               CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
1338                 cppi5_tr_csf_set(&tr_req[1].flags, CPPI5_TR_CSF_SUPR_EVT);
1339
1340                 tr_req[1].addr = src + tr0_cnt1 * tr0_cnt0;
1341                 tr_req[1].icnt0 = tr1_cnt0;
1342                 tr_req[1].icnt1 = 1;
1343                 tr_req[1].icnt2 = 1;
1344                 tr_req[1].icnt3 = 1;
1345
1346                 tr_req[1].daddr = dest + tr0_cnt1 * tr0_cnt0;
1347                 tr_req[1].dicnt0 = tr1_cnt0;
1348                 tr_req[1].dicnt1 = 1;
1349                 tr_req[1].dicnt2 = 1;
1350                 tr_req[1].dicnt3 = 1;
1351         }
1352
1353         cppi5_tr_csf_set(&tr_req[num_tr - 1].flags, CPPI5_TR_CSF_EOP);
1354
1355         if (!udma_is_coherent(uc)) {
1356                 flush_dcache_range((u64)tr_desc,
1357                                    ALIGN((u64)tr_desc + desc_size,
1358                                          ARCH_DMA_MINALIGN));
1359         }
1360
1361         k3_nav_ringacc_ring_push(uc->tchan->t_ring, &tr_desc);
1362
1363         return 0;
1364 }
1365
1366 static int udma_transfer(struct udevice *dev, int direction,
1367                          void *dst, void *src, size_t len)
1368 {
1369         struct udma_dev *ud = dev_get_priv(dev);
1370         /* Channel0 is reserved for memcpy */
1371         struct udma_chan *uc = &ud->channels[0];
1372         dma_addr_t paddr = 0;
1373         int ret;
1374
1375         ret = udma_alloc_chan_resources(uc);
1376         if (ret)
1377                 return ret;
1378
1379         udma_prep_dma_memcpy(uc, (dma_addr_t)dst, (dma_addr_t)src, len);
1380         udma_start(uc);
1381         udma_poll_completion(uc, &paddr);
1382         udma_stop(uc);
1383
1384         udma_free_chan_resources(uc);
1385         return 0;
1386 }
1387
1388 static int udma_request(struct dma *dma)
1389 {
1390         struct udma_dev *ud = dev_get_priv(dma->dev);
1391         struct udma_chan *uc;
1392         unsigned long dummy;
1393         int ret;
1394
1395         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1396                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1397                 return -EINVAL;
1398         }
1399
1400         uc = &ud->channels[dma->id];
1401         ret = udma_alloc_chan_resources(uc);
1402         if (ret) {
1403                 dev_err(dma->dev, "alloc dma res failed %d\n", ret);
1404                 return -EINVAL;
1405         }
1406
1407         uc->hdesc_size = cppi5_hdesc_calc_size(uc->needs_epib,
1408                                                uc->psd_size, 0);
1409         uc->hdesc_size = ALIGN(uc->hdesc_size, ARCH_DMA_MINALIGN);
1410
1411         if (uc->dir == DMA_MEM_TO_DEV) {
1412                 uc->desc_tx = dma_alloc_coherent(uc->hdesc_size, &dummy);
1413                 memset(uc->desc_tx, 0, uc->hdesc_size);
1414         } else {
1415                 uc->desc_rx = dma_alloc_coherent(
1416                                 uc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
1417                 memset(uc->desc_rx, 0, uc->hdesc_size * UDMA_RX_DESC_NUM);
1418         }
1419
1420         uc->in_use = true;
1421         uc->desc_rx_cur = 0;
1422         uc->num_rx_bufs = 0;
1423
1424         return 0;
1425 }
1426
1427 static int udma_free(struct dma *dma)
1428 {
1429         struct udma_dev *ud = dev_get_priv(dma->dev);
1430         struct udma_chan *uc;
1431
1432         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1433                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1434                 return -EINVAL;
1435         }
1436         uc = &ud->channels[dma->id];
1437
1438         if (udma_is_chan_running(uc))
1439                 udma_stop(uc);
1440         udma_free_chan_resources(uc);
1441
1442         uc->in_use = false;
1443
1444         return 0;
1445 }
1446
1447 static int udma_enable(struct dma *dma)
1448 {
1449         struct udma_dev *ud = dev_get_priv(dma->dev);
1450         struct udma_chan *uc;
1451         int ret;
1452
1453         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1454                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1455                 return -EINVAL;
1456         }
1457         uc = &ud->channels[dma->id];
1458
1459         ret = udma_start(uc);
1460
1461         return ret;
1462 }
1463
1464 static int udma_disable(struct dma *dma)
1465 {
1466         struct udma_dev *ud = dev_get_priv(dma->dev);
1467         struct udma_chan *uc;
1468         int ret = 0;
1469
1470         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1471                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1472                 return -EINVAL;
1473         }
1474         uc = &ud->channels[dma->id];
1475
1476         if (udma_is_chan_running(uc))
1477                 ret = udma_stop(uc);
1478         else
1479                 dev_err(dma->dev, "%s not running\n", __func__);
1480
1481         return ret;
1482 }
1483
1484 static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
1485 {
1486         struct udma_dev *ud = dev_get_priv(dma->dev);
1487         struct cppi5_host_desc_t *desc_tx;
1488         dma_addr_t dma_src = (dma_addr_t)src;
1489         struct ti_udma_drv_packet_data packet_data = { 0 };
1490         dma_addr_t paddr;
1491         struct udma_chan *uc;
1492         u32 tc_ring_id;
1493         int ret;
1494
1495         if (!metadata)
1496                 packet_data = *((struct ti_udma_drv_packet_data *)metadata);
1497
1498         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1499                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1500                 return -EINVAL;
1501         }
1502         uc = &ud->channels[dma->id];
1503
1504         if (uc->dir != DMA_MEM_TO_DEV)
1505                 return -EINVAL;
1506
1507         tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
1508
1509         desc_tx = uc->desc_tx;
1510
1511         cppi5_hdesc_reset_hbdesc(desc_tx);
1512
1513         cppi5_hdesc_init(desc_tx,
1514                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1515                          uc->psd_size);
1516         cppi5_hdesc_set_pktlen(desc_tx, len);
1517         cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
1518         cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
1519         cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, tc_ring_id);
1520         /* pass below information from caller */
1521         cppi5_hdesc_set_pkttype(desc_tx, packet_data.pkt_type);
1522         cppi5_desc_set_tags_ids(&desc_tx->hdr, 0, packet_data.dest_tag);
1523
1524         if (!udma_is_coherent(uc)) {
1525                 flush_dcache_range((u64)dma_src,
1526                                    ALIGN((u64)dma_src + len,
1527                                          ARCH_DMA_MINALIGN));
1528                 flush_dcache_range((u64)desc_tx,
1529                                    ALIGN((u64)desc_tx + uc->hdesc_size,
1530                                          ARCH_DMA_MINALIGN));
1531         }
1532
1533         ret = k3_nav_ringacc_ring_push(uc->tchan->t_ring, &uc->desc_tx);
1534         if (ret) {
1535                 dev_err(dma->dev, "TX dma push fail ch_id %lu %d\n",
1536                         dma->id, ret);
1537                 return ret;
1538         }
1539
1540         udma_poll_completion(uc, &paddr);
1541
1542         return 0;
1543 }
1544
1545 static int udma_receive(struct dma *dma, void **dst, void *metadata)
1546 {
1547         struct udma_dev *ud = dev_get_priv(dma->dev);
1548         struct cppi5_host_desc_t *desc_rx;
1549         dma_addr_t buf_dma;
1550         struct udma_chan *uc;
1551         u32 buf_dma_len, pkt_len;
1552         u32 port_id = 0;
1553         int ret;
1554
1555         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1556                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1557                 return -EINVAL;
1558         }
1559         uc = &ud->channels[dma->id];
1560
1561         if (uc->dir != DMA_DEV_TO_MEM)
1562                 return -EINVAL;
1563         if (!uc->num_rx_bufs)
1564                 return -EINVAL;
1565
1566         ret = k3_nav_ringacc_ring_pop(uc->rchan->r_ring, &desc_rx);
1567         if (ret && ret != -ENODATA) {
1568                 dev_err(dma->dev, "rx dma fail ch_id:%lu %d\n", dma->id, ret);
1569                 return ret;
1570         } else if (ret == -ENODATA) {
1571                 return 0;
1572         }
1573
1574         /* invalidate cache data */
1575         if (!udma_is_coherent(uc)) {
1576                 invalidate_dcache_range((ulong)desc_rx,
1577                                         (ulong)(desc_rx + uc->hdesc_size));
1578         }
1579
1580         cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
1581         pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
1582
1583         /* invalidate cache data */
1584         if (!udma_is_coherent(uc)) {
1585                 invalidate_dcache_range((ulong)buf_dma,
1586                                         (ulong)(buf_dma + buf_dma_len));
1587         }
1588
1589         cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
1590
1591         *dst = (void *)buf_dma;
1592         uc->num_rx_bufs--;
1593
1594         return pkt_len;
1595 }
1596
1597 static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
1598 {
1599         struct udma_dev *ud = dev_get_priv(dma->dev);
1600         struct udma_chan *uc = &ud->channels[0];
1601         ofnode chconf_node, slave_node;
1602         char prop[50];
1603         u32 val;
1604
1605         for (val = 0; val < ud->ch_count; val++) {
1606                 uc = &ud->channels[val];
1607                 if (!uc->in_use)
1608                         break;
1609         }
1610
1611         if (val == ud->ch_count)
1612                 return -EBUSY;
1613
1614         uc->dir = DMA_DEV_TO_MEM;
1615         if (args->args[2] == UDMA_DIR_TX)
1616                 uc->dir = DMA_MEM_TO_DEV;
1617
1618         slave_node = ofnode_get_by_phandle(args->args[0]);
1619         if (!ofnode_valid(slave_node)) {
1620                 dev_err(ud->dev, "slave node is missing\n");
1621                 return -EINVAL;
1622         }
1623
1624         snprintf(prop, sizeof(prop), "ti,psil-config%u", args->args[1]);
1625         chconf_node = ofnode_find_subnode(slave_node, prop);
1626         if (!ofnode_valid(chconf_node)) {
1627                 dev_err(ud->dev, "Channel configuration node is missing\n");
1628                 return -EINVAL;
1629         }
1630
1631         if (!ofnode_read_u32(chconf_node, "linux,udma-mode", &val)) {
1632                 if (val == UDMA_PKT_MODE)
1633                         uc->pkt_mode = true;
1634         }
1635
1636         if (!ofnode_read_u32(chconf_node, "statictr-type", &val))
1637                 uc->static_tr_type = val;
1638
1639         uc->needs_epib = ofnode_read_bool(chconf_node, "ti,needs-epib");
1640         if (!ofnode_read_u32(chconf_node, "ti,psd-size", &val))
1641                 uc->psd_size = val;
1642         uc->metadata_size = (uc->needs_epib ? 16 : 0) + uc->psd_size;
1643
1644         if (ofnode_read_u32(slave_node, "ti,psil-base", &val)) {
1645                 dev_err(ud->dev, "ti,psil-base is missing\n");
1646                 return -EINVAL;
1647         }
1648
1649         uc->slave_thread_id = val + args->args[1];
1650
1651         dma->id = uc->id;
1652         pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
1653                  dma->id, uc->needs_epib,
1654                  uc->psd_size, uc->metadata_size,
1655                  uc->slave_thread_id);
1656
1657         return 0;
1658 }
1659
1660 int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
1661 {
1662         struct udma_dev *ud = dev_get_priv(dma->dev);
1663         struct cppi5_host_desc_t *desc_rx;
1664         dma_addr_t dma_dst;
1665         struct udma_chan *uc;
1666         u32 desc_num;
1667
1668         if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) {
1669                 dev_err(dma->dev, "invalid dma ch_id %lu\n", dma->id);
1670                 return -EINVAL;
1671         }
1672         uc = &ud->channels[dma->id];
1673
1674         if (uc->dir != DMA_DEV_TO_MEM)
1675                 return -EINVAL;
1676
1677         if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
1678                 return -EINVAL;
1679
1680         desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
1681         desc_rx = uc->desc_rx + (desc_num * uc->hdesc_size);
1682         dma_dst = (dma_addr_t)dst;
1683
1684         cppi5_hdesc_reset_hbdesc(desc_rx);
1685
1686         cppi5_hdesc_init(desc_rx,
1687                          uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
1688                          uc->psd_size);
1689         cppi5_hdesc_set_pktlen(desc_rx, size);
1690         cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
1691
1692         if (!udma_is_coherent(uc)) {
1693                 flush_dcache_range((u64)desc_rx,
1694                                    ALIGN((u64)desc_rx + uc->hdesc_size,
1695                                          ARCH_DMA_MINALIGN));
1696         }
1697
1698         k3_nav_ringacc_ring_push(uc->rchan->fd_ring, &desc_rx);
1699
1700         uc->num_rx_bufs++;
1701         uc->desc_rx_cur++;
1702
1703         return 0;
1704 }
1705
1706 static const struct dma_ops udma_ops = {
1707         .transfer       = udma_transfer,
1708         .of_xlate       = udma_of_xlate,
1709         .request        = udma_request,
1710         .free           = udma_free,
1711         .enable         = udma_enable,
1712         .disable        = udma_disable,
1713         .send           = udma_send,
1714         .receive        = udma_receive,
1715         .prepare_rcv_buf = udma_prepare_rcv_buf,
1716 };
1717
1718 static const struct udevice_id udma_ids[] = {
1719         { .compatible = "ti,k3-navss-udmap" },
1720         { }
1721 };
1722
1723 U_BOOT_DRIVER(ti_edma3) = {
1724         .name   = "ti-udma",
1725         .id     = UCLASS_DMA,
1726         .of_match = udma_ids,
1727         .ops    = &udma_ops,
1728         .probe  = udma_probe,
1729         .priv_auto_alloc_size = sizeof(struct udma_dev),
1730 };