1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2008 by NXP Semiconductors
5 * @Descr: LPC3250 DMA controller interface support functions
7 * Copyright (c) 2015 Tyco Fire Protection Products.
12 #include <asm/arch/dma.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/sys_proto.h>
18 /* DMA controller channel register structure */
19 struct dmac_chan_reg {
28 /* DMA controller register structures */
40 u32 sw_last_burst_req;
41 u32 sw_last_single_req;
45 struct dmac_chan_reg dma_chan[8];
48 #define DMA_NO_OF_CHANNELS 8
50 /* config register definitions */
51 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
55 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
57 int lpc32xx_dma_get_channel(void)
61 if (!alloc_ch) { /* First time caller */
63 * DMA clock are enable by "lpc32xx_dma_init()" and should
64 * be call by board "board_early_init_f()" function.
68 * Make sure DMA controller and all channels are disabled.
69 * Controller is in little-endian mode. Disable sync signals.
71 writel(0, &dma->config);
72 writel(0, &dma->sync);
74 /* Clear interrupt and error statuses */
75 writel(0xFF, &dma->int_tc_clear);
76 writel(0xFF, &dma->raw_tc_stat);
77 writel(0xFF, &dma->int_err_clear);
78 writel(0xFF, &dma->raw_err_stat);
80 /* Enable DMA controller */
81 writel(DMAC_CTRL_ENABLE, &dma->config);
86 /* Check if all the available channels are busy */
87 if (unlikely(i == DMA_NO_OF_CHANNELS))
89 alloc_ch |= BIT_MASK(i);
93 int lpc32xx_dma_start_xfer(unsigned int channel,
94 const struct lpc32xx_dmac_ll *desc, u32 config)
96 if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
97 (channel >= DMA_NO_OF_CHANNELS))) {
98 pr_err("Request for xfer on unallocated channel %d", channel);
101 writel(BIT_MASK(channel), &dma->int_tc_clear);
102 writel(BIT_MASK(channel), &dma->int_err_clear);
103 writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
104 writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
105 writel(desc->next_lli, &dma->dma_chan[channel].lli);
106 writel(desc->next_ctrl, &dma->dma_chan[channel].control);
107 writel(config, &dma->dma_chan[channel].config_ch);
112 int lpc32xx_dma_wait_status(unsigned int channel)
117 /* Check if given channel is valid */
118 if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
119 pr_err("Request for status on unallocated channel %d", channel);
123 start = get_timer(0);
125 reg = readl(&dma->raw_tc_stat);
126 reg |= readl(dma->raw_err_stat);
127 if (reg & BIT_MASK(channel))
130 if (get_timer(start) > CONFIG_SYS_HZ) {
131 pr_err("DMA status timeout channel %d\n", channel);
137 if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
138 setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
139 setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
140 pr_err("DMA error on channel %d\n", channel);
143 setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
144 setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));