2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/fsl_dma.h>
33 /* Controller can only transfer 2^26 - 1 bytes at a time */
34 #define FSL_DMA_MAX_SIZE (0x3ffffff)
36 #if defined(CONFIG_MPC85xx)
37 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
38 #elif defined(CONFIG_MPC86xx)
39 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
41 #error "Freescale DMA engine not supported on your processor"
44 static void dma_sync(void)
46 #if defined(CONFIG_MPC85xx)
47 asm("sync; isync; msync");
48 #elif defined(CONFIG_MPC86xx)
53 static uint dma_check(void) {
54 volatile fsl_dma_t *dma = &dma_base->dma[0];
57 /* While the channel is busy, spin */
59 status = in_be32(&dma->sr);
60 } while (status & FSL_DMA_SR_CB);
62 /* clear MR[CS] channel start bit */
63 out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS);
67 printf ("DMA Error: status = %x\n", status);
73 volatile fsl_dma_t *dma = &dma_base->dma[0];
75 out_be32(&dma->satr, FSL_DMA_SATR_SREAD_NO_SNOOP);
76 out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_NO_SNOOP);
77 out_be32(&dma->sr, 0xffffffff); /* clear any errors */
81 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
82 volatile fsl_dma_t *dma = &dma_base->dma[0];
86 xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
88 out_be32(&dma->dar, (uint) dest);
89 out_be32(&dma->sar, (uint) src);
90 out_be32(&dma->bcr, xfer_size);
92 /* Disable bandwidth control, use direct transfer mode */
93 out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT);
96 /* Start the transfer */
97 out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS |
98 FSL_DMA_MR_CTM_DIRECT |
114 #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
115 void dma_meminit(uint val, uint size)
120 for (*p = 0; p < (uint *)(8 * 1024); p++) {
121 if (((uint)p & 0x1f) == 0)
124 *p = (uint)CONFIG_MEM_INIT_VALUE;
126 if (((uint)p & 0x1c) == 0x1c)
130 dmacpy(0x002000, 0, 0x002000); /* 8K */
131 dmacpy(0x004000, 0, 0x004000); /* 16K */
132 dmacpy(0x008000, 0, 0x008000); /* 32K */
133 dmacpy(0x010000, 0, 0x010000); /* 64K */
134 dmacpy(0x020000, 0, 0x020000); /* 128K */
135 dmacpy(0x040000, 0, 0x040000); /* 256K */
136 dmacpy(0x080000, 0, 0x080000); /* 512K */
137 dmacpy(0x100000, 0, 0x100000); /* 1M */
138 dmacpy(0x200000, 0, 0x200000); /* 2M */
139 dmacpy(0x400000, 0, 0x400000); /* 4M */
141 for (i = 1; i < size / 0x800000; i++)
142 dmacpy((0x800000 * i), 0, 0x800000);