drivers/dma/bcm6348-iudma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/drivers/dma/bcm63xx-iudma.c:
   6  *      Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
   7  *
   8  * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
   9  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  10  *
  11  * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
  12  *      Copyright (C) 2000-2010 Broadcom Corporation
  13  *
  14  * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c:
  15  *      Copyright (C) 2010 Broadcom Corporation
  16  */
  17
  18 #include <common.h>
  19 #include <clk.h>
  20 #include <dm.h>
  21 #include <dma-uclass.h>
  22 #include <memalign.h>
  23 #include <reset.h>
  24 #include <asm/io.h>
  25
  26 #define DMA_RX_DESC     6
  27 #define DMA_TX_DESC     1
  28
  29 /* DMA Channels */
  30 #define DMA_CHAN_FLOWC(x)               ((x) >> 1)
  31 #define DMA_CHAN_MAX                    16
  32 #define DMA_CHAN_SIZE                   0x10
  33 #define DMA_CHAN_TOUT                   500
  34
  35 /* DMA Global Configuration register */
  36 #define DMA_CFG_REG                     0x00
  37 #define  DMA_CFG_ENABLE_SHIFT           0
  38 #define  DMA_CFG_ENABLE_MASK            (1 << DMA_CFG_ENABLE_SHIFT)
  39 #define  DMA_CFG_FLOWC_ENABLE(x)        BIT(DMA_CHAN_FLOWC(x) + 1)
  40 #define  DMA_CFG_NCHANS_SHIFT           24
  41 #define  DMA_CFG_NCHANS_MASK            (0xf << DMA_CFG_NCHANS_SHIFT)
  42
  43 /* DMA Global Flow Control registers */
  44 #define DMA_FLOWC_THR_LO_REG(x)         (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
  45 #define DMA_FLOWC_THR_HI_REG(x)         (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
  46 #define DMA_FLOWC_ALLOC_REG(x)          (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
  47 #define  DMA_FLOWC_ALLOC_FORCE_SHIFT    31
  48 #define  DMA_FLOWC_ALLOC_FORCE_MASK     (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
  49
  50 /* DMA Global Reset register */
  51 #define DMA_RST_REG                     0x34
  52 #define  DMA_RST_CHAN_SHIFT             0
  53 #define  DMA_RST_CHAN_MASK(x)           (1 << x)
  54
  55 /* DMA Channel Configuration register */
  56 #define DMAC_CFG_REG(x)                 (DMA_CHAN_SIZE * (x) + 0x00)
  57 #define  DMAC_CFG_ENABLE_SHIFT          0
  58 #define  DMAC_CFG_ENABLE_MASK           (1 << DMAC_CFG_ENABLE_SHIFT)
  59 #define  DMAC_CFG_PKT_HALT_SHIFT        1
  60 #define  DMAC_CFG_PKT_HALT_MASK         (1 << DMAC_CFG_PKT_HALT_SHIFT)
  61 #define  DMAC_CFG_BRST_HALT_SHIFT       2
  62 #define  DMAC_CFG_BRST_HALT_MASK        (1 << DMAC_CFG_BRST_HALT_SHIFT)
  63
  64 /* DMA Channel Max Burst Length register */
  65 #define DMAC_BURST_REG(x)               (DMA_CHAN_SIZE * (x) + 0x0c)
  66
  67 /* DMA SRAM Descriptor Ring Start register */
  68 #define DMAS_RSTART_REG(x)              (DMA_CHAN_SIZE * (x) + 0x00)
  69
  70 /* DMA SRAM State/Bytes done/ring offset register */
  71 #define DMAS_STATE_DATA_REG(x)          (DMA_CHAN_SIZE * (x) + 0x04)
  72
  73 /* DMA SRAM Buffer Descriptor status and length register */
  74 #define DMAS_DESC_LEN_STATUS_REG(x)     (DMA_CHAN_SIZE * (x) + 0x08)
  75
  76 /* DMA SRAM Buffer Descriptor status and length register */
  77 #define DMAS_DESC_BASE_BUFPTR_REG(x)    (DMA_CHAN_SIZE * (x) + 0x0c)
  78
  79 /* DMA Descriptor Status */
  80 #define DMAD_ST_CRC_SHIFT               8
  81 #define DMAD_ST_CRC_MASK                (1 << DMAD_ST_CRC_SHIFT)
  82 #define DMAD_ST_WRAP_SHIFT              12
  83 #define DMAD_ST_WRAP_MASK               (1 << DMAD_ST_WRAP_SHIFT)
  84 #define DMAD_ST_SOP_SHIFT               13
  85 #define DMAD_ST_SOP_MASK                (1 << DMAD_ST_SOP_SHIFT)
  86 #define DMAD_ST_EOP_SHIFT               14
  87 #define DMAD_ST_EOP_MASK                (1 << DMAD_ST_EOP_SHIFT)
  88 #define DMAD_ST_OWN_SHIFT               15
  89 #define DMAD_ST_OWN_MASK                (1 << DMAD_ST_OWN_SHIFT)
  90
  91 #define DMAD6348_ST_OV_ERR_SHIFT        0
  92 #define DMAD6348_ST_OV_ERR_MASK         (1 << DMAD6348_ST_OV_ERR_SHIFT)
  93 #define DMAD6348_ST_CRC_ERR_SHIFT       1
  94 #define DMAD6348_ST_CRC_ERR_MASK        (1 << DMAD6348_ST_CRC_ERR_SHIFT)
  95 #define DMAD6348_ST_RX_ERR_SHIFT        2
  96 #define DMAD6348_ST_RX_ERR_MASK         (1 << DMAD6348_ST_RX_ERR_SHIFT)
  97 #define DMAD6348_ST_OS_ERR_SHIFT        4
  98 #define DMAD6348_ST_OS_ERR_MASK         (1 << DMAD6348_ST_OS_ERR_SHIFT)
  99 #define DMAD6348_ST_UN_ERR_SHIFT        9
 100 #define DMAD6348_ST_UN_ERR_MASK         (1 << DMAD6348_ST_UN_ERR_SHIFT)
 101
 102 struct bcm6348_dma_desc {
 103         uint16_t length;
 104         uint16_t status;
 105         uint32_t address;
 106 };
 107
 108 struct bcm6348_chan_priv {
 109         void __iomem *dma_ring;
 110         uint8_t dma_ring_size;
 111         uint8_t desc_id;
 112         uint8_t desc_cnt;
 113         bool *busy_desc;
 114         bool running;
 115 };
 116
 117 struct bcm6348_iudma_hw {
 118         uint16_t err_mask;
 119 };
 120
 121 struct bcm6348_iudma_priv {
 122         const struct bcm6348_iudma_hw *hw;
 123         void __iomem *base;
 124         void __iomem *chan;
 125         void __iomem *sram;
 126         struct bcm6348_chan_priv **ch_priv;
 127         uint8_t n_channels;
 128 };
 129
 130 static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
 131 {
 132         return !(ch & 1);
 133 }
 134
 135 static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
 136 {
 137         ulong start = (ulong) ptr;
 138
 139         flush_dcache_range(start, start + size);
 140 }
 141
 142 static inline void bcm6348_iudma_idc(void *ptr, ulong size)
 143 {
 144         ulong start = (ulong) ptr;
 145
 146         invalidate_dcache_range(start, start + size);
 147 }
 148
 149 static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
 150                                     uint8_t ch)
 151 {
 152         unsigned int timeout = DMA_CHAN_TOUT;
 153
 154         do {
 155                 uint32_t cfg, halt;
 156
 157                 if (timeout > DMA_CHAN_TOUT / 2)
 158                         halt = DMAC_CFG_PKT_HALT_MASK;
 159                 else
 160                         halt = DMAC_CFG_BRST_HALT_MASK;
 161
 162                 /* try to stop dma channel */
 163                 writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
 164                 mb();
 165
 166                 /* check if channel was stopped */
 167                 cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
 168                 if (!(cfg & DMAC_CFG_ENABLE_MASK))
 169                         break;
 170
 171                 udelay(1);
 172         } while (--timeout);
 173
 174         if (!timeout)
 175                 pr_err("unable to stop channel %u\n", ch);
 176
 177         /* reset dma channel */
 178         setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 179         mb();
 180         clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 181 }
 182
 183 static int bcm6348_iudma_disable(struct dma *dma)
 184 {
 185         struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 186         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 187
 188         /* stop dma channel */
 189         bcm6348_iudma_chan_stop(priv, dma->id);
 190
 191         /* dma flow control */
 192         if (bcm6348_iudma_chan_is_rx(dma->id))
 193                 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
 194                           DMA_FLOWC_ALLOC_REG(dma->id));
 195
 196         /* init channel config */
 197         ch_priv->running = false;
 198         ch_priv->desc_id = 0;
 199         if (bcm6348_iudma_chan_is_rx(dma->id))
 200                 ch_priv->desc_cnt = 0;
 201         else
 202                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 203
 204         return 0;
 205 }
 206
 207 static int bcm6348_iudma_enable(struct dma *dma)
 208 {
 209         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 210         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 211         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 212         uint8_t i;
 213
 214         /* dma ring init */
 215         for (i = 0; i < ch_priv->desc_cnt; i++) {
 216                 if (bcm6348_iudma_chan_is_rx(dma->id)) {
 217                         ch_priv->busy_desc[i] = false;
 218                         dma_desc->status |= DMAD_ST_OWN_MASK;
 219                 } else {
 220                         dma_desc->status = 0;
 221                         dma_desc->length = 0;
 222                         dma_desc->address = 0;
 223                 }
 224
 225                 if (i == ch_priv->desc_cnt - 1)
 226                         dma_desc->status |= DMAD_ST_WRAP_MASK;
 227
 228                 dma_desc++;
 229         }
 230
 231         /* init to first descriptor */
 232         ch_priv->desc_id = 0;
 233
 234         /* force cache writeback */
 235         bcm6348_iudma_fdc(ch_priv->dma_ring,
 236                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 237
 238         /* clear sram */
 239         writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
 240         writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
 241         writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
 242
 243         /* set dma ring start */
 244         writel_be(virt_to_phys(ch_priv->dma_ring),
 245                   priv->sram + DMAS_RSTART_REG(dma->id));
 246
 247         /* set flow control */
 248         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 249                 u32 val;
 250
 251                 setbits_be32(priv->base + DMA_CFG_REG,
 252                              DMA_CFG_FLOWC_ENABLE(dma->id));
 253
 254                 val = ch_priv->desc_cnt / 3;
 255                 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
 256
 257                 val = (ch_priv->desc_cnt * 2) / 3;
 258                 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
 259
 260                 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
 261         }
 262
 263         /* set dma max burst */
 264         writel_be(ch_priv->desc_cnt,
 265                   priv->chan + DMAC_BURST_REG(dma->id));
 266
 267         /* kick rx dma channel */
 268         if (bcm6348_iudma_chan_is_rx(dma->id))
 269                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 270                              DMAC_CFG_ENABLE_MASK);
 271
 272         /* channel is now enabled */
 273         ch_priv->running = true;
 274
 275         return 0;
 276 }
 277
 278 static int bcm6348_iudma_request(struct dma *dma)
 279 {
 280         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 281         struct bcm6348_chan_priv *ch_priv;
 282
 283         /* check if channel is valid */
 284         if (dma->id >= priv->n_channels)
 285                 return -ENODEV;
 286
 287         /* alloc channel private data */
 288         priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
 289         if (!priv->ch_priv[dma->id])
 290                 return -ENOMEM;
 291         ch_priv = priv->ch_priv[dma->id];
 292
 293         /* alloc dma ring */
 294         if (bcm6348_iudma_chan_is_rx(dma->id))
 295                 ch_priv->dma_ring_size = DMA_RX_DESC;
 296         else
 297                 ch_priv->dma_ring_size = DMA_TX_DESC;
 298
 299         ch_priv->dma_ring =
 300                 malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
 301                                      ch_priv->dma_ring_size);
 302         if (!ch_priv->dma_ring)
 303                 return -ENOMEM;
 304
 305         /* init channel config */
 306         ch_priv->running = false;
 307         ch_priv->desc_id = 0;
 308         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 309                 ch_priv->desc_cnt = 0;
 310                 ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
 311         } else {
 312                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 313                 ch_priv->busy_desc = NULL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
 320 {
 321         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 322         const struct bcm6348_iudma_hw *hw = priv->hw;
 323         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 324         struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
 325         int ret;
 326
 327         if (!ch_priv->running)
 328                 return -EINVAL;
 329
 330         /* get dma ring descriptor address */
 331         dma_desc += ch_priv->desc_id;
 332
 333         /* invalidate cache data */
 334         bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 335
 336         /* check dma own */
 337         if (dma_desc->status & DMAD_ST_OWN_MASK)
 338                 return -EAGAIN;
 339
 340         /* check pkt */
 341         if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
 342             !(dma_desc->status & DMAD_ST_SOP_MASK) ||
 343             (dma_desc->status & hw->err_mask)) {
 344                 pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
 345                        dma->id, ch_priv->desc_id, dma_desc->status);
 346                 ret = -EAGAIN;
 347         } else {
 348                 /* set dma buffer address */
 349                 *dst = phys_to_virt(dma_desc->address);
 350
 351                 /* invalidate cache data */
 352                 bcm6348_iudma_idc(*dst, dma_desc->length);
 353
 354                 /* return packet length */
 355                 ret = dma_desc->length;
 356         }
 357
 358         /* busy dma descriptor */
 359         ch_priv->busy_desc[ch_priv->desc_id] = true;
 360
 361         /* increment dma descriptor */
 362         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 363
 364         return ret;
 365 }
 366
 367 static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
 368                               void *metadata)
 369 {
 370         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 371         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 372         struct bcm6348_dma_desc *dma_desc;
 373         uint16_t status;
 374
 375         if (!ch_priv->running)
 376                 return -EINVAL;
 377
 378         /* flush cache */
 379         bcm6348_iudma_fdc(src, len);
 380
 381         /* get dma ring descriptor address */
 382         dma_desc = ch_priv->dma_ring;
 383         dma_desc += ch_priv->desc_id;
 384
 385         /* config dma descriptor */
 386         status = (DMAD_ST_OWN_MASK |
 387                   DMAD_ST_EOP_MASK |
 388                   DMAD_ST_CRC_MASK |
 389                   DMAD_ST_SOP_MASK);
 390         if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
 391                 status |= DMAD_ST_WRAP_MASK;
 392
 393         /* set dma descriptor */
 394         dma_desc->address = virt_to_phys(src);
 395         dma_desc->length = len;
 396         dma_desc->status = status;
 397
 398         /* flush cache */
 399         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 400
 401         /* kick tx dma channel */
 402         setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
 403
 404         /* poll dma status */
 405         do {
 406                 /* invalidate cache */
 407                 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 408
 409                 if (!(dma_desc->status & DMAD_ST_OWN_MASK))
 410                         break;
 411         } while(1);
 412
 413         /* increment dma descriptor */
 414         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 415
 416         return 0;
 417 }
 418
 419 static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
 420 {
 421         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 422         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 423         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 424         uint16_t status;
 425         uint8_t i;
 426         u32 cfg;
 427
 428         /* get dirty dma descriptor */
 429         for (i = 0; i < ch_priv->desc_cnt; i++) {
 430                 if (phys_to_virt(dma_desc->address) == dst)
 431                         break;
 432
 433                 dma_desc++;
 434         }
 435
 436         /* dma descriptor not found */
 437         if (i == ch_priv->desc_cnt) {
 438                 pr_err("dirty dma descriptor not found\n");
 439                 return -ENOENT;
 440         }
 441
 442         /* invalidate cache */
 443         bcm6348_iudma_idc(ch_priv->dma_ring,
 444                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 445
 446         /* free dma descriptor */
 447         ch_priv->busy_desc[i] = false;
 448
 449         status = DMAD_ST_OWN_MASK;
 450         if (i == ch_priv->desc_cnt - 1)
 451                 status |= DMAD_ST_WRAP_MASK;
 452
 453         dma_desc->status |= status;
 454         dma_desc->length = PKTSIZE_ALIGN;
 455
 456         /* tell dma we allocated one buffer */
 457         writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
 458
 459         /* flush cache */
 460         bcm6348_iudma_fdc(ch_priv->dma_ring,
 461                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 462
 463         /* kick rx dma channel if disabled */
 464         cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
 465         if (!(cfg & DMAC_CFG_ENABLE_MASK))
 466                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 467                              DMAC_CFG_ENABLE_MASK);
 468
 469         return 0;
 470 }
 471
 472 static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
 473 {
 474         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 475         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 476         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 477
 478         /* no more dma descriptors available */
 479         if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
 480                 pr_err("max number of buffers reached\n");
 481                 return -EINVAL;
 482         }
 483
 484         /* get next dma descriptor */
 485         dma_desc += ch_priv->desc_cnt;
 486
 487         /* init dma descriptor */
 488         dma_desc->address = virt_to_phys(dst);
 489         dma_desc->length = size;
 490         dma_desc->status = 0;
 491
 492         /* flush cache */
 493         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 494
 495         /* increment dma descriptors */
 496         ch_priv->desc_cnt++;
 497
 498         return 0;
 499 }
 500
 501 static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
 502                                          size_t size)
 503 {
 504         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 505         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 506
 507         /* only add new rx buffers if channel isn't running */
 508         if (ch_priv->running)
 509                 return bcm6348_iudma_free_rcv_buf(dma, dst, size);
 510         else
 511                 return bcm6348_iudma_add_rcv_buf(dma, dst, size);
 512 }
 513
 514 static const struct dma_ops bcm6348_iudma_ops = {
 515         .disable = bcm6348_iudma_disable,
 516         .enable = bcm6348_iudma_enable,
 517         .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
 518         .request = bcm6348_iudma_request,
 519         .receive = bcm6348_iudma_receive,
 520         .send = bcm6348_iudma_send,
 521 };
 522
 523 static const struct bcm6348_iudma_hw bcm6348_hw = {
 524         .err_mask = (DMAD6348_ST_OV_ERR_MASK |
 525                      DMAD6348_ST_CRC_ERR_MASK |
 526                      DMAD6348_ST_RX_ERR_MASK |
 527                      DMAD6348_ST_OS_ERR_MASK |
 528                      DMAD6348_ST_UN_ERR_MASK),
 529 };
 530
 531 static const struct bcm6348_iudma_hw bcm6368_hw = {
 532         .err_mask = 0,
 533 };
 534
 535 static const struct udevice_id bcm6348_iudma_ids[] = {
 536         {
 537                 .compatible = "brcm,bcm6348-iudma",
 538                 .data = (ulong)&bcm6348_hw,
 539         }, {
 540                 .compatible = "brcm,bcm6368-iudma",
 541                 .data = (ulong)&bcm6368_hw,
 542         }, { /* sentinel */ }
 543 };
 544
 545 static int bcm6348_iudma_probe(struct udevice *dev)
 546 {
 547         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 548         struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
 549         const struct bcm6348_iudma_hw *hw =
 550                 (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
 551         uint8_t ch;
 552         int i;
 553
 554         uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
 555                               DMA_SUPPORTS_MEM_TO_DEV);
 556         priv->hw = hw;
 557
 558         /* dma global base address */
 559         priv->base = dev_remap_addr_name(dev, "dma");
 560         if (!priv->base)
 561                 return -EINVAL;
 562
 563         /* dma channels base address */
 564         priv->chan = dev_remap_addr_name(dev, "dma-channels");
 565         if (!priv->chan)
 566                 return -EINVAL;
 567
 568         /* dma sram base address */
 569         priv->sram = dev_remap_addr_name(dev, "dma-sram");
 570         if (!priv->sram)
 571                 return -EINVAL;
 572
 573         /* get number of channels */
 574         priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
 575         if (priv->n_channels > DMA_CHAN_MAX)
 576                 return -EINVAL;
 577
 578         /* try to enable clocks */
 579         for (i = 0; ; i++) {
 580                 struct clk clk;
 581                 int ret;
 582
 583                 ret = clk_get_by_index(dev, i, &clk);
 584                 if (ret < 0)
 585                         break;
 586
 587                 ret = clk_enable(&clk);
 588                 if (ret < 0) {
 589                         pr_err("error enabling clock %d\n", i);
 590                         return ret;
 591                 }
 592
 593                 ret = clk_free(&clk);
 594                 if (ret < 0) {
 595                         pr_err("error freeing clock %d\n", i);
 596                         return ret;
 597                 }
 598         }
 599
 600         /* try to perform resets */
 601         for (i = 0; ; i++) {
 602                 struct reset_ctl reset;
 603                 int ret;
 604
 605                 ret = reset_get_by_index(dev, i, &reset);
 606                 if (ret < 0)
 607                         break;
 608
 609                 ret = reset_deassert(&reset);
 610                 if (ret < 0) {
 611                         pr_err("error deasserting reset %d\n", i);
 612                         return ret;
 613                 }
 614
 615                 ret = reset_free(&reset);
 616                 if (ret < 0) {
 617                         pr_err("error freeing reset %d\n", i);
 618                         return ret;
 619                 }
 620         }
 621
 622         /* disable dma controller */
 623         clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 624
 625         /* alloc channel private data pointers */
 626         priv->ch_priv = calloc(priv->n_channels,
 627                                sizeof(struct bcm6348_chan_priv*));
 628         if (!priv->ch_priv)
 629                 return -ENOMEM;
 630
 631         /* stop dma channels */
 632         for (ch = 0; ch < priv->n_channels; ch++)
 633                 bcm6348_iudma_chan_stop(priv, ch);
 634
 635         /* enable dma controller */
 636         setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 637
 638         return 0;
 639 }
 640
 641 U_BOOT_DRIVER(bcm6348_iudma) = {
 642         .name = "bcm6348_iudma",
 643         .id = UCLASS_DMA,
 644         .of_match = bcm6348_iudma_ids,
 645         .ops = &bcm6348_iudma_ops,
 646         .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
 647         .probe = bcm6348_iudma_probe,
 648 };