drivers/dma/bcm6348-iudma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
   4  *
   5  * Derived from linux/drivers/dma/bcm63xx-iudma.c:
   6  *      Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
   7  *
   8  * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
   9  *      Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  10  *
  11  * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h:
  12  *      Copyright (C) 2000-2010 Broadcom Corporation
  13  *
  14  * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c:
  15  *      Copyright (C) 2010 Broadcom Corporation
  16  */
  17
  18 #include <common.h>
  19 #include <clk.h>
  20 #include <cpu_func.h>
  21 #include <dm.h>
  22 #include <dma-uclass.h>
  23 #include <memalign.h>
  24 #include <reset.h>
  25 #include <asm/io.h>
  26
  27 #define DMA_RX_DESC     6
  28 #define DMA_TX_DESC     1
  29
  30 /* DMA Channels */
  31 #define DMA_CHAN_FLOWC(x)               ((x) >> 1)
  32 #define DMA_CHAN_MAX                    16
  33 #define DMA_CHAN_SIZE                   0x10
  34 #define DMA_CHAN_TOUT                   500
  35
  36 /* DMA Global Configuration register */
  37 #define DMA_CFG_REG                     0x00
  38 #define  DMA_CFG_ENABLE_SHIFT           0
  39 #define  DMA_CFG_ENABLE_MASK            (1 << DMA_CFG_ENABLE_SHIFT)
  40 #define  DMA_CFG_FLOWC_ENABLE(x)        BIT(DMA_CHAN_FLOWC(x) + 1)
  41 #define  DMA_CFG_NCHANS_SHIFT           24
  42 #define  DMA_CFG_NCHANS_MASK            (0xf << DMA_CFG_NCHANS_SHIFT)
  43
  44 /* DMA Global Flow Control registers */
  45 #define DMA_FLOWC_THR_LO_REG(x)         (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
  46 #define DMA_FLOWC_THR_HI_REG(x)         (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
  47 #define DMA_FLOWC_ALLOC_REG(x)          (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
  48 #define  DMA_FLOWC_ALLOC_FORCE_SHIFT    31
  49 #define  DMA_FLOWC_ALLOC_FORCE_MASK     (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
  50
  51 /* DMA Global Reset register */
  52 #define DMA_RST_REG                     0x34
  53 #define  DMA_RST_CHAN_SHIFT             0
  54 #define  DMA_RST_CHAN_MASK(x)           (1 << x)
  55
  56 /* DMA Channel Configuration register */
  57 #define DMAC_CFG_REG(x)                 (DMA_CHAN_SIZE * (x) + 0x00)
  58 #define  DMAC_CFG_ENABLE_SHIFT          0
  59 #define  DMAC_CFG_ENABLE_MASK           (1 << DMAC_CFG_ENABLE_SHIFT)
  60 #define  DMAC_CFG_PKT_HALT_SHIFT        1
  61 #define  DMAC_CFG_PKT_HALT_MASK         (1 << DMAC_CFG_PKT_HALT_SHIFT)
  62 #define  DMAC_CFG_BRST_HALT_SHIFT       2
  63 #define  DMAC_CFG_BRST_HALT_MASK        (1 << DMAC_CFG_BRST_HALT_SHIFT)
  64
  65 /* DMA Channel Max Burst Length register */
  66 #define DMAC_BURST_REG(x)               (DMA_CHAN_SIZE * (x) + 0x0c)
  67
  68 /* DMA SRAM Descriptor Ring Start register */
  69 #define DMAS_RSTART_REG(x)              (DMA_CHAN_SIZE * (x) + 0x00)
  70
  71 /* DMA SRAM State/Bytes done/ring offset register */
  72 #define DMAS_STATE_DATA_REG(x)          (DMA_CHAN_SIZE * (x) + 0x04)
  73
  74 /* DMA SRAM Buffer Descriptor status and length register */
  75 #define DMAS_DESC_LEN_STATUS_REG(x)     (DMA_CHAN_SIZE * (x) + 0x08)
  76
  77 /* DMA SRAM Buffer Descriptor status and length register */
  78 #define DMAS_DESC_BASE_BUFPTR_REG(x)    (DMA_CHAN_SIZE * (x) + 0x0c)
  79
  80 /* DMA Descriptor Status */
  81 #define DMAD_ST_CRC_SHIFT               8
  82 #define DMAD_ST_CRC_MASK                (1 << DMAD_ST_CRC_SHIFT)
  83 #define DMAD_ST_WRAP_SHIFT              12
  84 #define DMAD_ST_WRAP_MASK               (1 << DMAD_ST_WRAP_SHIFT)
  85 #define DMAD_ST_SOP_SHIFT               13
  86 #define DMAD_ST_SOP_MASK                (1 << DMAD_ST_SOP_SHIFT)
  87 #define DMAD_ST_EOP_SHIFT               14
  88 #define DMAD_ST_EOP_MASK                (1 << DMAD_ST_EOP_SHIFT)
  89 #define DMAD_ST_OWN_SHIFT               15
  90 #define DMAD_ST_OWN_MASK                (1 << DMAD_ST_OWN_SHIFT)
  91
  92 #define DMAD6348_ST_OV_ERR_SHIFT        0
  93 #define DMAD6348_ST_OV_ERR_MASK         (1 << DMAD6348_ST_OV_ERR_SHIFT)
  94 #define DMAD6348_ST_CRC_ERR_SHIFT       1
  95 #define DMAD6348_ST_CRC_ERR_MASK        (1 << DMAD6348_ST_CRC_ERR_SHIFT)
  96 #define DMAD6348_ST_RX_ERR_SHIFT        2
  97 #define DMAD6348_ST_RX_ERR_MASK         (1 << DMAD6348_ST_RX_ERR_SHIFT)
  98 #define DMAD6348_ST_OS_ERR_SHIFT        4
  99 #define DMAD6348_ST_OS_ERR_MASK         (1 << DMAD6348_ST_OS_ERR_SHIFT)
 100 #define DMAD6348_ST_UN_ERR_SHIFT        9
 101 #define DMAD6348_ST_UN_ERR_MASK         (1 << DMAD6348_ST_UN_ERR_SHIFT)
 102
 103 struct bcm6348_dma_desc {
 104         uint16_t length;
 105         uint16_t status;
 106         uint32_t address;
 107 };
 108
 109 struct bcm6348_chan_priv {
 110         void __iomem *dma_ring;
 111         uint8_t dma_ring_size;
 112         uint8_t desc_id;
 113         uint8_t desc_cnt;
 114         bool *busy_desc;
 115         bool running;
 116 };
 117
 118 struct bcm6348_iudma_hw {
 119         uint16_t err_mask;
 120 };
 121
 122 struct bcm6348_iudma_priv {
 123         const struct bcm6348_iudma_hw *hw;
 124         void __iomem *base;
 125         void __iomem *chan;
 126         void __iomem *sram;
 127         struct bcm6348_chan_priv **ch_priv;
 128         uint8_t n_channels;
 129 };
 130
 131 static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
 132 {
 133         return !(ch & 1);
 134 }
 135
 136 static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
 137 {
 138         ulong start = (ulong) ptr;
 139
 140         flush_dcache_range(start, start + size);
 141 }
 142
 143 static inline void bcm6348_iudma_idc(void *ptr, ulong size)
 144 {
 145         ulong start = (ulong) ptr;
 146
 147         invalidate_dcache_range(start, start + size);
 148 }
 149
 150 static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
 151                                     uint8_t ch)
 152 {
 153         unsigned int timeout = DMA_CHAN_TOUT;
 154
 155         do {
 156                 uint32_t cfg, halt;
 157
 158                 if (timeout > DMA_CHAN_TOUT / 2)
 159                         halt = DMAC_CFG_PKT_HALT_MASK;
 160                 else
 161                         halt = DMAC_CFG_BRST_HALT_MASK;
 162
 163                 /* try to stop dma channel */
 164                 writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
 165                 mb();
 166
 167                 /* check if channel was stopped */
 168                 cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
 169                 if (!(cfg & DMAC_CFG_ENABLE_MASK))
 170                         break;
 171
 172                 udelay(1);
 173         } while (--timeout);
 174
 175         if (!timeout)
 176                 pr_err("unable to stop channel %u\n", ch);
 177
 178         /* reset dma channel */
 179         setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 180         mb();
 181         clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
 182 }
 183
 184 static int bcm6348_iudma_disable(struct dma *dma)
 185 {
 186         struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 187         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 188
 189         /* stop dma channel */
 190         bcm6348_iudma_chan_stop(priv, dma->id);
 191
 192         /* dma flow control */
 193         if (bcm6348_iudma_chan_is_rx(dma->id))
 194                 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
 195                           DMA_FLOWC_ALLOC_REG(dma->id));
 196
 197         /* init channel config */
 198         ch_priv->running = false;
 199         ch_priv->desc_id = 0;
 200         if (bcm6348_iudma_chan_is_rx(dma->id))
 201                 ch_priv->desc_cnt = 0;
 202         else
 203                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 204
 205         return 0;
 206 }
 207
 208 static int bcm6348_iudma_enable(struct dma *dma)
 209 {
 210         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 211         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 212         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 213         uint8_t i;
 214
 215         /* dma ring init */
 216         for (i = 0; i < ch_priv->desc_cnt; i++) {
 217                 if (bcm6348_iudma_chan_is_rx(dma->id)) {
 218                         ch_priv->busy_desc[i] = false;
 219                         dma_desc->status |= DMAD_ST_OWN_MASK;
 220                 } else {
 221                         dma_desc->status = 0;
 222                         dma_desc->length = 0;
 223                         dma_desc->address = 0;
 224                 }
 225
 226                 if (i == ch_priv->desc_cnt - 1)
 227                         dma_desc->status |= DMAD_ST_WRAP_MASK;
 228
 229                 dma_desc++;
 230         }
 231
 232         /* init to first descriptor */
 233         ch_priv->desc_id = 0;
 234
 235         /* force cache writeback */
 236         bcm6348_iudma_fdc(ch_priv->dma_ring,
 237                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 238
 239         /* clear sram */
 240         writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
 241         writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
 242         writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
 243
 244         /* set dma ring start */
 245         writel_be(virt_to_phys(ch_priv->dma_ring),
 246                   priv->sram + DMAS_RSTART_REG(dma->id));
 247
 248         /* set flow control */
 249         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 250                 u32 val;
 251
 252                 setbits_be32(priv->base + DMA_CFG_REG,
 253                              DMA_CFG_FLOWC_ENABLE(dma->id));
 254
 255                 val = ch_priv->desc_cnt / 3;
 256                 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
 257
 258                 val = (ch_priv->desc_cnt * 2) / 3;
 259                 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
 260
 261                 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
 262         }
 263
 264         /* set dma max burst */
 265         writel_be(ch_priv->desc_cnt,
 266                   priv->chan + DMAC_BURST_REG(dma->id));
 267
 268         /* kick rx dma channel */
 269         if (bcm6348_iudma_chan_is_rx(dma->id))
 270                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 271                              DMAC_CFG_ENABLE_MASK);
 272
 273         /* channel is now enabled */
 274         ch_priv->running = true;
 275
 276         return 0;
 277 }
 278
 279 static int bcm6348_iudma_request(struct dma *dma)
 280 {
 281         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 282         struct bcm6348_chan_priv *ch_priv;
 283
 284         /* check if channel is valid */
 285         if (dma->id >= priv->n_channels)
 286                 return -ENODEV;
 287
 288         /* alloc channel private data */
 289         priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
 290         if (!priv->ch_priv[dma->id])
 291                 return -ENOMEM;
 292         ch_priv = priv->ch_priv[dma->id];
 293
 294         /* alloc dma ring */
 295         if (bcm6348_iudma_chan_is_rx(dma->id))
 296                 ch_priv->dma_ring_size = DMA_RX_DESC;
 297         else
 298                 ch_priv->dma_ring_size = DMA_TX_DESC;
 299
 300         ch_priv->dma_ring =
 301                 malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
 302                                      ch_priv->dma_ring_size);
 303         if (!ch_priv->dma_ring)
 304                 return -ENOMEM;
 305
 306         /* init channel config */
 307         ch_priv->running = false;
 308         ch_priv->desc_id = 0;
 309         if (bcm6348_iudma_chan_is_rx(dma->id)) {
 310                 ch_priv->desc_cnt = 0;
 311                 ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
 312         } else {
 313                 ch_priv->desc_cnt = ch_priv->dma_ring_size;
 314                 ch_priv->busy_desc = NULL;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
 321 {
 322         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 323         const struct bcm6348_iudma_hw *hw = priv->hw;
 324         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 325         struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
 326         int ret;
 327
 328         if (!ch_priv->running)
 329                 return -EINVAL;
 330
 331         /* get dma ring descriptor address */
 332         dma_desc += ch_priv->desc_id;
 333
 334         /* invalidate cache data */
 335         bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 336
 337         /* check dma own */
 338         if (dma_desc->status & DMAD_ST_OWN_MASK)
 339                 return -EAGAIN;
 340
 341         /* check pkt */
 342         if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
 343             !(dma_desc->status & DMAD_ST_SOP_MASK) ||
 344             (dma_desc->status & hw->err_mask)) {
 345                 pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
 346                        dma->id, ch_priv->desc_id, dma_desc->status);
 347                 ret = -EAGAIN;
 348         } else {
 349                 /* set dma buffer address */
 350                 *dst = phys_to_virt(dma_desc->address);
 351
 352                 /* invalidate cache data */
 353                 bcm6348_iudma_idc(*dst, dma_desc->length);
 354
 355                 /* return packet length */
 356                 ret = dma_desc->length;
 357         }
 358
 359         /* busy dma descriptor */
 360         ch_priv->busy_desc[ch_priv->desc_id] = true;
 361
 362         /* increment dma descriptor */
 363         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 364
 365         return ret;
 366 }
 367
 368 static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
 369                               void *metadata)
 370 {
 371         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 372         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 373         struct bcm6348_dma_desc *dma_desc;
 374         uint16_t status;
 375
 376         if (!ch_priv->running)
 377                 return -EINVAL;
 378
 379         /* flush cache */
 380         bcm6348_iudma_fdc(src, len);
 381
 382         /* get dma ring descriptor address */
 383         dma_desc = ch_priv->dma_ring;
 384         dma_desc += ch_priv->desc_id;
 385
 386         /* config dma descriptor */
 387         status = (DMAD_ST_OWN_MASK |
 388                   DMAD_ST_EOP_MASK |
 389                   DMAD_ST_CRC_MASK |
 390                   DMAD_ST_SOP_MASK);
 391         if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
 392                 status |= DMAD_ST_WRAP_MASK;
 393
 394         /* set dma descriptor */
 395         dma_desc->address = virt_to_phys(src);
 396         dma_desc->length = len;
 397         dma_desc->status = status;
 398
 399         /* flush cache */
 400         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 401
 402         /* kick tx dma channel */
 403         setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
 404
 405         /* poll dma status */
 406         do {
 407                 /* invalidate cache */
 408                 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
 409
 410                 if (!(dma_desc->status & DMAD_ST_OWN_MASK))
 411                         break;
 412         } while(1);
 413
 414         /* increment dma descriptor */
 415         ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
 416
 417         return 0;
 418 }
 419
 420 static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
 421 {
 422         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 423         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 424         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 425         uint16_t status;
 426         uint8_t i;
 427         u32 cfg;
 428
 429         /* get dirty dma descriptor */
 430         for (i = 0; i < ch_priv->desc_cnt; i++) {
 431                 if (phys_to_virt(dma_desc->address) == dst)
 432                         break;
 433
 434                 dma_desc++;
 435         }
 436
 437         /* dma descriptor not found */
 438         if (i == ch_priv->desc_cnt) {
 439                 pr_err("dirty dma descriptor not found\n");
 440                 return -ENOENT;
 441         }
 442
 443         /* invalidate cache */
 444         bcm6348_iudma_idc(ch_priv->dma_ring,
 445                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 446
 447         /* free dma descriptor */
 448         ch_priv->busy_desc[i] = false;
 449
 450         status = DMAD_ST_OWN_MASK;
 451         if (i == ch_priv->desc_cnt - 1)
 452                 status |= DMAD_ST_WRAP_MASK;
 453
 454         dma_desc->status |= status;
 455         dma_desc->length = PKTSIZE_ALIGN;
 456
 457         /* tell dma we allocated one buffer */
 458         writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
 459
 460         /* flush cache */
 461         bcm6348_iudma_fdc(ch_priv->dma_ring,
 462                           sizeof(*dma_desc) * ch_priv->desc_cnt);
 463
 464         /* kick rx dma channel if disabled */
 465         cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
 466         if (!(cfg & DMAC_CFG_ENABLE_MASK))
 467                 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
 468                              DMAC_CFG_ENABLE_MASK);
 469
 470         return 0;
 471 }
 472
 473 static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
 474 {
 475         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 476         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 477         struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
 478
 479         /* no more dma descriptors available */
 480         if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
 481                 pr_err("max number of buffers reached\n");
 482                 return -EINVAL;
 483         }
 484
 485         /* get next dma descriptor */
 486         dma_desc += ch_priv->desc_cnt;
 487
 488         /* init dma descriptor */
 489         dma_desc->address = virt_to_phys(dst);
 490         dma_desc->length = size;
 491         dma_desc->status = 0;
 492
 493         /* flush cache */
 494         bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
 495
 496         /* increment dma descriptors */
 497         ch_priv->desc_cnt++;
 498
 499         return 0;
 500 }
 501
 502 static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
 503                                          size_t size)
 504 {
 505         const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
 506         struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
 507
 508         /* only add new rx buffers if channel isn't running */
 509         if (ch_priv->running)
 510                 return bcm6348_iudma_free_rcv_buf(dma, dst, size);
 511         else
 512                 return bcm6348_iudma_add_rcv_buf(dma, dst, size);
 513 }
 514
 515 static const struct dma_ops bcm6348_iudma_ops = {
 516         .disable = bcm6348_iudma_disable,
 517         .enable = bcm6348_iudma_enable,
 518         .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
 519         .request = bcm6348_iudma_request,
 520         .receive = bcm6348_iudma_receive,
 521         .send = bcm6348_iudma_send,
 522 };
 523
 524 static const struct bcm6348_iudma_hw bcm6348_hw = {
 525         .err_mask = (DMAD6348_ST_OV_ERR_MASK |
 526                      DMAD6348_ST_CRC_ERR_MASK |
 527                      DMAD6348_ST_RX_ERR_MASK |
 528                      DMAD6348_ST_OS_ERR_MASK |
 529                      DMAD6348_ST_UN_ERR_MASK),
 530 };
 531
 532 static const struct bcm6348_iudma_hw bcm6368_hw = {
 533         .err_mask = 0,
 534 };
 535
 536 static const struct udevice_id bcm6348_iudma_ids[] = {
 537         {
 538                 .compatible = "brcm,bcm6348-iudma",
 539                 .data = (ulong)&bcm6348_hw,
 540         }, {
 541                 .compatible = "brcm,bcm6368-iudma",
 542                 .data = (ulong)&bcm6368_hw,
 543         }, { /* sentinel */ }
 544 };
 545
 546 static int bcm6348_iudma_probe(struct udevice *dev)
 547 {
 548         struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 549         struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
 550         const struct bcm6348_iudma_hw *hw =
 551                 (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
 552         uint8_t ch;
 553         int i;
 554
 555         uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
 556                               DMA_SUPPORTS_MEM_TO_DEV);
 557         priv->hw = hw;
 558
 559         /* dma global base address */
 560         priv->base = dev_remap_addr_name(dev, "dma");
 561         if (!priv->base)
 562                 return -EINVAL;
 563
 564         /* dma channels base address */
 565         priv->chan = dev_remap_addr_name(dev, "dma-channels");
 566         if (!priv->chan)
 567                 return -EINVAL;
 568
 569         /* dma sram base address */
 570         priv->sram = dev_remap_addr_name(dev, "dma-sram");
 571         if (!priv->sram)
 572                 return -EINVAL;
 573
 574         /* get number of channels */
 575         priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
 576         if (priv->n_channels > DMA_CHAN_MAX)
 577                 return -EINVAL;
 578
 579         /* try to enable clocks */
 580         for (i = 0; ; i++) {
 581                 struct clk clk;
 582                 int ret;
 583
 584                 ret = clk_get_by_index(dev, i, &clk);
 585                 if (ret < 0)
 586                         break;
 587
 588                 ret = clk_enable(&clk);
 589                 if (ret < 0) {
 590                         pr_err("error enabling clock %d\n", i);
 591                         return ret;
 592                 }
 593
 594                 ret = clk_free(&clk);
 595                 if (ret < 0) {
 596                         pr_err("error freeing clock %d\n", i);
 597                         return ret;
 598                 }
 599         }
 600
 601         /* try to perform resets */
 602         for (i = 0; ; i++) {
 603                 struct reset_ctl reset;
 604                 int ret;
 605
 606                 ret = reset_get_by_index(dev, i, &reset);
 607                 if (ret < 0)
 608                         break;
 609
 610                 ret = reset_deassert(&reset);
 611                 if (ret < 0) {
 612                         pr_err("error deasserting reset %d\n", i);
 613                         return ret;
 614                 }
 615
 616                 ret = reset_free(&reset);
 617                 if (ret < 0) {
 618                         pr_err("error freeing reset %d\n", i);
 619                         return ret;
 620                 }
 621         }
 622
 623         /* disable dma controller */
 624         clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 625
 626         /* alloc channel private data pointers */
 627         priv->ch_priv = calloc(priv->n_channels,
 628                                sizeof(struct bcm6348_chan_priv*));
 629         if (!priv->ch_priv)
 630                 return -ENOMEM;
 631
 632         /* stop dma channels */
 633         for (ch = 0; ch < priv->n_channels; ch++)
 634                 bcm6348_iudma_chan_stop(priv, ch);
 635
 636         /* enable dma controller */
 637         setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
 638
 639         return 0;
 640 }
 641
 642 U_BOOT_DRIVER(bcm6348_iudma) = {
 643         .name = "bcm6348_iudma",
 644         .id = UCLASS_DMA,
 645         .of_match = bcm6348_iudma_ids,
 646         .ops = &bcm6348_iudma_ops,
 647         .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv),
 648         .probe = bcm6348_iudma_probe,
 649 };