1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
10 * For controllers that have two XOR units, then chans 2 & 3 will be mapped
11 * to channels 0 & 1 of unit 1
13 #define XOR_UNIT(chan) ((chan) >> 1)
14 #define XOR_CHAN(chan) ((chan) & 1)
16 #ifdef CONFIG_ARMADA_MSYS
17 #define MV_XOR_REGS_OFFSET(unit) (0xF0800)
19 #define MV_XOR_REGS_OFFSET(unit) (0x60900)
21 #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
23 /* XOR Engine Control Register Map */
24 #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit))
25 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4)))
26 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4)))
28 /* XOR Engine Interrupt Register Map */
29 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30)
30 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40)
31 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50)
32 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60)
34 /* XOR Engine Descriptor Register Map */
35 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4)))
36 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4)))
37 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4)))
39 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4)))
40 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4)))
41 #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0)
42 #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4)
43 #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8)
44 #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0)
45 #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4)
47 /* XOR register fileds */
49 /* XOR Engine [0..1] Configuration Registers (XExCR) */
50 #define XEXCR_OPERATION_MODE_OFFS (0)
51 #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS)
52 #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS)
53 #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS)
54 #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS)
55 #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS)
56 #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS)
58 #define XEXCR_SRC_BURST_LIMIT_OFFS (4)
59 #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS)
60 #define XEXCR_DST_BURST_LIMIT_OFFS (8)
61 #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS)
62 #define XEXCR_DRD_RES_SWP_OFFS (12)
63 #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS)
64 #define XEXCR_DWR_REQ_SWP_OFFS (13)
65 #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS)
66 #define XEXCR_DES_SWP_OFFS (14)
67 #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS)
68 #define XEXCR_REG_ACC_PROTECT_OFFS (15)
69 #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS)
71 /* XOR Engine [0..1] Activation Registers (XExACTR) */
72 #define XEXACTR_XESTART_OFFS (0)
73 #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS)
74 #define XEXACTR_XESTOP_OFFS (1)
75 #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS)
76 #define XEXACTR_XEPAUSE_OFFS (2)
77 #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS)
78 #define XEXACTR_XERESTART_OFFS (3)
79 #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS)
80 #define XEXACTR_XESTATUS_OFFS (4)
81 #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS)
82 #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS)
83 #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS)
84 #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS)
86 /* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */
87 #define XEXDPR_DST_PTR_OFFS (0)
88 #define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS)
89 #define XEXDPR_DST_PTR_XOR_MASK (0x3F)
90 #define XEXDPR_DST_PTR_DMA_MASK (0x1F)
91 #define XEXDPR_DST_PTR_CRC_MASK (0x1F)
93 /* XOR Engine[0..1] Block Size Registers (XExBSR) */
94 #define XEXBSR_BLOCK_SIZE_OFFS (0)
95 #define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS)
96 #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128)
97 #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF)
99 /* XOR Engine Address Decoding Register Map */
100 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4)))
101 #define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4)))
102 #define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4)))
103 #define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4)))
104 #define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4)))
106 #endif /* __XOR_REGS_H */