1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
13 #include "ddr3_hw_training.h"
17 static void ddr3_flush_l1_line(u32 line);
19 extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
20 extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
21 #if defined(MV88F78X60)
22 extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
24 extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
26 #if defined(MV88F78X60) || defined(MV88F672X)
27 /* PBS locked dq (per pup) */
28 u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
29 u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
30 u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
32 int per_bit_data[MAX_PUP_NUM][DQ_NUM];
35 static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
37 static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
39 #define XOR_TIMEOUT 0x8000000
41 struct xor_channel_t {
42 struct crc_dma_desc *desc;
43 unsigned long desc_phys_addr;
46 #define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
48 void xor_waiton_eng(int chan)
53 while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
54 XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
55 if (timeout > XOR_TIMEOUT)
62 while (mv_xor_state_get(chan) != MV_IDLE) {
63 if (timeout > XOR_TIMEOUT)
70 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
71 ~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
77 static int special_compare_pattern(u32 uj)
79 if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
80 (uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
87 * Compare code extracted as its used by multiple functions. This
88 * reduces code-size and makes it easier to maintain it. Additionally
89 * the code is not indented that much and therefore easier to read.
91 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
92 u32 pup_groups, int debug_dqs)
98 __maybe_unused u32 dq;
100 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
101 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
102 val = CMP_BYTE_SHIFT * uk;
103 var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
104 var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
107 *pup |= (1 << (uk + (PUP_NUM_32BIT *
108 (uj % pup_groups))));
114 for (dq = 0; dq < DQ_NUM; dq++) {
115 val = uk + (PUP_NUM_32BIT *
117 if (((var1 >> dq) & 0x1) !=
118 ((var2 >> dq) & 0x1))
119 per_bit_data[val][dq] = 1;
121 per_bit_data[val][dq] = 0;
129 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
136 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
138 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
139 val = CMP_BYTE_SHIFT * uk;
140 var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
141 var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
143 *pup |= (1 << (uk % PUP_NUM_16BIT));
149 * Name: ddr3_sdram_compare
150 * Desc: Execute compare per PUP
151 * Args: unlock_pup Bit array of the unlock pups
152 * new_locked_pup Output bit array of the pups with failed compare
153 * pattern Pattern to compare
154 * pattern_len Length of pattern (in bytes)
155 * sdram_offset offset address to the SDRAM
156 * write write to the SDRAM before read
157 * mask compare pattern with mask;
158 * mask_pattern Mask to compare pattern
161 * Returns: MV_OK if success, other error code if fail.
163 int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
164 u32 *new_locked_pup, u32 *pattern,
165 u32 pattern_len, u32 sdram_offset, int write,
166 int mask, u32 *mask_pattern,
170 __maybe_unused u32 pup_groups;
171 __maybe_unused u32 dq;
173 #if !defined(MV88F67XX)
174 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
180 ddr3_reset_phy_read_fifo();
182 /* Check if need to write to sdram before read */
184 ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
186 ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
188 /* Compare read result to write */
189 for (uj = 0; uj < pattern_len; uj++) {
190 if (special_compare && special_compare_pattern(uj))
193 #if defined(MV88F78X60) || defined(MV88F672X)
194 compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
195 #elif defined(MV88F67XX)
196 compare_pattern_v2(uj, new_locked_pup, pattern);
203 #if defined(MV88F78X60) || defined(MV88F672X)
205 * Name: ddr3_sdram_dm_compare
206 * Desc: Execute compare per PUP
207 * Args: unlock_pup Bit array of the unlock pups
208 * new_locked_pup Output bit array of the pups with failed compare
209 * pattern Pattern to compare
210 * pattern_len Length of pattern (in bytes)
211 * sdram_offset offset address to the SDRAM
212 * write write to the SDRAM before read
213 * mask compare pattern with mask;
214 * mask_pattern Mask to compare pattern
217 * Returns: MV_OK if success, other error code if fail.
219 int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
220 u32 *new_locked_pup, u32 *pattern,
223 u32 uj, uk, var1, var2, pup_groups;
227 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
232 ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
234 ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
237 /* Validate the correctness of the results */
238 for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
239 compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
241 /* Test the DM Signals */
242 *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
243 *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
245 sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
246 sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
248 for (uj = 0; uj < 2; uj++) {
249 if (((sdram_data[uj]) != (pattern[uj])) &&
250 (*new_locked_pup != 0xFF)) {
251 for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
252 val = CMP_BYTE_SHIFT * uk;
253 var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
254 var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
256 *new_locked_pup |= (1 << (uk +
257 (PUP_NUM_32BIT * (uj % pup_groups))));
258 *new_locked_pup |= pup;
268 * Name: ddr3_sdram_pbs_compare
269 * Desc: Execute SRAM compare per PUP and DQ.
270 * Args: pup_locked bit array of locked pups
271 * is_tx Indicate whether Rx or Tx
272 * pbs_pattern_idx Index of PBS pattern
273 * pbs_curr_val The PBS value
274 * pbs_lock_val The value to set to locked PBS
275 * skew_array Global array to update with the compare results
276 * ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
278 * Returns: MV_OK if success, other error code if fail.
280 int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
281 int is_tx, u32 pbs_pattern_idx,
282 u32 pbs_curr_val, u32 pbs_lock_val,
283 u32 *skew_array, u8 *unlock_pup_dq_array,
286 /* bit array failed dq per pup for current compare */
287 u32 pbs_write_pup[DQ_NUM] = { 0 };
288 u32 update_pup; /* pup as HW convention */
289 u32 max_pup; /* maximal pup index */
293 u32 sdram_offset, pup_groups, tmp_pup;
298 switch (dram_info->ddr_width) {
299 #if defined(MV88F672X)
301 pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
305 pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
307 #if defined(MV88F78X60)
309 pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
316 max_pup = dram_info->num_of_std_pups;
318 sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
320 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
325 ddr3_reset_phy_read_fifo();
327 /* Check if need to write to sdram before read */
329 ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
333 ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
335 /* Compare read result to write */
336 for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
337 if ((sdram_data[ui]) != (pattern_ptr[ui])) {
339 /* error in low pup group */
340 for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
341 val = CMP_BYTE_SHIFT * pup;
342 var1 = ((sdram_data[ui] >> val) &
344 var2 = ((pattern_ptr[ui] >> val) &
348 if (dram_info->ddr_width > 16) {
349 tmp_pup = (pup + PUP_NUM_32BIT *
352 tmp_pup = (pup % PUP_NUM_16BIT);
355 update_pup = (1 << tmp_pup);
356 if (ecc && (update_pup != 0x1))
360 * Pup is failed - Go over all DQs and
363 for (dq = 0; dq < DQ_NUM; dq++) {
364 val = tmp_pup * (1 - ecc) +
366 if (((var1 >> dq) & 0x1) !=
367 ((var2 >> dq) & 0x1)) {
368 if (pbs_locked_dq[val][dq] == 1 &&
369 pbs_locked_value[val][dq] != pbs_curr_val)
382 * unlock_pup_dq_array
384 unlock_pup_dq_array[dq] &=
392 skew_array[tmp_pup * DQ_NUM + dq] =
401 pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
403 /* Set last failed bits PBS to min / max pbs value */
404 for (dq = 0; dq < DQ_NUM; dq++) {
405 for (pup = 0; pup < max_pup; pup++) {
406 if (pbs_write_pup[dq] & (1 << pup)) {
407 val = pup * (1 - ecc) + ecc * ECC_PUP;
408 if (pbs_locked_dq[val][dq] == 1 &&
409 pbs_locked_value[val][dq] != pbs_curr_val)
412 /* Mark the dq as locked */
413 pbs_locked_dq[val][dq] = 1;
414 pbs_locked_value[val][dq] = pbs_curr_val;
415 ddr3_write_pup_reg(pup_addr +
416 pbs_dq_mapping[val][dq],
417 CS0, val, 0, pbs_lock_val);
427 * Name: ddr3_sdram_direct_compare
428 * Desc: Execute compare per PUP without DMA (no burst mode)
429 * Args: unlock_pup Bit array of the unlock pups
430 * new_locked_pup Output bit array of the pups with failed compare
431 * pattern Pattern to compare
432 * pattern_len Length of pattern (in bytes)
433 * sdram_offset offset address to the SDRAM
434 * write write to the SDRAM before read
435 * mask compare pattern with mask;
436 * auiMaskPatter Mask to compare pattern
439 * Returns: MV_OK if success, other error code if fail.
441 int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
442 u32 *new_locked_pup, u32 *pattern,
443 u32 pattern_len, u32 sdram_offset,
444 int write, int mask, u32 *mask_pattern)
446 u32 uj, uk, pup_groups;
447 u32 *sdram_addr; /* used to read from SDRAM */
449 sdram_addr = (u32 *)sdram_offset;
451 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
456 /* Check if need to write before read */
458 for (uk = 0; uk < pattern_len; uk++) {
459 *sdram_addr = pattern[uk];
464 sdram_addr = (u32 *)sdram_offset;
466 for (uk = 0; uk < pattern_len; uk++) {
467 sdram_data[uk] = *sdram_addr;
471 /* Compare read result to write */
472 for (uj = 0; uj < pattern_len; uj++) {
473 if (dram_info->ddr_width > 16) {
474 compare_pattern_v1(uj, new_locked_pup, pattern,
477 compare_pattern_v2(uj, new_locked_pup, pattern);
485 * Name: ddr3_dram_sram_burst
486 * Desc: Read from the SDRAM in burst of 64 bytes
489 * Notes: Using the XOR mechanism
490 * Returns: MV_OK if success, other error code if fail.
492 int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
494 u32 chan, byte_count, cs_num, byte;
495 struct xor_channel_t channel;
498 byte_count = len * 4;
500 /* Wait for previous transfer completion */
501 while (mv_xor_state_get(chan) != MV_IDLE)
504 /* Build the channel descriptor */
505 channel.desc = &dma_desc;
507 /* Enable Address Override and set correct src and dst */
508 if (src < SRAM_BASE) {
509 /* src is DRAM CS, dst is SRAM */
510 cs_num = (src / (1 + SDRAM_CS_SIZE));
511 reg_write(XOR_ADDR_OVRD_REG(0, 0),
512 ((cs_num << 1) | (1 << 0)));
513 channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
514 channel.desc->dst_addr = dst;
516 /* src is SRAM, dst is DRAM CS */
517 cs_num = (dst / (1 + SDRAM_CS_SIZE));
518 reg_write(XOR_ADDR_OVRD_REG(0, 0),
519 ((cs_num << 25) | (1 << 24)));
520 channel.desc->src_addr0 = (src);
521 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
522 channel.desc->src_addr0 = src;
523 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
526 channel.desc->src_addr1 = 0;
527 channel.desc->byte_cnt = byte_count;
528 channel.desc->next_desc_ptr = 0;
529 channel.desc->status = 1 << 31;
530 channel.desc->desc_cmd = 0x0;
531 channel.desc_phys_addr = (unsigned long)&dma_desc;
533 ddr3_flush_l1_line((u32)&dma_desc);
535 /* Issue the transfer */
536 if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
539 /* Wait for completion */
540 xor_waiton_eng(chan);
542 if (dst > SRAM_BASE) {
543 for (byte = 0; byte < byte_count; byte += 0x20)
544 cache_inv(dst + byte);
551 * Name: ddr3_flush_l1_line
555 * Returns: MV_OK if success, other error code if fail.
557 static void ddr3_flush_l1_line(u32 line)
561 #if defined(MV88F672X)
564 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
565 (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
567 reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
574 flush_l1_v7(line + CACHE_LINE_SIZE);
578 flush_l1_v6(line + CACHE_LINE_SIZE);
582 int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
585 u32 *dst_ptr, *src_ptr;
587 dst_ptr = (u32 *)dst;
588 src_ptr = (u32 *)src;
590 for (ui = 0; ui < len; ui++) {
599 int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
600 u32 *new_locked_pup, u32 *pattern,
601 u32 pattern_len, u32 sdram_offset, int write,
602 int mask, u32 *mask_pattern,
607 if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
612 ddr3_reset_phy_read_fifo();
614 /* Check if need to write to sdram before read */
616 ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
618 ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
620 /* Compare read result to write */
621 for (uj = 0; uj < pattern_len; uj++) {
622 if (special_compare && special_compare_pattern(uj))
625 if (dram_info->ddr_width > 16) {
626 compare_pattern_v1(uj, new_locked_pup, pattern,
629 compare_pattern_v2(uj, new_locked_pup, pattern);
636 void ddr3_reset_phy_read_fifo(void)
640 /* reset read FIFO */
641 reg = reg_read(REG_DRAM_TRAINING_ADDR);
642 /* Start Auto Read Leveling procedure */
643 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
645 /* 0x15B0 - Training Register */
646 reg_write(REG_DRAM_TRAINING_ADDR, reg);
648 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
649 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
650 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
652 /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
653 /* 0x15B8 - Training SW 2 Register */
654 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
657 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
658 (1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
659 } while (reg); /* Wait for '0' */
661 reg = reg_read(REG_DRAM_TRAINING_ADDR);
663 /* Clear Auto Read Leveling procedure */
664 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
666 /* 0x15B0 - Training Register */
667 reg_write(REG_DRAM_TRAINING_ADDR, reg);