1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <linux/delay.h>
15 #include "ddr3_init.h"
16 #include "ddr3_hw_training.h"
20 #include "ddr3_patterns_64bit.h"
22 #include "ddr3_patterns_16bit.h"
23 #if defined(MV88F672X)
24 #include "ddr3_patterns_16bit.h"
32 #define DEBUG_MAIN_C(s, d, l) \
33 DEBUG_MAIN_S(s); DEBUG_MAIN_D(d, l); DEBUG_MAIN_S("\n")
34 #define DEBUG_MAIN_FULL_C(s, d, l) \
35 DEBUG_MAIN_FULL_S(s); DEBUG_MAIN_FULL_D(d, l); DEBUG_MAIN_FULL_S("\n")
38 #define DEBUG_MAIN_S(s) puts(s)
39 #define DEBUG_MAIN_D(d, l) printf("%x", d)
41 #define DEBUG_MAIN_S(s)
42 #define DEBUG_MAIN_D(d, l)
45 #ifdef MV_DEBUG_MAIN_FULL
46 #define DEBUG_MAIN_FULL_S(s) puts(s)
47 #define DEBUG_MAIN_FULL_D(d, l) printf("%x", d)
49 #define DEBUG_MAIN_FULL_S(s)
50 #define DEBUG_MAIN_FULL_D(d, l)
53 #ifdef MV_DEBUG_SUSPEND_RESUME
54 #define DEBUG_SUSPEND_RESUME_S(s) puts(s)
55 #define DEBUG_SUSPEND_RESUME_D(d, l) printf("%x", d)
57 #define DEBUG_SUSPEND_RESUME_S(s)
58 #define DEBUG_SUSPEND_RESUME_D(d, l)
61 static u32 ddr3_sw_wl_rl_debug;
62 static u32 ddr3_run_pbs = 1;
64 void ddr3_print_version(void)
66 puts("DDR3 Training Sequence - Ver 5.7.");
69 void ddr3_set_sw_wl_rl_debug(u32 val)
71 ddr3_sw_wl_rl_debug = val;
74 void ddr3_set_pbs(u32 val)
79 int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass,
80 u32 scrub_offs, u32 scrub_size, int dqs_clk_aligned,
81 int debug_mode, int reg_dimm_skip_wl)
83 /* A370 has no PBS mechanism */
84 __maybe_unused u32 first_loop_flag = 0;
86 MV_DRAM_INFO dram_info;
92 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n");
94 memset(&dram_info, 0, sizeof(dram_info));
95 dram_info.num_cs = ddr3_get_cs_num_from_reg();
96 dram_info.cs_ena = ddr3_get_cs_ena_from_reg();
97 dram_info.target_frequency = target_freq;
98 dram_info.ddr_width = ddr_width;
99 dram_info.num_of_std_pups = ddr_width / PUP_SIZE;
100 dram_info.rl400_bug = 0;
101 dram_info.multi_cs_mr_support = 0;
103 dram_info.rl400_bug = 1;
106 /* Ignore ECC errors - if ECC is enabled */
107 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
108 if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) {
109 dram_info.ecc_ena = 1;
110 reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
111 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
113 dram_info.ecc_ena = 0;
116 reg = reg_read(REG_SDRAM_CONFIG_ADDR);
117 if (reg & (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS))
118 dram_info.reg_dimm = 1;
120 dram_info.reg_dimm = 0;
122 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena;
124 /* Get target 2T value */
125 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
126 dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) &
127 REG_DUNIT_CTRL_LOW_2T_MASK;
129 /* Get target CL value */
131 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2;
133 reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2;
136 reg = (((reg >> 1) & 0xE) | (reg & 0x1)) & 0xF;
137 dram_info.cl = ddr3_valid_cl_to_cl(reg);
139 /* Get target CWL value */
141 reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
143 reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
146 reg &= REG_DDR3_MR2_CWL_MASK;
148 #if !defined(MV88F67XX)
149 /* A370 has no PBS mechanism */
150 #if defined(MV88F78X60)
151 if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs))
154 /* first_loop_flag = 1; skip mid freq at ALP/A375 */
155 if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs) &&
156 (mv_ctrl_revision_get() >= UMC_A0))
163 freq = dram_info.target_frequency;
165 /* Set ODT to always on */
166 ddr3_odt_activate(1);
169 mv_sys_xor_init(&dram_info);
171 /* Get DRAM/HCLK ratio */
172 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
176 * Xor Bypass - ECC support in AXP is currently available for 1:1
177 * modes frequency modes.
178 * Not all frequency modes support the ddr3 training sequence
180 * Xor Bypass allows using the Xor initializations and scrubbing
181 * inside the ddr3 training sequence without running the training
184 if (xor_bypass == 0) {
186 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n");
188 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n");
191 if (dram_info.target_frequency > DFS_MARGIN) {
195 if (dram_info.reg_dimm == 1)
198 if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) {
199 /* Set low - 100Mhz DDR Frequency by HW */
200 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n");
201 return MV_DDR3_TRAINING_ERR_DFS_H2L;
204 if ((dram_info.reg_dimm == 1) &&
205 (reg_dimm_skip_wl == 0)) {
207 ddr3_write_leveling_hw_reg_dimm(freq,
209 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n");
212 if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
213 ddr3_print_freq(freq);
216 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 2\n");
218 if (!dqs_clk_aligned) {
221 * If running training sequence without DFS,
222 * we must run Write leveling before writing
227 * ODT - Multi CS system use SW WL,
228 * Single CS System use HW WL
230 if (dram_info.cs_ena > 1) {
232 ddr3_write_leveling_sw(
235 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
236 return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
240 ddr3_write_leveling_hw(freq,
242 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
243 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
247 if (MV_OK != ddr3_write_leveling_hw(
249 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
250 if (ddr3_sw_wl_rl_debug) {
252 ddr3_write_leveling_sw(
255 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
256 return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
259 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
266 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 3\n");
269 if (MV_OK != ddr3_load_patterns(&dram_info, 0)) {
270 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Loading Patterns)\n");
271 return MV_DDR3_TRAINING_ERR_LOAD_PATTERNS;
276 * The mainline U-Boot port of the bin_hdr DDR training code
277 * needs a delay of minimum 20ms here (10ms is a bit too short
278 * and the CPU hangs). The bin_hdr code doesn't have this delay.
279 * To be save here, lets add a delay of 50ms here.
281 * Tested on the Marvell DB-MV784MP-GP board
286 freq = dram_info.target_frequency;
287 tmp_ratio = ratio_2to1;
288 DEBUG_MAIN_FULL_S("DDR3 Training Sequence - DEBUG - 4\n");
290 #if defined(MV88F78X60)
292 * There is a difference on the DFS frequency at the
293 * first iteration of this loop
295 if (first_loop_flag) {
301 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio,
303 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs Low2High)\n");
304 return MV_DDR3_TRAINING_ERR_DFS_H2L;
307 if (ddr3_get_log_level() >= MV_LOG_LEVEL_1) {
308 ddr3_print_freq(freq);
312 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 5\n");
315 if (!dqs_clk_aligned) {
318 * ODT - Multi CS system that not support Multi
319 * CS MRS commands must use SW WL
321 if (dram_info.cs_ena > 1) {
322 if (MV_OK != ddr3_write_leveling_sw(
323 freq, tmp_ratio, &dram_info)) {
324 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
325 return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
328 if (MV_OK != ddr3_write_leveling_hw(
330 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
331 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
335 if ((dram_info.reg_dimm == 1) &&
337 if (reg_dimm_skip_wl == 0) {
338 if (MV_OK != ddr3_write_leveling_hw_reg_dimm(
340 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM WL - SKIP\n");
343 if (MV_OK != ddr3_write_leveling_hw(
345 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
346 if (ddr3_sw_wl_rl_debug) {
347 if (MV_OK != ddr3_write_leveling_sw(
348 freq, tmp_ratio, &dram_info)) {
349 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
350 return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
353 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
360 ("DDR3 Training Sequence - DEBUG - 6\n");
365 * Armada 370 - Support for HCLK @ 400MHZ - must use
368 if (freq == DDR_400 && dram_info.rl400_bug) {
369 status = ddr3_read_leveling_sw(freq, tmp_ratio,
371 if (MV_OK != status) {
373 ("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n");
377 if (MV_OK != ddr3_read_leveling_hw(
379 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Hw)\n");
380 if (ddr3_sw_wl_rl_debug) {
381 if (MV_OK != ddr3_read_leveling_sw(
384 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n");
385 return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
388 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
394 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 7\n");
396 if (MV_OK != ddr3_wl_supplement(&dram_info)) {
397 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hi-Freq Sup)\n");
398 return MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ;
402 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 8\n");
403 #if !defined(MV88F67XX)
404 /* A370 has no PBS mechanism */
405 #if defined(MV88F78X60) || defined(MV88F672X)
406 if (first_loop_flag == 1) {
410 status = ddr3_pbs_rx(&dram_info);
411 if (MV_OK != status) {
412 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS RX)\n");
417 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 9\n");
419 status = ddr3_pbs_tx(&dram_info);
420 if (MV_OK != status) {
421 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS TX)\n");
426 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 10\n");
430 } while (freq != dram_info.target_frequency);
432 status = ddr3_dqs_centralization_rx(&dram_info);
433 if (MV_OK != status) {
434 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization RX)\n");
439 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 11\n");
441 status = ddr3_dqs_centralization_tx(&dram_info);
442 if (MV_OK != status) {
443 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization TX)\n");
448 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 12\n");
451 ddr3_set_performance_params(&dram_info);
453 if (dram_info.ecc_ena) {
454 /* Need to SCRUB the DRAM memory area to load U-Boot */
456 dram_info.num_cs = 1;
457 dram_info.cs_ena = 1;
458 mv_sys_xor_init(&dram_info);
459 mv_xor_mem_init(0, scrub_offs, scrub_size, 0xdeadbeef,
462 /* Wait for previous transfer completion */
463 while (mv_xor_state_get(0) != MV_IDLE)
467 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 13\n");
470 /* Return XOR State */
473 #if defined(MV88F78X60)
474 /* Save training results in memeory for resume state */
475 ddr3_save_training(&dram_info);
477 /* Clear ODT always on */
478 ddr3_odt_activate(0);
480 /* Configure Dynamic read ODT */
481 ddr3_odt_read_dynamic_config(&dram_info);
486 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info)
488 u32 twr2wr, trd2rd, trd2wr_wr2rd;
491 DEBUG_MAIN_FULL_C("Max WL Phase: ", dram_info->wl_max_phase, 2);
492 DEBUG_MAIN_FULL_C("Min WL Phase: ", dram_info->wl_min_phase, 2);
493 DEBUG_MAIN_FULL_C("Max RL Phase: ", dram_info->rl_max_phase, 2);
494 DEBUG_MAIN_FULL_C("Min RL Phase: ", dram_info->rl_min_phase, 2);
496 if (dram_info->wl_max_phase < 2)
501 trd2rd = 0x1 + (dram_info->rl_max_phase + 1) / 2 +
502 (dram_info->rl_max_phase + 1) % 2;
504 tmp1 = (dram_info->rl_max_phase - dram_info->wl_min_phase) / 2 +
505 (((dram_info->rl_max_phase - dram_info->wl_min_phase) % 2) >
507 tmp2 = (dram_info->wl_max_phase - dram_info->rl_min_phase) / 2 +
508 ((dram_info->wl_max_phase - dram_info->rl_min_phase) % 2 >
510 trd2wr_wr2rd = (tmp1 >= tmp2) ? tmp1 : tmp2;
516 DEBUG_MAIN_FULL_C("WR 2 WR: ", twr2wr, 2);
517 DEBUG_MAIN_FULL_C("RD 2 RD: ", trd2rd, 2);
518 DEBUG_MAIN_FULL_C("RD 2 WR / WR 2 RD: ", trd2wr_wr2rd, 2);
520 reg = reg_read(REG_SDRAM_TIMING_HIGH_ADDR);
522 reg &= ~(REG_SDRAM_TIMING_H_W2W_MASK << REG_SDRAM_TIMING_H_W2W_OFFS);
523 reg |= ((twr2wr & REG_SDRAM_TIMING_H_W2W_MASK) <<
524 REG_SDRAM_TIMING_H_W2W_OFFS);
526 reg &= ~(REG_SDRAM_TIMING_H_R2R_MASK << REG_SDRAM_TIMING_H_R2R_OFFS);
527 reg &= ~(REG_SDRAM_TIMING_H_R2R_H_MASK <<
528 REG_SDRAM_TIMING_H_R2R_H_OFFS);
529 reg |= ((trd2rd & REG_SDRAM_TIMING_H_R2R_MASK) <<
530 REG_SDRAM_TIMING_H_R2R_OFFS);
531 reg |= (((trd2rd >> 2) & REG_SDRAM_TIMING_H_R2R_H_MASK) <<
532 REG_SDRAM_TIMING_H_R2R_H_OFFS);
534 reg &= ~(REG_SDRAM_TIMING_H_R2W_W2R_MASK <<
535 REG_SDRAM_TIMING_H_R2W_W2R_OFFS);
536 reg &= ~(REG_SDRAM_TIMING_H_R2W_W2R_H_MASK <<
537 REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS);
538 reg |= ((trd2wr_wr2rd & REG_SDRAM_TIMING_H_R2W_W2R_MASK) <<
539 REG_SDRAM_TIMING_H_R2W_W2R_OFFS);
540 reg |= (((trd2wr_wr2rd >> 2) & REG_SDRAM_TIMING_H_R2W_W2R_H_MASK) <<
541 REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS);
543 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);
547 * Perform DDR3 PUP Indirect Write
549 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay)
554 reg |= (1 << REG_PHY_BC_OFFS);
556 reg |= (pup << REG_PHY_PUP_OFFS);
558 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
559 reg |= (phase << REG_PHY_PHASE_OFFS) | delay;
561 if (mode == PUP_WL_MODE)
562 reg |= ((INIT_WL_DELAY + delay) << REG_PHY_DQS_REF_DLY_OFFS);
564 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
565 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR;
566 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
569 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
570 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
571 } while (reg); /* Wait for '0' to mark the end of the transaction */
573 /* If read Leveling mode - need to write to register 3 separetly */
574 if (mode == PUP_RL_MODE) {
578 reg |= (1 << REG_PHY_BC_OFFS);
580 reg |= (pup << REG_PHY_PUP_OFFS);
582 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS);
583 reg |= (INIT_RL_DELAY);
585 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
586 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR;
587 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
590 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
591 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
597 * Perform DDR3 PUP Indirect Read
599 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup)
603 reg = (pup << REG_PHY_PUP_OFFS) |
604 ((0x4 * cs + mode) << REG_PHY_CS_OFFS);
605 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
607 reg |= REG_PHY_REGISTRY_FILE_ACCESS_OP_RD;
608 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */
611 reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
612 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
613 } while (reg); /* Wait for '0' to mark the end of the transaction */
615 return reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR); /* 0x16A0 */
619 * Set training patterns
621 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume)
625 /* Enable SW override - Required for the ECC Pup */
626 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) |
627 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
629 /* [0] = 1 - Enable SW override */
630 /* 0x15B8 - Training SW 2 Register */
631 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
633 reg = (1 << REG_DRAM_TRAINING_AUTO_OFFS);
634 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */
637 #if defined(MV88F78X60) || defined(MV88F672X)
638 ddr3_load_pbs_patterns(dram_info);
640 ddr3_load_dqs_patterns(dram_info);
643 /* Disable SW override - Must be in a different stage */
644 /* [0]=0 - Enable SW override */
645 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
646 reg &= ~(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS);
647 /* 0x15B8 - Training SW 2 Register */
648 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
650 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) |
651 (1 << REG_DRAM_TRAINING_1_TRNBPOINT_OFFS);
652 reg_write(REG_DRAM_TRAINING_1_ADDR, reg);
655 #if defined(MV88F67XX)
656 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0);
659 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0);
661 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR,
662 RESUME_RL_PATTERNS_ADDR);
667 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) |
668 (1 << REG_DRAM_TRAINING_PATTERNS_OFFS);
670 reg = (0x1 << REG_DRAM_TRAINING_CS_OFFS) |
671 (1 << REG_DRAM_TRAINING_PATTERNS_OFFS);
674 reg |= (1 << REG_DRAM_TRAINING_AUTO_OFFS);
676 reg_write(REG_DRAM_TRAINING_ADDR, reg);
680 /* Check if Successful */
681 if (reg_read(REG_DRAM_TRAINING_ADDR) &
682 (1 << REG_DRAM_TRAINING_ERROR_OFFS))
688 #if !defined(MV88F67XX)
690 * Name: ddr3_save_training(MV_DRAM_INFO *dram_info)
691 * Desc: saves the training results to memeory (RL,WL,PBS,Rx/Tx
693 * Args: MV_DRAM_INFO *dram_info
697 void ddr3_save_training(MV_DRAM_INFO *dram_info)
699 u32 val, pup, tmp_cs, cs, i, dq;
702 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;
703 u32 mode_config[MAX_TRAINING_MODE];
705 mode_config[DQS_WR_MODE] = PUP_DQS_WR;
706 mode_config[WL_MODE_] = PUP_WL_MODE;
707 mode_config[RL_MODE_] = PUP_RL_MODE;
708 mode_config[DQS_RD_MODE] = PUP_DQS_RD;
709 mode_config[PBS_TX_DM_MODE] = PUP_PBS_TX_DM;
710 mode_config[PBS_TX_MODE] = PUP_PBS_TX;
711 mode_config[PBS_RX_MODE] = PUP_PBS_RX;
713 /* num of training modes */
714 for (i = 0; i < MAX_TRAINING_MODE; i++) {
715 tmp_cs = dram_info->cs_ena;
717 for (cs = 0; cs < MAX_CS; cs++) {
718 if (tmp_cs & (1 << cs)) {
720 for (pup = 0; pup < dram_info->num_of_total_pups;
722 if (pup == dram_info->num_of_std_pups &&
725 if (i == PBS_TX_DM_MODE) {
727 * Change CS bitmask because
728 * PBS works only with CS0
731 val = ddr3_read_pup_reg(
732 mode_config[i], CS0, pup);
733 } else if (i == PBS_TX_MODE ||
736 * Change CS bitmask because
737 * PBS works only with CS0
740 for (dq = 0; dq <= DQ_NUM;
742 val = ddr3_read_pup_reg(
746 (*sdram_offset) = val;
747 crc += *sdram_offset;
753 val = ddr3_read_pup_reg(
754 mode_config[i], cs, pup);
758 crc += *sdram_offset;
766 *sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
767 crc += *sdram_offset;
770 *sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR);
771 crc += *sdram_offset;
774 sdram_offset = (u32 *)NUM_OF_REGISTER_ADDR;
775 *sdram_offset = regs;
776 DEBUG_SUSPEND_RESUME_S("Training Results CheckSum write= ");
777 DEBUG_SUSPEND_RESUME_D(crc, 8);
778 DEBUG_SUSPEND_RESUME_S("\n");
779 sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;
784 * Name: ddr3_read_training_results()
785 * Desc: Reads the training results from memeory (RL,WL,PBS,Rx/Tx
787 * and writes them to the relevant registers
788 * Args: MV_DRAM_INFO *dram_info
792 int ddr3_read_training_results(void)
794 u32 val, reg, idx, dqs_wr_idx = 0, crc = 0;
795 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR;
796 u32 training_val[RESUME_TRAINING_VALUES_MAX] = { 0 };
797 u32 regs = *((u32 *)NUM_OF_REGISTER_ADDR);
800 * Read Training results & Dunit registers from memory and write
803 for (idx = 0; idx < regs; idx++) {
804 training_val[idx] = *sdram_offset;
805 crc += *sdram_offset;
809 sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR;
811 if ((*sdram_offset) == crc) {
812 DEBUG_SUSPEND_RESUME_S("Training Results CheckSum read PASS= ");
813 DEBUG_SUSPEND_RESUME_D(crc, 8);
814 DEBUG_SUSPEND_RESUME_S("\n");
816 DEBUG_MAIN_S("Wrong Training Results CheckSum\n");
821 * We iterate through all the registers except for the last 2 since
822 * they are Dunit registers (and not PHY registers)
824 for (idx = 0; idx < (regs - 2); idx++) {
825 val = training_val[idx];
826 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */
828 /* Check if the values belongs to the DQS WR */
829 if (reg == PUP_WL_MODE) {
830 /* bit[5:0] in DQS_WR are delay */
831 val = (training_val[dqs_wr_idx++] & 0x3F);
833 * bit[15:10] are DQS_WR delay & bit[9:0] are
836 val = (val << REG_PHY_DQS_REF_DLY_OFFS) |
837 (training_val[idx] & 0x3C003FF);
838 /* Add Request pending and write operation bits */
839 val |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR;
840 } else if (reg == PUP_DQS_WR) {
842 * Do nothing since DQS_WR will be done in PUP_WL_MODE
847 val |= REG_PHY_REGISTRY_FILE_ACCESS_OP_WR;
848 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, val);
850 val = (reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR)) &
851 REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
852 } while (val); /* Wait for '0' to mark the end of the transaction */
855 /* write last 2 Dunit configurations */
856 val = training_val[idx];
857 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, val); /* reg 0x1538 */
858 val = training_val[idx + 1];
859 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, val); /* reg 0x153c */
865 * Name: ddr3_check_if_resume_mode()
866 * Desc: Reads the address (0x3000) of the Resume Magic word (0xDEADB002)
867 * Args: MV_DRAM_INFO *dram_info
869 * Returns: return (magic_word == SUSPEND_MAGIC_WORD)
871 int ddr3_check_if_resume_mode(MV_DRAM_INFO *dram_info, u32 freq)
874 u32 *sdram_offset = (u32 *)BOOT_INFO_ADDR;
876 if (dram_info->reg_dimm != 1) {
878 * Perform write levleling in order initiate the phy with
881 if (MV_OK != ddr3_write_leveling_hw(freq, dram_info)) {
882 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
883 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
887 if (MV_OK != ddr3_load_patterns(dram_info, 1)) {
888 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Loading Patterns)\n");
889 return MV_DDR3_TRAINING_ERR_LOAD_PATTERNS;
892 /* Enable CS0 only for RL */
893 dram_info->cs_ena = 0x1;
895 /* Perform Read levleling in order to get stable memory */
896 if (MV_OK != ddr3_read_leveling_hw(freq, dram_info)) {
897 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Hw)\n");
898 return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
901 /* Back to relevant CS */
902 dram_info->cs_ena = ddr3_get_cs_ena_from_reg();
904 magic_word = *sdram_offset;
905 return magic_word == SUSPEND_MAGIC_WORD;
909 * Name: ddr3_training_suspend_resume()
910 * Desc: Execute the Resume state
911 * Args: MV_DRAM_INFO *dram_info
913 * Returns: return (magic_word == SUSPEND_MAGIC_WORD)
915 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info)
921 if (MV_OK != ddr3_read_training_results())
924 /* Reset read FIFO */
925 reg = reg_read(REG_DRAM_TRAINING_ADDR);
927 /* Start Auto Read Leveling procedure */
928 reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
929 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */
931 reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
932 reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
933 (1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
935 /* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
936 /* 0x15B8 - Training SW 2 Register */
937 reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
941 reg = reg_read(REG_DRAM_TRAINING_ADDR);
942 /* Clear Auto Read Leveling procedure */
943 reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
944 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */
946 /* Return to target frequency */
947 freq = dram_info->target_frequency;
949 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, dram_info)) {
950 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs Low2High)\n");
951 return MV_DDR3_TRAINING_ERR_DFS_H2L;
954 if (dram_info->ecc_ena) {
955 /* Scabbling the RL area pattern and the training area */
957 dram_info->num_cs = 1;
958 dram_info->cs_ena = 1;
959 mv_sys_xor_init(dram_info);
960 mv_xor_mem_init(0, RESUME_RL_PATTERNS_ADDR,
961 RESUME_RL_PATTERNS_SIZE, 0xFFFFFFFF, 0xFFFFFFFF);
963 /* Wait for previous transfer completion */
965 while (mv_xor_state_get(0) != MV_IDLE)
968 /* Return XOR State */
976 void ddr3_print_freq(u32 freq)
1018 printf("Current frequency is: %dMHz\n", tmp_freq);
1021 int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
1022 u32 *max, u32 *cs_max)
1029 for (cs = 0; cs < MAX_CS; cs++) {
1030 if ((cs_enable & (1 << cs)) == 0)
1033 delay = ((reg >> (cs * 8)) & 0x1F);
1047 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
1050 u32 pup, reg, phase;
1055 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) {
1056 reg = ddr3_read_pup_reg(PUP_RL_MODE, cs, pup);
1057 phase = ((reg >> 8) & 0x7);
1069 int ddr3_odt_activate(int activate)
1073 mask = (1 << REG_DUNIT_ODT_CTRL_OVRD_OFFS) |
1074 (1 << REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS);
1075 /* {0x0000149C} - DDR Dunit ODT Control Register */
1076 reg = reg_read(REG_DUNIT_ODT_CTRL_ADDR);
1082 reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg);
1087 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info)
1089 u32 min_read_sample_delay, max_read_sample_delay, max_rl_phase;
1090 u32 min, max, cs_max;
1093 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
1094 cs_ena = ddr3_get_cs_ena_from_reg();
1096 /* Get minimum and maximum of read sample delay of all CS */
1097 ddr3_get_min_max_read_sample_delay(cs_ena, reg, &min_read_sample_delay,
1098 &max_read_sample_delay, &cs_max);
1101 * Get minimum and maximum read leveling phase which belongs to the
1102 * maximal read sample delay
1104 ddr3_get_min_max_rl_phase(dram_info, &min, &max, cs_max);
1107 /* DDR ODT Timing (Low) Register calculation */
1108 reg = reg_read(REG_ODT_TIME_LOW_ADDR);
1109 reg &= ~(0x1FF << REG_ODT_ON_CTL_RD_OFFS);
1110 reg |= (((min_read_sample_delay - 1) & 0xF) << REG_ODT_ON_CTL_RD_OFFS);
1111 reg |= (((max_read_sample_delay + 4 + (((max_rl_phase + 1) / 2) + 1)) &
1112 0x1F) << REG_ODT_OFF_CTL_RD_OFFS);
1113 reg_write(REG_ODT_TIME_LOW_ADDR, reg);